src/drivers/ati/ragexl/xlinit.c

   1 /*
   2  *  ATI Rage XL Initialization. Support for Xpert98 and Victoria
   3  *  PCI cards.
   4  *
   5  *  Copyright (C) 2002 MontaVista Software Inc.
   6  *  Author: MontaVista Software, Inc.
   7  *              stevel@mvista.com or source@mvista.com
   8  *  Copyright (C) 2004 Tyan Computer.
   9  *  Auther: Yinghai Lu   yhlu@tyan.com
  10  *         move to coreboot
  11  * This code is distributed without warranty under the GPL v2 (see COPYING) *
  12  */
  13 #include <delay.h>
  14 #include <stdlib.h>
  15 #include <string.h>
  16 #include <arch/io.h>
  17
  18 #include <console/console.h>
  19 #include <device/device.h>
  20 #include <device/pci.h>
  21 #include <device/pci_ids.h>
  22 #include <device/pci_ops.h>
  23
  24 #if CONFIG_CONSOLE_BTEXT==1
  25
  26 #define PLL_CRTC_DECODE 0
  27 #define SUPPORT_8_BPP_ABOVE 0
  28
  29 #include "fb.h"
  30 #include "fbcon.h"
  31
  32 struct aty_cmap_regs {
  33         u8 windex;
  34         u8 lut;
  35         u8 mask;
  36         u8 rindex;
  37         u8 cntl;
  38 };
  39
  40 #include <console/btext.h>
  41
  42 #endif /*CONFIG_CONSOLE_BTEXT*/
  43
  44 #include "mach64.h"
  45
  46 #include "atyfb.h"
  47
  48 #include "mach64_ct.c"
  49
  50 #define MPLL_GAIN       0xad
  51 #define VPLL_GAIN       0xd5
  52
  53 #define HAS_VICTORIA 0
  54
  55 enum {
  56 #if HAS_VICTORIA==1
  57         VICTORIA = 0,
  58         XPERT98,
  59 #else
  60         XPERT98=0,
  61 #endif
  62         NUM_XL_CARDS
  63 };
  64
  65 //static struct aty_pll_ops aty_pll_ct;
  66
  67 #define DEFAULT_CARD XPERT98
  68 static int xl_card = DEFAULT_CARD;
  69
  70 static const struct xl_card_cfg_t {
  71         int ref_crystal; // 10^4 Hz
  72         int mem_type;
  73         int mem_size;
  74         u32 mem_cntl;
  75         u32 ext_mem_cntl;
  76         u32 mem_addr_config;
  77         u32 bus_cntl;
  78         u32 dac_cntl;
  79         u32 hw_debug;
  80         u32 custom_macro_cntl;
  81         u8  dll2_cntl;
  82         u8  pll_yclk_cntl;
  83 } card_cfg[NUM_XL_CARDS] = {
  84 #if HAS_VICTORIA==1
  85         // VICTORIA
  86         {       2700, SDRAM, 0x800000,
  87                 0x10757A3B, 0x64000C81, 0x00110202, 0x7b33A040,
  88                 0x82010102, 0x48803800, 0x005E0179,
  89                 0x50, 0x25
  90         },
  91 #endif
  92         // XPERT98
  93         {       1432,  WRAM, 0x800000,
  94                 0x00165A2B, 0xE0000CF1, 0x00200213, 0x7333A001,
  95                 0x8000000A, 0x48833800, 0x007F0779,
  96                 0x10, 0x19
  97         }
  98 };
  99
 100 typedef struct {
 101         u8 lcd_reg;
 102         u32 val;
 103 } lcd_tbl_t;
 104
 105 static const lcd_tbl_t lcd_tbl[] = {
 106         { 0x01, 0x000520C0 },
 107         { 0x08, 0x02000408 },
 108         { 0x03, 0x00000F00 },
 109         { 0x00, 0x00000000 },
 110         { 0x02, 0x00000000 },
 111         { 0x04, 0x00000000 },
 112         { 0x05, 0x00000000 },
 113         { 0x06, 0x00000000 },
 114         { 0x33, 0x00000000 },
 115         { 0x34, 0x00000000 },
 116         { 0x35, 0x00000000 },
 117         { 0x36, 0x00000000 },
 118         { 0x37, 0x00000000 }
 119 };
 120
 121 static inline u32 aty_ld_lcd(u8 lcd_reg, struct fb_info_aty *info)
 122 {
 123         aty_st_8(LCD_INDEX, lcd_reg, info);
 124         return aty_ld_le32(LCD_DATA, info);
 125 }
 126
 127 static inline void aty_st_lcd(u8 lcd_reg, u32 val,
 128                               struct fb_info_aty *info)
 129 {
 130         aty_st_8(LCD_INDEX, lcd_reg, info);
 131         aty_st_le32(LCD_DATA, val, info);
 132 }
 133
 134 static void reset_gui(struct fb_info_aty *info)
 135 {
 136         aty_st_8(GEN_TEST_CNTL+1, 0x01, info);
 137         aty_st_8(GEN_TEST_CNTL+1, 0x00, info);
 138         aty_st_8(GEN_TEST_CNTL+1, 0x02, info);
 139         mdelay(5);
 140 }
 141
 142
 143 static void reset_sdram(struct fb_info_aty *info)
 144 {
 145         u8 temp;
 146
 147         temp = aty_ld_8(EXT_MEM_CNTL, info);
 148         temp |= 0x02;
 149         aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_SDRAM_RESET = 1b
 150         temp |= 0x08;
 151         aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_CYC_TEST    = 10b
 152         temp |= 0x0c;
 153         aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_CYC_TEST    = 11b
 154         mdelay(5);
 155         temp &= 0xf3;
 156         aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_CYC_TEST    = 00b
 157         temp &= 0xfd;
 158         aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_SDRAM_REST  = 0b
 159         mdelay(5);
 160 }
 161
 162 static void init_dll(struct fb_info_aty *info)
 163 {
 164         // enable DLL
 165         aty_st_pll(PLL_GEN_CNTL,
 166                    aty_ld_pll(PLL_GEN_CNTL, info) & 0x7f,
 167                    info);
 168
 169         // reset DLL
 170         aty_st_pll(DLL_CNTL, 0x82, info);
 171         aty_st_pll(DLL_CNTL, 0xE2, info);
 172         mdelay(5);
 173         aty_st_pll(DLL_CNTL, 0x82, info);
 174         mdelay(6);
 175 }
 176
 177 static void reset_clocks(struct fb_info_aty *info, struct pll_ct *pll,
 178                          int hsync_enb)
 179 {
 180         reset_gui(info);
 181         aty_st_pll(MCLK_FB_DIV, pll->mclk_fb_div, info);
 182         aty_st_pll(SCLK_FB_DIV, pll->sclk_fb_div, info);
 183
 184         mdelay(15);
 185         init_dll(info);
 186         aty_st_8(GEN_TEST_CNTL+1, 0x00, info);
 187         mdelay(5);
 188         aty_st_8(CRTC_GEN_CNTL+3, 0x04, info);
 189         mdelay(6);
 190         reset_sdram(info);
 191         aty_st_8(CRTC_GEN_CNTL+3,
 192                  hsync_enb ? 0x00 : 0x04, info);
 193
 194         aty_st_pll(SPLL_CNTL2, pll->spll_cntl2, info);
 195         aty_st_pll(PLL_GEN_CNTL, pll->pll_gen_cntl, info);
 196         aty_st_pll(PLL_VCLK_CNTL, pll->pll_vclk_cntl, info);
 197 }
 198
 199 static int atyfb_xl_init(struct fb_info_aty *info)
 200 {
 201         int i, err;
 202         u32 temp;
 203         union aty_pll pll;
 204         const struct xl_card_cfg_t * card = &card_cfg[xl_card];
 205
 206         aty_st_8(CONFIG_STAT0, 0x85, info);
 207         mdelay(10);
 208
 209         /*
 210          * The following needs to be set before the call
 211          * to var_to_pll() below. They'll be re-set again
 212          * to the same values in aty_init().
 213          */
 214         info->ref_clk_per = 100000000UL/card->ref_crystal;
 215         info->ram_type = card->mem_type;
 216         info->total_vram = card->mem_size;
 217 #if HAS_VICTORIA == 1
 218         if (xl_card == VICTORIA) {
 219                 // the MCLK, XCLK are 120MHz on victoria card
 220                 info->mclk_per = 1000000/120;
 221                 info->xclk_per = 1000000/120;
 222                 info->features &= ~M64F_MFB_TIMES_4;
 223         }
 224 #endif
 225
 226         /*
 227          * Calculate mclk and xclk dividers, etc. The passed
 228          * pixclock and bpp values don't matter yet, the vclk
 229          * isn't programmed until later.
 230          */
 231         if ((err = aty_var_to_pll_ct(info, 39726, 8, &pll))) return err;
 232 //        if ((err = aty_pll_ct.var_to_pll(info, 39726, 8, &pll))) return err;
 233
 234
 235         aty_st_pll(LVDS_CNTL0, 0x00, info);
 236         aty_st_pll(DLL2_CNTL, card->dll2_cntl, info);
 237         aty_st_pll(V2PLL_CNTL, 0x10, info);
 238         aty_st_pll(MPLL_CNTL, MPLL_GAIN, info);
 239         aty_st_pll(VPLL_CNTL, VPLL_GAIN, info);
 240         aty_st_pll(PLL_VCLK_CNTL, 0x00, info);
 241         aty_st_pll(VFC_CNTL, 0x1B, info);
 242         aty_st_pll(PLL_REF_DIV, pll.ct.pll_ref_div, info);
 243         aty_st_pll(PLL_EXT_CNTL, pll.ct.pll_ext_cntl, info);
 244         aty_st_pll(SPLL_CNTL2, 0x03, info);
 245         aty_st_pll(PLL_GEN_CNTL, 0x44, info);
 246
 247         reset_clocks(info, &pll.ct, 0);
 248         mdelay(10);
 249
 250         aty_st_pll(VCLK_POST_DIV, 0x03, info);
 251         aty_st_pll(VCLK0_FB_DIV, 0xDA, info);
 252         aty_st_pll(VCLK_POST_DIV, 0x0F, info);
 253         aty_st_pll(VCLK1_FB_DIV, 0xF5, info);
 254         aty_st_pll(VCLK_POST_DIV, 0x3F, info);
 255         aty_st_pll(PLL_EXT_CNTL, 0x40 | pll.ct.pll_ext_cntl, info);
 256         aty_st_pll(VCLK2_FB_DIV, 0x00, info);
 257         aty_st_pll(VCLK_POST_DIV, 0xFF, info);
 258         aty_st_pll(PLL_EXT_CNTL, 0xC0 | pll.ct.pll_ext_cntl, info);
 259         aty_st_pll(VCLK3_FB_DIV, 0x00, info);
 260
 261         aty_st_8(BUS_CNTL, 0x01, info);
 262         aty_st_le32(BUS_CNTL, card->bus_cntl | 0x08000000, info);
 263
 264         aty_st_le32(CRTC_GEN_CNTL, 0x04000200, info);
 265         aty_st_le16(CONFIG_STAT0, 0x0020, info);
 266         aty_st_le32(MEM_CNTL, 0x10151A33, info);
 267         aty_st_le32(EXT_MEM_CNTL, 0xE0000C01, info);
 268         aty_st_le16(CRTC_GEN_CNTL+2, 0x0000, info);
 269         aty_st_le32(DAC_CNTL, card->dac_cntl, info);
 270         aty_st_le16(GEN_TEST_CNTL, 0x0100, info);
 271         aty_st_le32(CUSTOM_MACRO_CNTL, 0x003C0171, info);
 272         aty_st_le32(MEM_BUF_CNTL, 0x00382848, info);
 273
 274         aty_st_le32(HW_DEBUG, card->hw_debug, info);
 275         aty_st_le16(MEM_ADDR_CONFIG, 0x0000, info);
 276         aty_st_le16(GP_IO+2, 0x0000, info);
 277         aty_st_le16(GEN_TEST_CNTL, 0x0000, info);
 278         aty_st_le16(EXT_DAC_REGS+2, 0x0000, info);
 279         aty_st_le32(CRTC_INT_CNTL, 0x00000000, info);
 280         aty_st_le32(TIMER_CONFIG, 0x00000000, info);
 281         aty_st_le32(0xEC, 0x00000000, info);
 282         aty_st_le32(0xFC, 0x00000000, info);
 283
 284         for (i=0; i<ARRAY_SIZE(lcd_tbl); i++) {
 285                 aty_st_lcd(lcd_tbl[i].lcd_reg, lcd_tbl[i].val, info);
 286         }
 287
 288         aty_st_le16(CONFIG_STAT0, 0x00A4, info);
 289         mdelay(10);
 290
 291         aty_st_8(BUS_CNTL+1, 0xA0, info);
 292         mdelay(10);
 293
 294         reset_clocks(info, &pll.ct, 1);
 295         mdelay(10);
 296
 297         // something about power management
 298         aty_st_8(LCD_INDEX, 0x08, info);
 299         aty_st_8(LCD_DATA, 0x0A, info);
 300         aty_st_8(LCD_INDEX, 0x08, info);
 301         aty_st_8(LCD_DATA+3, 0x02, info);
 302         aty_st_8(LCD_INDEX, 0x08, info);
 303         aty_st_8(LCD_DATA, 0x0B, info);
 304         mdelay(2);
 305
 306         // enable display requests, enable CRTC
 307         aty_st_8(CRTC_GEN_CNTL+3, 0x02, info);
 308         // disable display
 309         aty_st_8(CRTC_GEN_CNTL, 0x40, info);
 310         // disable display requests, disable CRTC
 311         aty_st_8(CRTC_GEN_CNTL+3, 0x04, info);
 312         mdelay(10);
 313
 314         aty_st_pll(PLL_YCLK_CNTL, 0x25, info);
 315
 316         aty_st_le16(CUSTOM_MACRO_CNTL, 0x0179, info);
 317         aty_st_le16(CUSTOM_MACRO_CNTL+2, 0x005E, info);
 318         aty_st_le16(CUSTOM_MACRO_CNTL+2, card->custom_macro_cntl>>16, info);
 319         aty_st_8(CUSTOM_MACRO_CNTL+1,
 320                  (card->custom_macro_cntl>>8) & 0xff, info);
 321
 322         aty_st_le32(MEM_ADDR_CONFIG, card->mem_addr_config, info);
 323         aty_st_le32(MEM_CNTL, card->mem_cntl, info);
 324         aty_st_le32(EXT_MEM_CNTL, card->ext_mem_cntl, info);
 325
 326         aty_st_8(CONFIG_STAT0, 0xA0 | card->mem_type, info);
 327
 328         aty_st_pll(PLL_YCLK_CNTL, 0x01, info);
 329         mdelay(15);
 330         aty_st_pll(PLL_YCLK_CNTL, card->pll_yclk_cntl, info);
 331         mdelay(1);
 332
 333         reset_clocks(info, &pll.ct, 0);
 334         mdelay(50);
 335         reset_clocks(info, &pll.ct, 0);
 336         mdelay(50);
 337
 338         // enable extended register block
 339         aty_st_8(BUS_CNTL+3, 0x7B, info);
 340         mdelay(1);
 341         // disable extended register block
 342         aty_st_8(BUS_CNTL+3, 0x73, info);
 343
 344         aty_st_8(CONFIG_STAT0, 0x80 | card->mem_type, info);
 345
 346         // disable display requests, disable CRTC
 347         aty_st_8(CRTC_GEN_CNTL+3, 0x04, info);
 348         // disable mapping registers in VGA aperture
 349         aty_st_8(CONFIG_CNTL, aty_ld_8(CONFIG_CNTL, info) & ~0x04, info);
 350         mdelay(50);
 351         // enable display requests, enable CRTC
 352         aty_st_8(CRTC_GEN_CNTL+3, 0x02, info);
 353
 354         // make GPIO's 14,15,16 all inputs
 355         aty_st_8(LCD_INDEX, 0x07, info);
 356         aty_st_8(LCD_DATA+3, 0x00, info);
 357
 358         // enable the display
 359         aty_st_8(CRTC_GEN_CNTL, 0x00, info);
 360         mdelay(17);
 361         // reset the memory controller
 362         aty_st_8(GEN_TEST_CNTL+1, 0x02, info);
 363         mdelay(15);
 364         aty_st_8(GEN_TEST_CNTL+1, 0x00, info);
 365         mdelay(30);
 366
 367         // enable extended register block
 368         aty_st_8(BUS_CNTL+3,
 369                  (u8)(aty_ld_8(BUS_CNTL+3, info) | 0x08),
 370                  info);
 371         // set FIFO size to 512 (PIO)
 372         aty_st_le32(GUI_CNTL,
 373                     aty_ld_le32(GUI_CNTL, info) & ~0x3,
 374                     info);
 375
 376         // enable CRT and disable lcd
 377         aty_st_8(LCD_INDEX, 0x01, info);
 378         temp = aty_ld_le32(LCD_DATA, info);
 379         temp = (temp | 0x01) & ~0x02;
 380         aty_st_le32(LCD_DATA, temp, info);
 381
 382         return 0;
 383 }
 384
 385 static char m64n_xl_33[] = "3D RAGE (XL PCI-33MHz)";
 386 static char m64n_xl_66[] = "3D RAGE (XL PCI-66MHz)";
 387
 388
 389 #if CONFIG_CONSOLE_BTEXT==1
 390 static void aty_set_crtc(const struct fb_info_aty *info,
 391                          const struct crtc *crtc);
 392 static int aty_var_to_crtc(const struct fb_info_aty *info,
 393                            const struct fb_var_screeninfo *var,
 394                            struct crtc *crtc);
 395 #if PLL_CRTC_DECODE==1
 396 static int aty_crtc_to_var(const struct crtc *crtc,
 397                            struct fb_var_screeninfo *var);
 398 #endif
 399
 400 static void atyfb_set_par(const struct atyfb_par *par,
 401                           struct fb_info_aty *info);
 402 static int atyfb_decode_var(const struct fb_var_screeninfo *var,
 403                             struct atyfb_par *par,
 404                             const struct fb_info_aty *info);
 405 #if PLL_CRTC_DECODE==1
 406 static int atyfb_encode_var(struct fb_var_screeninfo *var,
 407                             const struct atyfb_par *par,
 408                             const struct fb_info_aty *info);
 409 #endif
 410
 411 static void do_install_cmap(int con, struct fb_info_aty *info);
 412
 413 #if 0
 414 static u32 default_vram  = 0;
 415 #endif
 416
 417 unsigned char color_table[] = { 0, 4, 2, 6, 1, 5, 3, 7,
 418                                        8,12,10,14, 9,13,11,15 };
 419 #if 0
 420 /* the default colour table, for VGA+ colour systems */
 421 int default_red[] = {0x00,0xaa,0x00,0xaa,0x00,0xaa,0x00,0xaa,
 422     0x55,0xff,0x55,0xff,0x55,0xff,0x55,0xff};
 423 int default_grn[] = {0x00,0x00,0xaa,0x55,0x00,0x00,0xaa,0xaa,
 424     0x55,0x55,0xff,0xff,0x55,0x55,0xff,0xff};
 425 int default_blu[] = {0x00,0x00,0x00,0x00,0xaa,0xaa,0xaa,0xaa,
 426     0x55,0x55,0x55,0x55,0xff,0xff,0xff,0xff};
 427 #endif
 428
 429 struct fb_var_screeninfo default_var = {
 430         /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
 431         640, 480, 640, 480, 0, 0, 8, 0,
 432         {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
 433         0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
 434         0, FB_VMODE_NONINTERLACED
 435 };
 436
 437 #endif /*CONFIG_CONSOLE_BTEXT*/
 438
 439 static struct {
 440         u16 pci_id, chip_type;
 441         u8 rev_mask, rev_val;
 442         const char *name;
 443         int pll, mclk, xclk;
 444         u32 features;
 445 } aty_chips[] = {
 446         /* 3D RAGE XL PCI-66/BGA */
 447         { 0x474f, 0x474f, 0x00, 0x00, m64n_xl_66, 230, 83, 63, M64F_GT | M64F_INTEGRATED | M64F_RESET_3D | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL | M64F_EXTRA_BRIGHT | M64F_XL_DLL | M64F_MFB_TIMES_4 },
 448         /* 3D RAGE XL PCI-33/BGA */
 449         { 0x4752, 0x4752, 0x00, 0x00, m64n_xl_33, 230, 83, 63, M64F_GT | M64F_INTEGRATED | M64F_RESET_3D | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL | M64F_EXTRA_BRIGHT | M64F_XL_DLL | M64F_MFB_TIMES_4 },
 450 };
 451 #if CONFIG_CONSOLE_BTEXT==1
 452 static void aty_calc_mem_refresh(struct fb_info_aty *info, u16 id, int xclk)
 453 {
 454         int i, size;
 455 #if 0
 456         const int ragepro_tbl[] = {
 457                 44, 50, 55, 66, 75, 80, 100
 458         };
 459 #endif
 460         const int ragexl_tbl[] = {
 461                 50, 66, 75, 83, 90, 95, 100, 105,
 462                 110, 115, 120, 125, 133, 143, 166
 463         };
 464         const int *refresh_tbl;
 465 #if 0
 466         if (IS_XL(id)) {
 467 #endif
 468                 refresh_tbl = ragexl_tbl;
 469                 size = sizeof(ragexl_tbl)/sizeof(int);
 470 #if 0
 471         } else {
 472                 refresh_tbl = ragepro_tbl;
 473                 size = sizeof(ragepro_tbl)/sizeof(int);
 474         }
 475 #endif
 476
 477         for (i=0; i < size; i++) {
 478                 if (xclk < refresh_tbl[i])
 479                         break;
 480         }
 481
 482         info->mem_refresh_rate = i;
 483 }
 484 #endif /*CONFIG_CONSOLE_BTEXT */
 485 static void ati_ragexl_init(device_t dev)
 486 {
 487         u32 chip_id;
 488         int j;
 489         u16 type;
 490         u8 rev;
 491         const char *chipname = NULL;
 492 #if CONFIG_CONSOLE_BTEXT
 493         u32 i;
 494         const char *xtal;
 495 #endif
 496         int pll, mclk, xclk;
 497
 498 #if CONFIG_CONSOLE_BTEXT==1
 499
 500 #if 0
 501         int gtb_memsize, k;
 502 #endif
 503
 504         struct fb_var_screeninfo var;
 505 #if 0
 506         struct display *disp;
 507 #endif
 508
 509 #if 0
 510         u8 pll_ref_div;
 511 #endif
 512
 513 #endif /*CONFIG_CONSOLE_BTEXT==1 */
 514
 515         struct fb_info_aty *info;
 516         struct fb_info_aty info_t;
 517         struct resource *res;
 518         info = &info_t;
 519
 520 #define USE_AUX_REG 1
 521
 522
 523         res = dev->resource_list;
 524         if(res->flags & IORESOURCE_IO) {
 525                 res = res->next;
 526         }
 527
 528 #if CONFIG_CONSOLE_BTEXT==1
 529         info->frame_buffer = res->base;
 530 #endif /* CONFIG_CONSOLE_BTEXT */
 531
 532 #if USE_AUX_REG==0
 533         info->ati_regbase = res->base+0x7ff000+0xc00;
 534 #else
 535         /* Fix this to look for the correct index. */
 536         //if (dev->resource_list && dev->resource_list->next)
 537         res = dev->resource_list->next->next;
 538         if(res->flags & IORESOURCE_MEM) {
 539                 info->ati_regbase = res->base+0x400; //using auxiliary register
 540         }
 541
 542 #endif
 543
 544 #if CONFIG_CONSOLE_BTEXT==1
 545         info->aty_cmap_regs = (struct aty_cmap_regs *)(info->ati_regbase+0xc0);
 546 #endif
 547
 548 #if 0
 549         printk(BIOS_DEBUG, "ati_regbase = 0x%08x, frame_buffer = 0x%08x\n", info->ati_regbase, info->frame_buffer);
 550 #endif
 551
 552         chip_id = aty_ld_le32(CONFIG_CHIP_ID, info);
 553         type = chip_id & CFG_CHIP_TYPE;
 554         rev = (chip_id & CFG_CHIP_REV)>>24;
 555         for (j = 0; j < ARRAY_SIZE(aty_chips); j++)
 556                 if (type == aty_chips[j].chip_type &&
 557                         (rev & aty_chips[j].rev_mask) == aty_chips[j].rev_val) {
 558                         chipname = aty_chips[j].name;
 559                         pll = aty_chips[j].pll;
 560                         mclk = aty_chips[j].mclk;
 561                         xclk = aty_chips[j].xclk;
 562                         info->features = aty_chips[j].features;
 563                         goto found;
 564         }
 565         printk(BIOS_SPEW, "ati_ragexl_init: Unknown mach64 0x%04x rev 0x%04x\n", type, rev);
 566         return ;
 567
 568 found:
 569         printk(BIOS_INFO, "ati_ragexl_init: %s [0x%04x rev 0x%02x]\n", chipname, type, rev);
 570 #if 0
 571         if (M64_HAS(INTEGRATED)) {
 572                 /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
 573                 if (mclk == 67 && info->ram_type < SDRAM)
 574                         mclk = 63;
 575         }
 576 #endif
 577 #if CONFIG_CONSOLE_BTEXT==1
 578         aty_calc_mem_refresh(info, type, xclk);
 579 #endif /* CONFIG_CONSOLE_BTEXT */
 580
 581         info->pll_per = 1000000/pll;
 582         info->mclk_per = 1000000/mclk;
 583         info->xclk_per = 1000000/xclk;
 584
 585 //        info->dac_ops = &aty_dac_ct;
 586 //        info->pll_ops = &aty_pll_ct;
 587         info->bus_type = PCI;
 588
 589
 590         atyfb_xl_init(info);
 591
 592 #if CONFIG_CONSOLE_BTEXT==1
 593
 594         info->ram_type = (aty_ld_le32(CONFIG_STAT0, info) & 0x07);
 595
 596         info->ref_clk_per = 1000000000000ULL/14318180;
 597         xtal = "14.31818";
 598 #if 0
 599         if (M64_HAS(GTB_DSP) && (pll_ref_div = aty_ld_pll(PLL_REF_DIV, info))) {
 600                 int diff1, diff2;
 601                 diff1 = 510*14/pll_ref_div-pll;
 602                 diff2 = 510*29/pll_ref_div-pll;
 603                 if (diff1 < 0)
 604                         diff1 = -diff1;
 605                 if (diff2 < 0)
 606                         diff2 = -diff2;
 607                 if (diff2 < diff1) {
 608                         info->ref_clk_per = 1000000000000ULL/29498928;
 609                         xtal = "29.498928";
 610                 }
 611         }
 612 #endif
 613
 614     i = aty_ld_le32(MEM_CNTL, info);
 615 #if 0
 616     gtb_memsize = M64_HAS(GTB_DSP);
 617     if (gtb_memsize)  // We have
 618 #endif
 619         switch (i & 0xF) {      /* 0xF used instead of MEM_SIZE_ALIAS */
 620             case MEM_SIZE_512K:
 621                 info->total_vram = 0x80000;
 622                 break;
 623             case MEM_SIZE_1M:
 624                 info->total_vram = 0x100000;
 625                 break;
 626             case MEM_SIZE_2M_GTB:
 627                 info->total_vram = 0x200000;
 628                 break;
 629             case MEM_SIZE_4M_GTB:
 630                 info->total_vram = 0x400000;
 631                 break;
 632             case MEM_SIZE_6M_GTB:
 633                 info->total_vram = 0x600000;
 634                 break;
 635             case MEM_SIZE_8M_GTB:
 636                 info->total_vram = 0x800000;
 637                 break;
 638             default:
 639                 info->total_vram = 0x80000;
 640         }
 641 #if 0
 642     else
 643         switch (i & MEM_SIZE_ALIAS) {
 644             case MEM_SIZE_512K:
 645                 info->total_vram = 0x80000;
 646                 break;
 647             case MEM_SIZE_1M:
 648                 info->total_vram = 0x100000;
 649                 break;
 650             case MEM_SIZE_2M:
 651                 info->total_vram = 0x200000;
 652                 break;
 653             case MEM_SIZE_4M:
 654                 info->total_vram = 0x400000;
 655                 break;
 656             case MEM_SIZE_6M:
 657                 info->total_vram = 0x600000;
 658                 break;
 659             case MEM_SIZE_8M:
 660                 info->total_vram = 0x800000;
 661                 break;
 662             default:
 663                 info->total_vram = 0x80000;
 664        }
 665 #endif
 666
 667     if (M64_HAS(MAGIC_VRAM_SIZE)) {
 668         if (aty_ld_le32(CONFIG_STAT1, info) & 0x40000000)
 669           info->total_vram += 0x400000;
 670     }
 671 #if 0
 672     if (default_vram) {
 673         info->total_vram = default_vram*1024;
 674         i = i & ~(gtb_memsize ? 0xF : MEM_SIZE_ALIAS);
 675         if (info->total_vram <= 0x80000)
 676             i |= MEM_SIZE_512K;
 677         else if (info->total_vram <= 0x100000)
 678             i |= MEM_SIZE_1M;
 679         else if (info->total_vram <= 0x200000)
 680             i |= gtb_memsize ? MEM_SIZE_2M_GTB : MEM_SIZE_2M;
 681         else if (info->total_vram <= 0x400000)
 682             i |= gtb_memsize ? MEM_SIZE_4M_GTB : MEM_SIZE_4M;
 683         else if (info->total_vram <= 0x600000)
 684             i |= gtb_memsize ? MEM_SIZE_6M_GTB : MEM_SIZE_6M;
 685         else
 686             i |= gtb_memsize ? MEM_SIZE_8M_GTB : MEM_SIZE_8M;
 687         aty_st_le32(MEM_CNTL, i, info);
 688     }
 689 #endif
 690
 691     /* Clear the video memory */
 692 //    fb_memset((void *)info->frame_buffer, 0, info->total_vram);
 693 #if 0
 694         disp = &info->disp;
 695
 696 //    strcpy(info->fb_info.modename, atyfb_name);
 697     info->fb_info.node = -1;
 698 //    info->fb_info.fbops = &atyfb_ops;
 699     info->fb_info.disp = disp;
 700 //    strcpy(info->fb_info.fontname, fontname);
 701     info->fb_info.changevar = NULL;
 702 //    info->fb_info.switch_con = &atyfbcon_switch;
 703 //    info->fb_info.updatevar = &atyfbcon_updatevar;
 704 //    info->fb_info.blank = &atyfbcon_blank;
 705     info->fb_info.flags = FBINFO_FLAG_DEFAULT;
 706 #endif
 707         var = default_var;
 708
 709 #if 0
 710     if (noaccel)  // We has noaccel in default
 711         var.accel_flags &= ~FB_ACCELF_TEXT;
 712     else
 713         var.accel_flags |= FB_ACCELF_TEXT;
 714 #endif
 715
 716     if (var.yres == var.yres_virtual) {
 717         u32 vram = info->total_vram ;
 718         var.yres_virtual = ((vram * 8) / var.bits_per_pixel) / var.xres_virtual;
 719         if (var.yres_virtual < var.yres)
 720                 var.yres_virtual = var.yres;
 721     }
 722
 723     if (atyfb_decode_var(&var, &info->default_par, info)) {
 724 #if 0
 725         printk(BIOS_DEBUG, "atyfb: can't set default video mode\n");
 726 #endif
 727         return ;
 728     }
 729 #if 0
 730     for (j = 0; j < 16; j++) {
 731         k = color_table[j];
 732         info->palette[j].red = default_red[k];
 733         info->palette[j].green = default_grn[k];
 734         info->palette[j].blue = default_blu[k];
 735     }
 736 #endif
 737
 738 #if 0
 739     if (curblink && M64_HAS(INTEGRATED)) {
 740         info->cursor = aty_init_cursor(info);
 741         if (info->cursor) {
 742             info->dispsw.cursor = atyfb_cursor;
 743             info->dispsw.set_font = atyfb_set_font;
 744         }
 745     }
 746 #endif
 747
 748 #if PLL_CRTC_DECODE==1
 749         atyfb_set_var(&var, -1, &info->fb_info);
 750 #else
 751             atyfb_set_par(&info->default_par, info);
 752 //            do_install_cmap(-1, &info->fb_info);
 753             do_install_cmap(-1, info);
 754 #endif
 755
 756 #if PLL_CRTC_DECODE==1
 757
 758     printk(BIOS_SPEW, "framebuffer=0x%08x, width=%d, height=%d, bpp=%d, pitch=%d\n",info->frame_buffer,
 759                          (((info->current_par.crtc.h_tot_disp>>16) & 0xff)+1)*8,
 760                          ((info->current_par.crtc.v_tot_disp>>16) & 0x7ff)+1,
 761                          info->current_par.crtc.bpp,
 762                          info->current_par.crtc.vxres*info->default_par.crtc.bpp/8
 763                         );
 764  btext_setup_display(
 765                          (((info->current_par.crtc.h_tot_disp>>16) & 0xff)+1)*8,
 766                          ((info->current_par.crtc.v_tot_disp>>16) & 0x7ff)+1,
 767                          info->current_par.crtc.bpp,
 768                          info->current_par.crtc.vxres*info->current_par.crtc.bpp/8,info->frame_buffer);
 769 #else
 770     printk(BIOS_SPEW, "framebuffer=0x%08x, width=%d, height=%d, bpp=%d, pitch=%d\n",info->frame_buffer,
 771                          (((info->default_par.crtc.h_tot_disp>>16) & 0xff)+1)*8,
 772                          ((info->default_par.crtc.v_tot_disp>>16) & 0x7ff)+1,
 773                          info->default_par.crtc.bpp,
 774                          info->default_par.crtc.vxres*info->default_par.crtc.bpp/8
 775                         );
 776  btext_setup_display(
 777                          (((info->default_par.crtc.h_tot_disp>>16) & 0xff)+1)*8,
 778                          ((info->default_par.crtc.v_tot_disp>>16) & 0x7ff)+1,
 779                          info->default_par.crtc.bpp,
 780                          info->default_par.crtc.vxres*info->default_par.crtc.bpp/8,info->frame_buffer);
 781 #endif
 782
 783  btext_clearscreen();
 784
 785  map_boot_text();
 786
 787 #if 0
 788
 789  btext_drawstring("test framebuffer\n");
 790
 791  mdelay(10000);
 792 // test end
 793 #endif
 794
 795 #endif /* CONFIG_CONSOLE_BTEXT */
 796
 797 }
 798
 799 #if CONFIG_CONSOLE_BTEXT==1
 800
 801 static int atyfb_decode_var(const struct fb_var_screeninfo *var,
 802                             struct atyfb_par *par,
 803                             const struct fb_info_aty *info)
 804 {
 805     int err;
 806
 807     if ((err = aty_var_to_crtc(info, var, &par->crtc)) ||
 808         (err = aty_var_to_pll_ct(info, var->pixclock, par->crtc.bpp,
 809                                          &par->pll)))
 810         return err;
 811
 812 #if 0
 813     if (var->accel_flags & FB_ACCELF_TEXT)
 814         par->accel_flags = FB_ACCELF_TEXT;
 815     else
 816 #endif
 817         par->accel_flags = 0;
 818
 819 #if 0 /* fbmon is not done. uncomment for 2.5.x -brad */
 820     if (!fbmon_valid_timings(var->pixclock, htotal, vtotal, info))
 821         return -EINVAL;
 822 #endif
 823
 824     return 0;
 825 }
 826 #if PLL_CRTC_DECODE==1
 827 static int atyfb_encode_var(struct fb_var_screeninfo *var,
 828                             const struct atyfb_par *par,
 829                             const struct fb_info_aty *info)
 830 {
 831     int err;
 832
 833     memset(var, 0, sizeof(struct fb_var_screeninfo));
 834
 835     if ((err = aty_crtc_to_var(&par->crtc, var)))
 836         return err;
 837     var->pixclock = aty_pll_ct_to_var(info, &par->pll);
 838
 839     var->height = -1;
 840     var->width = -1;
 841     var->accel_flags = par->accel_flags;
 842
 843     return 0;
 844 }
 845 #endif
 846 static void aty_set_crtc(const struct fb_info_aty *info,
 847                          const struct crtc *crtc)
 848 {
 849     aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_tot_disp, info);
 850     aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid, info);
 851     aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_tot_disp, info);
 852     aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid, info);
 853     aty_st_le32(CRTC_VLINE_CRNT_VLINE, 0, info);
 854     aty_st_le32(CRTC_OFF_PITCH, crtc->off_pitch, info);
 855     aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl, info);
 856 }
 857
 858 static int aty_var_to_crtc(const struct fb_info_aty *info,
 859                            const struct fb_var_screeninfo *var,
 860                            struct crtc *crtc)
 861 {
 862     u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp;
 863     u32 left, right, upper, lower, hslen, vslen, sync, vmode;
 864     u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol;
 865     u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
 866     u32 pix_width, dp_pix_width, dp_chain_mask;
 867
 868     /* input */
 869     xres = var->xres;
 870     yres = var->yres;
 871     vxres = var->xres_virtual;
 872     vyres = var->yres_virtual;
 873     xoffset = var->xoffset;
 874     yoffset = var->yoffset;
 875     bpp = var->bits_per_pixel;
 876     left = var->left_margin;
 877     right = var->right_margin;
 878     upper = var->upper_margin;
 879     lower = var->lower_margin;
 880     hslen = var->hsync_len;
 881     vslen = var->vsync_len;
 882     sync = var->sync;
 883     vmode = var->vmode;
 884
 885     /* convert (and round up) and validate */
 886     xres = (xres+7) & ~7;
 887     xoffset = (xoffset+7) & ~7;
 888     vxres = (vxres+7) & ~7;
 889     if (vxres < xres+xoffset)
 890         vxres = xres+xoffset;
 891     h_disp = xres/8-1;
 892     if (h_disp > 0xff)
 893         FAIL("h_disp too large");
 894     h_sync_strt = h_disp+(right/8);
 895     if (h_sync_strt > 0x1ff)
 896         FAIL("h_sync_start too large");
 897     h_sync_dly = right & 7;
 898     h_sync_wid = (hslen+7)/8;
 899     if (h_sync_wid > 0x1f)
 900         FAIL("h_sync_wid too large");
 901     h_total = h_sync_strt+h_sync_wid+(h_sync_dly+left+7)/8;
 902     if (h_total > 0x1ff)
 903      FAIL("h_total too large");
 904     h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
 905
 906     if (vyres < yres+yoffset)
 907         vyres = yres+yoffset;
 908     v_disp = yres-1;
 909     if (v_disp > 0x7ff)
 910         FAIL("v_disp too large");
 911     v_sync_strt = v_disp+lower;
 912     if (v_sync_strt > 0x7ff)
 913         FAIL("v_sync_strt too large");
 914     v_sync_wid = vslen;
 915     if (v_sync_wid > 0x1f)
 916         FAIL("v_sync_wid too large");
 917     v_total = v_sync_strt+v_sync_wid+upper;
 918     if (v_total > 0x7ff)
 919         FAIL("v_total too large");
 920     v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
 921
 922     c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? CRTC_CSYNC_EN : 0;
 923
 924     if (bpp <= 8) {
 925         bpp = 8;
 926         pix_width = CRTC_PIX_WIDTH_8BPP;
 927         dp_pix_width = HOST_8BPP | SRC_8BPP | DST_8BPP | BYTE_ORDER_LSB_TO_MSB;
 928         dp_chain_mask = 0x8080;
 929     }
 930 #if SUPPORT_8_BPP_ABOVE==1
 931    else if (bpp <= 16) {
 932         bpp = 16;
 933         pix_width = CRTC_PIX_WIDTH_15BPP;
 934         dp_pix_width = HOST_15BPP | SRC_15BPP | DST_15BPP |
 935                        BYTE_ORDER_LSB_TO_MSB;
 936         dp_chain_mask = 0x4210;
 937     } else if (bpp <= 24 && M64_HAS(INTEGRATED)) {
 938         bpp = 24;
 939         pix_width = CRTC_PIX_WIDTH_24BPP;
 940         dp_pix_width = HOST_8BPP | SRC_8BPP | DST_8BPP | BYTE_ORDER_LSB_TO_MSB;
 941         dp_chain_mask = 0x8080;
 942     } else if (bpp <= 32) {
 943         bpp = 32;
 944         pix_width = CRTC_PIX_WIDTH_32BPP;
 945         dp_pix_width = HOST_32BPP | SRC_32BPP | DST_32BPP |
 946                        BYTE_ORDER_LSB_TO_MSB;
 947         dp_chain_mask = 0x8080;
 948     }
 949 #endif
 950 else
 951         FAIL("invalid bpp");
 952
 953     if (vxres*vyres*bpp/8 > info->total_vram)
 954         FAIL("not enough video RAM");
 955   if ((vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
 956         FAIL("invalid vmode");
 957
 958     /* output */
 959     crtc->vxres = vxres;
 960     crtc->vyres = vyres;
 961     crtc->xoffset = xoffset;
 962     crtc->yoffset = yoffset;
 963     crtc->bpp = bpp;
 964     crtc->h_tot_disp = h_total | (h_disp<<16);
 965     crtc->h_sync_strt_wid = (h_sync_strt & 0xff) | (h_sync_dly<<8) |
 966                             ((h_sync_strt & 0x100)<<4) | (h_sync_wid<<16) |
 967                             (h_sync_pol<<21);
 968     crtc->v_tot_disp = v_total | (v_disp<<16);
 969     crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid<<16) | (v_sync_pol<<21);
 970     crtc->off_pitch = ((yoffset*vxres+xoffset)*bpp/64) | (vxres<<19);
 971     crtc->gen_cntl = pix_width | c_sync | CRTC_EXT_DISP_EN | CRTC_ENABLE;
 972     if (M64_HAS(MAGIC_FIFO)) {
 973         /* Not VTB/GTB */
 974         /* FIXME: magic FIFO values */
 975         crtc->gen_cntl |= aty_ld_le32(CRTC_GEN_CNTL, info) & 0x000e0000;
 976     }
 977     crtc->dp_pix_width = dp_pix_width;
 978     crtc->dp_chain_mask = dp_chain_mask;
 979
 980     return 0;
 981 }
 982 #if PLL_CRTC_DECODE==1
 983 static int aty_crtc_to_var(const struct crtc *crtc,
 984                            struct fb_var_screeninfo *var)
 985 {
 986     u32 xres, yres, bpp, left, right, upper, lower, hslen, vslen, sync;
 987     u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol;
 988     u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
 989     u32 pix_width;
 990
 991     /* input */
 992     h_total = crtc->h_tot_disp & 0x1ff;
 993     h_disp = (crtc->h_tot_disp>>16) & 0xff;
 994     h_sync_strt = (crtc->h_sync_strt_wid & 0xff) |
 995                   ((crtc->h_sync_strt_wid>>4) & 0x100);
 996     h_sync_dly = (crtc->h_sync_strt_wid>>8) & 0x7;
 997     h_sync_wid = (crtc->h_sync_strt_wid>>16) & 0x1f;
 998     h_sync_pol = (crtc->h_sync_strt_wid>>21) & 0x1;
 999     v_total = crtc->v_tot_disp & 0x7ff;
1000     v_disp = (crtc->v_tot_disp>>16) & 0x7ff;
1001     v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1002     v_sync_wid = (crtc->v_sync_strt_wid>>16) & 0x1f;
1003     v_sync_pol = (crtc->v_sync_strt_wid>>21) & 0x1;
1004     c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1005     pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1006
1007     /* convert */
1008     xres = (h_disp+1)*8;
1009     yres = v_disp+1;
1010     left = (h_total-h_sync_strt-h_sync_wid)*8-h_sync_dly;
1011     right = (h_sync_strt-h_disp)*8+h_sync_dly;
1012     hslen = h_sync_wid*8;
1013     upper = v_total-v_sync_strt-v_sync_wid;
1014     lower = v_sync_strt-v_disp;
1015     vslen = v_sync_wid;
1016     sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1017            (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1018            (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1019
1020     switch (pix_width) {
1021 #if 0
1022         case CRTC_PIX_WIDTH_4BPP:
1023             bpp = 4;
1024             var->red.offset = 0;
1025             var->red.length = 8;
1026             var->green.offset = 0;
1027             var->green.length = 8;
1028             var->blue.offset = 0;
1029             var->blue.length = 8;
1030             var->transp.offset = 0;
1031             var->transp.length = 0;
1032             break;
1033 #endif
1034         case CRTC_PIX_WIDTH_8BPP:
1035             bpp = 8;
1036             var->red.offset = 0;
1037             var->red.length = 8;
1038             var->green.offset = 0;
1039             var->green.length = 8;
1040             var->blue.offset = 0;
1041             var->blue.length = 8;
1042             var->transp.offset = 0;
1043             var->transp.length = 0;
1044             break;
1045 #if SUPPORT_8_BPP_ABOVE==1
1046         case CRTC_PIX_WIDTH_15BPP:      /* RGB 555 */
1047             bpp = 16;
1048             var->red.offset = 10;
1049             var->red.length = 5;
1050             var->green.offset = 5;
1051             var->green.length = 5;
1052             var->blue.offset = 0;
1053             var->blue.length = 5;
1054             var->transp.offset = 0;
1055             var->transp.length = 0;
1056             break;
1057         case CRTC_PIX_WIDTH_16BPP:      /* RGB 565 */
1058             bpp = 16;
1059             var->red.offset = 11;
1060             var->red.length = 5;
1061             var->green.offset = 5;
1062             var->green.length = 6;
1063             var->blue.offset = 0;
1064             var->blue.length = 5;
1065             var->transp.offset = 0;
1066             var->transp.length = 0;
1067             break;
1068         case CRTC_PIX_WIDTH_24BPP:      /* RGB 888 */
1069             bpp = 24;
1070             var->red.offset = 16;
1071             var->red.length = 8;
1072             var->green.offset = 8;
1073             var->green.length = 8;
1074             var->blue.offset = 0;
1075             var->blue.length = 8;
1076            var->transp.offset = 0;
1077             var->transp.length = 0;
1078             break;
1079         case CRTC_PIX_WIDTH_32BPP:      /* ARGB 8888 */
1080             bpp = 32;
1081             var->red.offset = 16;
1082             var->red.length = 8;
1083             var->green.offset = 8;
1084             var->green.length = 8;
1085             var->blue.offset = 0;
1086             var->blue.length = 8;
1087             var->transp.offset = 24;
1088             var->transp.length = 8;
1089             break;
1090 #endif
1091         default:
1092             FAIL("Invalid pixel width");
1093     }
1094
1095     /* output */
1096     var->xres = xres;
1097     var->yres = yres;
1098     var->xres_virtual = crtc->vxres;
1099     var->yres_virtual = crtc->vyres;
1100     var->bits_per_pixel = bpp;
1101     var->xoffset = crtc->xoffset;
1102     var->yoffset = crtc->yoffset;
1103     var->left_margin = left;
1104     var->right_margin = right;
1105     var->upper_margin = upper;
1106     var->lower_margin = lower;
1107     var->hsync_len = hslen;
1108     var->vsync_len = vslen;
1109     var->sync = sync;
1110     var->vmode = FB_VMODE_NONINTERLACED;
1111
1112     return 0;
1113 }
1114 #endif
1115
1116 #if 0
1117 static int encode_fix(struct fb_fix_screeninfo *fix,
1118                       const struct atyfb_par *par,
1119                       const struct fb_info_aty *info)
1120 {
1121     memset(fix, 0, sizeof(struct fb_fix_screeninfo));
1122
1123    // strcpy(fix->id, atyfb_name);
1124          memcpy(fix->id, "atyfb", 5);
1125     fix->smem_start = info->frame_buffer;
1126     fix->smem_len = (u32)info->total_vram;
1127
1128     /*
1129      *  Reg Block 0 (CT-compatible block) is at ati_regbase_phys
1130      *  Reg Block 1 (multimedia extensions) is at ati_regbase_phys-0x400
1131      */
1132     if (M64_HAS(GX)) {
1133         fix->mmio_start = info->ati_regbase;
1134         fix->mmio_len = 0x400;
1135         fix->accel = FB_ACCEL_ATI_MACH64GX;
1136     } else if (M64_HAS(CT)) {
1137         fix->mmio_start = info->ati_regbase;
1138         fix->mmio_len = 0x400;
1139         fix->accel = FB_ACCEL_ATI_MACH64CT;
1140     } else if (M64_HAS(VT)) {
1141         fix->mmio_start = info->ati_regbase-0x400;
1142         fix->mmio_len = 0x800;
1143         fix->accel = FB_ACCEL_ATI_MACH64VT;
1144     } else /* if (M64_HAS(GT)) */ {
1145         fix->mmio_start = info->ati_regbase-0x400;
1146         fix->mmio_len = 0x800;
1147         fix->accel = FB_ACCEL_ATI_MACH64GT;
1148     }
1149     fix->type = FB_TYPE_PACKED_PIXELS;
1150     fix->type_aux = 0;
1151     fix->line_length = par->crtc.vxres*par->crtc.bpp/8;
1152     fix->visual = par->crtc.bpp <= 8 ? FB_VISUAL_PSEUDOCOLOR
1153                                      : FB_VISUAL_DIRECTCOLOR;
1154     fix->ywrapstep = 0;
1155     fix->xpanstep = 8;
1156     fix->ypanstep = 1;
1157
1158     return 0;
1159 }
1160 #endif
1161    /*
1162      *  Set the User Defined Part of the Display
1163      */
1164 #if PLL_CRTC_DECODE==1
1165 static int atyfb_set_var(struct fb_var_screeninfo *var, int con,
1166                          struct fb_info *fb)
1167 {
1168     struct fb_info_aty *info = (struct fb_info_aty *)fb;
1169     struct atyfb_par par;
1170 #if 0
1171     struct display *display;
1172     int oldxres, oldyres, oldvxres, oldvyres, oldbpp, oldaccel, accel;
1173 #endif
1174     int err;
1175     int activate = var->activate;
1176
1177 #if 0
1178     if (con >= 0)
1179         display = &fb_display[con];
1180     else
1181 #endif
1182 #if 0
1183         display = fb->disp;     /* used during initialization */
1184 #endif
1185
1186     if ((err = atyfb_decode_var(var, &par, info)))
1187         return err;
1188
1189     atyfb_encode_var(var, &par, (struct fb_info_aty *)info);
1190
1191 #if 0
1192     printk(BIOS_INFO, "atyfb_set_var: activate=%d\n", activate & FB_ACTIVATE_MASK);
1193 #endif
1194
1195     if ((activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) {
1196 #if 0
1197         oldxres = display->var.xres;
1198         oldyres = display->var.yres;
1199         oldvxres = display->var.xres_virtual;
1200         oldvyres = display->var.yres_virtual;
1201         oldbpp = display->var.bits_per_pixel;
1202         oldaccel = display->var.accel_flags;
1203         display->var = *var;
1204         accel = var->accel_flags & FB_ACCELF_TEXT;
1205         if (oldxres != var->xres || oldyres != var->yres ||
1206             oldvxres != var->xres_virtual || oldvyres != var->yres_virtual ||
1207             oldbpp != var->bits_per_pixel || oldaccel != var->accel_flags) {
1208             struct fb_fix_screeninfo fix;
1209
1210             encode_fix(&fix, &par, info);
1211             display->screen_base = (char *)info->frame_buffer;
1212             display->visual = fix.visual;
1213             display->type = fix.type;
1214             display->type_aux = fix.type_aux;
1215             display->ypanstep = fix.ypanstep;
1216             display->ywrapstep = fix.ywrapstep;
1217             display->line_length = fix.line_length;
1218             display->can_soft_blank = 1;
1219             display->inverse = 0;
1220 #if 0
1221            if (accel)
1222                 display->scrollmode = (info->bus_type == PCI) ? SCROLL_YNOMOVE : 0;
1223             else
1224 #endif
1225                 display->scrollmode = SCROLL_YREDRAW;
1226 #if 0
1227             if (info->fb_info.changevar)
1228                 (*info->fb_info.changevar)(con);
1229 #endif
1230         }
1231 #endif
1232 //        if (!info->fb_info.display_fg ||
1233 //            info->fb_info.display_fg->vc_num == con) {
1234             atyfb_set_par(&par, info);
1235 #if 0
1236             atyfb_set_dispsw(display, info, par.crtc.bpp, accel);
1237 #endif
1238 //        }
1239 #if 0
1240         if (oldbpp != var->bits_per_pixel) {
1241             if ((err = fb_alloc_cmap(&display->cmap, 0, 0)))
1242                 return err;
1243 #endif
1244             do_install_cmap(con, info);
1245 #if 0
1246         }
1247 #endif
1248     }
1249
1250     return 0;
1251 }
1252
1253 #endif
1254 /* ------------------------------------------------------------------------- */
1255
1256 static void atyfb_set_par(const struct atyfb_par *par,
1257                           struct fb_info_aty *info)
1258 {
1259     u32 i;
1260     int accelmode;
1261     u8 tmp;
1262
1263     accelmode = par->accel_flags;  /* hack */
1264
1265 #if PLL_CRTC_DECODE==1
1266     info->current_par = *par;
1267 #endif
1268
1269     if (info->blitter_may_be_busy)
1270         wait_for_idle(info);
1271     tmp = aty_ld_8(CRTC_GEN_CNTL + 3, info);
1272     aty_set_crtc(info, &par->crtc);
1273     aty_st_8(CLOCK_CNTL + info->clk_wr_offset, 0, info);
1274                                         /* better call aty_StrobeClock ?? */
1275     aty_st_8(CLOCK_CNTL + info->clk_wr_offset, CLOCK_STROBE, info);
1276
1277     //info->dac_ops->set_dac(info, &par->pll, par->crtc.bpp, accelmode);
1278     //info->pll_ops->set_pll(info, &par->pll);
1279    aty_set_pll_ct(info, &par->pll);
1280
1281
1282     if (!M64_HAS(INTEGRATED)) {
1283         /* Don't forget MEM_CNTL */
1284         i = aty_ld_le32(MEM_CNTL, info) & 0xf0ffffff;
1285         switch (par->crtc.bpp) {
1286             case 8:
1287                 i |= 0x02000000;
1288                 break;
1289 #if SUPPORT_8_BPP_ABOVE==1
1290             case 16:
1291                 i |= 0x03000000;
1292                 break;
1293             case 32:
1294                 i |= 0x06000000;
1295                 break;
1296 #endif
1297         }
1298         aty_st_le32(MEM_CNTL, i, info);
1299     } else {
1300         i = aty_ld_le32(MEM_CNTL, info) & 0xf00fffff;
1301         if (!M64_HAS(MAGIC_POSTDIV))
1302                 i |= info->mem_refresh_rate << 20;
1303         switch (par->crtc.bpp) {
1304             case 8:
1305 #if SUPPORT_8_BPP_ABOVE==1
1306             case 24:
1307 #endif
1308                 i |= 0x00000000;
1309                break;
1310 #if SUPPORT_8_BPP_ABOVE==1
1311             case 16:
1312                 i |= 0x04000000;
1313                 break;
1314             case 32:
1315                 i |= 0x08000000;
1316                 break;
1317 #endif
1318         }
1319         if (M64_HAS(CT_BUS)) {
1320             aty_st_le32(DAC_CNTL, 0x87010184, info);
1321             aty_st_le32(BUS_CNTL, 0x680000f9, info);
1322         } else if (M64_HAS(VT_BUS)) {
1323             aty_st_le32(DAC_CNTL, 0x87010184, info);
1324             aty_st_le32(BUS_CNTL, 0x680000f9, info);
1325         }  else if (M64_HAS(MOBIL_BUS)) {
1326             aty_st_le32(DAC_CNTL, 0x80010102, info);
1327             aty_st_le32(BUS_CNTL, 0x7b33a040, info);
1328         }  else {
1329             /* GT */
1330             aty_st_le32(DAC_CNTL, 0x86010102, info);
1331             aty_st_le32(BUS_CNTL, 0x7b23a040, info);
1332             aty_st_le32(EXT_MEM_CNTL,
1333                         aty_ld_le32(EXT_MEM_CNTL, info) | 0x5000001, info);
1334         }
1335
1336         aty_st_le32(MEM_CNTL, i, info);
1337     }
1338     aty_st_8(DAC_MASK, 0xff, info);
1339
1340     /* Initialize the graphics engine */
1341 #if 0
1342     if (par->accel_flags & FB_ACCELF_TEXT)
1343         aty_init_engine(par, info);
1344 #endif
1345
1346
1347 }
1348 #if 0
1349 static u16 red2[] = {
1350     0x0000, 0xaaaa
1351 };
1352 static u16 green2[] = {
1353     0x0000, 0xaaaa
1354 };
1355 static u16 blue2[] = {
1356     0x0000, 0xaaaa
1357 };
1358
1359 static u16 red4[] = {
1360     0x0000, 0xaaaa, 0x5555, 0xffff
1361 };
1362 static u16 green4[] = {
1363     0x0000, 0xaaaa, 0x5555, 0xffff
1364 };
1365 static u16 blue4[] = {
1366     0x0000, 0xaaaa, 0x5555, 0xffff
1367 };
1368
1369 static u16 red8[] = {
1370     0x0000, 0x0000, 0x0000, 0x0000, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa
1371 };
1372 static u16 green8[] = {
1373     0x0000, 0x0000, 0xaaaa, 0xaaaa, 0x0000, 0x0000, 0x5555, 0xaaaa
1374 };
1375 static u16 blue8[] = {
1376     0x0000, 0xaaaa, 0x0000, 0xaaaa, 0x0000, 0xaaaa, 0x0000, 0xaaaa
1377 };
1378 #endif
1379 static u16 red16[] = {
1380     0x0000, 0x0000, 0x0000, 0x0000, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa,
1381     0x5555, 0x5555, 0x5555, 0x5555, 0xffff, 0xffff, 0xffff, 0xffff
1382 };
1383 static u16 green16[] = {
1384     0x0000, 0x0000, 0xaaaa, 0xaaaa, 0x0000, 0x0000, 0x5555, 0xaaaa,
1385     0x5555, 0x5555, 0xffff, 0xffff, 0x5555, 0x5555, 0xffff, 0xffff
1386 };
1387 static u16 blue16[] = {
1388     0x0000, 0xaaaa, 0x0000, 0xaaaa, 0x0000, 0xaaaa, 0x0000, 0xaaaa,
1389     0x5555, 0xffff, 0x5555, 0xffff, 0x5555, 0xffff, 0x5555, 0xffff
1390 };
1391 #if 0
1392 static struct fb_cmap default_2_colors = {
1393     0, 2, red2, green2, blue2, NULL
1394 };
1395 static struct fb_cmap default_8_colors = {
1396     0, 8, red8, green8, blue8, NULL
1397 };
1398 static struct fb_cmap default_4_colors = {
1399     0, 4, red4, green4, blue4, NULL
1400 };
1401 #endif
1402 static struct fb_cmap default_16_colors = {
1403     0, 16, red16, green16, blue16, NULL
1404 };
1405
1406
1407
1408 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
1409                            u_int transp, struct fb_info_aty *info)
1410 {
1411     int i, scale;
1412
1413     if (regno > 255)
1414         return 1;
1415     red >>= 8;
1416     green >>= 8;
1417     blue >>= 8;
1418 #if 0
1419 //We don't need to store it
1420     info->palette[regno].red = red;
1421     info->palette[regno].green = green;
1422     info->palette[regno].blue = blue;
1423 #endif
1424     i = aty_ld_8(DAC_CNTL, info) & 0xfc;
1425     if (M64_HAS(EXTRA_BRIGHT))
1426         i |= 0x2;       /*DAC_CNTL|0x2 turns off the extra brightness for gt*/
1427     aty_st_8(DAC_CNTL, i, info);
1428     aty_st_8(DAC_MASK, 0xff, info);
1429 #if PLL_CRTC_DECODE==1
1430     scale = (M64_HAS(INTEGRATED) && info->current_par.crtc.bpp == 16) ? 3 : 0;
1431 #else
1432     scale = (M64_HAS(INTEGRATED) && info->default_par.crtc.bpp == 16) ? 3 : 0;
1433 #endif
1434     write8(&info->aty_cmap_regs->windex, regno << scale)
1435     write8(&info->aty_cmap_regs->lut, red);
1436     write8(&info->aty_cmap_regs->lut, green);
1437     write8(&info->aty_cmap_regs->lut, blue);
1438     return 0;
1439 }
1440
1441 int fb_set_cmap(struct fb_cmap *cmap, int kspc,
1442                 int (*setcolreg)(u_int, u_int, u_int, u_int, u_int,
1443                                  struct fb_info_aty *),
1444                 struct fb_info_aty *info)
1445 {
1446     int i, start;
1447     u16 *red, *green, *blue, *transp;
1448     u_int hred, hgreen, hblue, htransp;
1449
1450     red = cmap->red;
1451     green = cmap->green;
1452     blue = cmap->blue;
1453     transp = cmap->transp;
1454     start = cmap->start;
1455
1456     if (start < 0)
1457         return -EINVAL;
1458     for (i = 0; i < cmap->len; i++) {
1459             hred = *red;
1460             hgreen = *green;
1461             hblue = *blue;
1462             htransp = transp ? *transp : 0;
1463         red++;
1464         green++;
1465         blue++;
1466         if (transp)
1467             transp++;
1468         if (setcolreg(start++, hred, hgreen, hblue, htransp, info))
1469             return 0;
1470     }
1471     return 0;
1472 }
1473
1474 struct fb_cmap *fb_default_cmap(int len)
1475 {
1476 #if 0
1477     if (len <= 2)
1478         return &default_2_colors;
1479     if (len <= 4)
1480         return &default_4_colors;
1481     if (len <= 8)
1482         return &default_8_colors;
1483 #endif
1484     return &default_16_colors;
1485 }
1486
1487 static void do_install_cmap(int con, struct fb_info_aty *info)
1488 {
1489 #if PLL_CRTC_DECODE==1
1490         int size = info->current_par.crtc.bpp == 16 ? 32 : 256;
1491 #else
1492         int size = 256;
1493 #endif
1494         fb_set_cmap(fb_default_cmap(size), 1, atyfb_setcolreg, info);
1495 }
1496
1497 #endif /*CONFIG_CONSOLE_BTEXT */
1498
1499 static struct device_operations ati_ragexl_graph_ops  = {
1500         .read_resources   = pci_dev_read_resources,
1501         .set_resources    = pci_dev_set_resources,
1502         .enable_resources = pci_dev_enable_resources,
1503         .init             = ati_ragexl_init,
1504         .scan_bus         = 0,
1505 };
1506
1507 static const struct pci_driver ati_ragexl_graph_driver __pci_driver = {
1508         .ops    = &ati_ragexl_graph_ops,
1509         .vendor = PCI_VENDOR_ID_ATI,
1510         .device = PCI_DEVICE_ID_ATI_215XL,
1511 };
1512
1513