src/drivers/ati/ragexl/xlinit.c

   1 /*
   2  *  ATI Rage XL Initialization. Support for Xpert98 and Victoria
   3  *  PCI cards.
   4  *
   5  *  Copyright (C) 2002 MontaVista Software Inc.
   6  *  Author: MontaVista Software, Inc.
   7  *              stevel@mvista.com or source@mvista.com
   8  *  Copyright (C) 2004 Tyan Computer.
   9  *  Auther: Yinghai Lu   yhlu@tyan.com
  10  *         move to LinuxBIOS
  11  * This code is distributed without warranty under the GPL v2 (see COPYING) *
  12  */
  13 #include <delay.h>
  14 #include <stdlib.h>
  15 #include <string.h>
  16 #include <arch/io.h>
  17
  18 #include <console/console.h>
  19 #include <device/device.h>
  20 #include <device/pci.h>
  21 #include <device/pci_ids.h>
  22 #include <device/pci_ops.h>
  23
  24 #include "mach64.h"
  25 #include "atyfb.h"
  26
  27 #include "mach64_ct.c"
  28
  29 #define MPLL_GAIN       0xad
  30 #define VPLL_GAIN       0xd5
  31
  32 enum {
  33         VICTORIA = 0,
  34         XPERT98,
  35         NUM_XL_CARDS
  36 };
  37
  38 //static struct aty_pll_ops aty_pll_ct;
  39
  40 #define DEFAULT_CARD XPERT98
  41 static int xl_card = DEFAULT_CARD;
  42
  43 static const struct xl_card_cfg_t {
  44         int ref_crystal; // 10^4 Hz
  45         int mem_type;
  46         int mem_size;
  47         u32 mem_cntl;
  48         u32 ext_mem_cntl;
  49         u32 mem_addr_config;
  50         u32 bus_cntl;
  51         u32 dac_cntl;
  52         u32 hw_debug;
  53         u32 custom_macro_cntl;
  54         u8  dll2_cntl;
  55         u8  pll_yclk_cntl;
  56 } card_cfg[NUM_XL_CARDS] = {
  57         // VICTORIA
  58         {       2700, SDRAM, 0x800000,
  59                 0x10757A3B, 0x64000C81, 0x00110202, 0x7b33A040,
  60                 0x82010102, 0x48803800, 0x005E0179,
  61                 0x50, 0x25
  62         },
  63         // XPERT98
  64         {       1432,  WRAM, 0x800000,
  65                 0x00165A2B, 0xE0000CF1, 0x00200213, 0x7333A001,
  66                 0x8000000A, 0x48833800, 0x007F0779,
  67                 0x10, 0x19
  68         }
  69 };
  70
  71 typedef struct {
  72         u8 lcd_reg;
  73         u32 val;
  74 } lcd_tbl_t;
  75
  76 static const lcd_tbl_t lcd_tbl[] = {
  77         { 0x01, 0x000520C0 },
  78         { 0x08, 0x02000408 },
  79         { 0x03, 0x00000F00 },
  80         { 0x00, 0x00000000 },
  81         { 0x02, 0x00000000 },
  82         { 0x04, 0x00000000 },
  83         { 0x05, 0x00000000 },
  84         { 0x06, 0x00000000 },
  85         { 0x33, 0x00000000 },
  86         { 0x34, 0x00000000 },
  87         { 0x35, 0x00000000 },
  88         { 0x36, 0x00000000 },
  89         { 0x37, 0x00000000 }
  90 };
  91
  92 static inline u32 aty_ld_lcd(u8 lcd_reg, struct fb_info_aty *info)
  93 {
  94         aty_st_8(LCD_INDEX, lcd_reg, info);
  95         return aty_ld_le32(LCD_DATA, info);
  96 }
  97
  98 static inline void aty_st_lcd(u8 lcd_reg, u32 val,
  99                               struct fb_info_aty *info)
 100 {
 101         aty_st_8(LCD_INDEX, lcd_reg, info);
 102         aty_st_le32(LCD_DATA, val, info);
 103 }
 104
 105 static void reset_gui(struct fb_info_aty *info)
 106 {
 107         aty_st_8(GEN_TEST_CNTL+1, 0x01, info);
 108         aty_st_8(GEN_TEST_CNTL+1, 0x00, info);
 109         aty_st_8(GEN_TEST_CNTL+1, 0x02, info);
 110         mdelay(5);
 111 }
 112
 113
 114 static void reset_sdram(struct fb_info_aty *info)
 115 {
 116         u8 temp;
 117
 118         temp = aty_ld_8(EXT_MEM_CNTL, info);
 119         temp |= 0x02;
 120         aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_SDRAM_RESET = 1b
 121         temp |= 0x08;
 122         aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_CYC_TEST    = 10b
 123         temp |= 0x0c;
 124         aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_CYC_TEST    = 11b
 125         mdelay(5);
 126         temp &= 0xf3;
 127         aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_CYC_TEST    = 00b
 128         temp &= 0xfd;
 129         aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_SDRAM_REST  = 0b
 130         mdelay(5);
 131 }
 132
 133 static void init_dll(struct fb_info_aty *info)
 134 {
 135         // enable DLL
 136         aty_st_pll(PLL_GEN_CNTL,
 137                    aty_ld_pll(PLL_GEN_CNTL, info) & 0x7f,
 138                    info);
 139
 140         // reset DLL
 141         aty_st_pll(DLL_CNTL, 0x82, info);
 142         aty_st_pll(DLL_CNTL, 0xE2, info);
 143         mdelay(5);
 144         aty_st_pll(DLL_CNTL, 0x82, info);
 145         mdelay(6);
 146 }
 147
 148 static void reset_clocks(struct fb_info_aty *info, struct pll_ct *pll,
 149                          int hsync_enb)
 150 {
 151         reset_gui(info);
 152         aty_st_pll(MCLK_FB_DIV, pll->mclk_fb_div, info);
 153         aty_st_pll(SCLK_FB_DIV, pll->sclk_fb_div, info);
 154
 155         mdelay(15);
 156         init_dll(info);
 157         aty_st_8(GEN_TEST_CNTL+1, 0x00, info);
 158         mdelay(5);
 159         aty_st_8(CRTC_GEN_CNTL+3, 0x04, info);
 160         mdelay(6);
 161         reset_sdram(info);
 162         aty_st_8(CRTC_GEN_CNTL+3,
 163                  hsync_enb ? 0x00 : 0x04, info);
 164
 165         aty_st_pll(SPLL_CNTL2, pll->spll_cntl2, info);
 166         aty_st_pll(PLL_GEN_CNTL, pll->pll_gen_cntl, info);
 167         aty_st_pll(PLL_VCLK_CNTL, pll->pll_vclk_cntl, info);
 168 }
 169
 170 static int atyfb_xl_init(struct fb_info_aty *info)
 171 {
 172         int i, err;
 173         u32 temp;
 174         union aty_pll pll;
 175         const struct xl_card_cfg_t * card = &card_cfg[xl_card];
 176
 177         aty_st_8(CONFIG_STAT0, 0x85, info);
 178         mdelay(10);
 179
 180         /*
 181          * The following needs to be set before the call
 182          * to var_to_pll() below. They'll be re-set again
 183          * to the same values in aty_init().
 184          */
 185         info->ref_clk_per = 100000000UL/card->ref_crystal;
 186         info->ram_type = card->mem_type;
 187         info->total_vram = card->mem_size;
 188         if (xl_card == VICTORIA) {
 189                 // the MCLK, XCLK are 120MHz on victoria card
 190                 info->mclk_per = 1000000/120;
 191                 info->xclk_per = 1000000/120;
 192                 info->features &= ~M64F_MFB_TIMES_4;
 193         }
 194
 195         /*
 196          * Calculate mclk and xclk dividers, etc. The passed
 197          * pixclock and bpp values don't matter yet, the vclk
 198          * isn't programmed until later.
 199          */
 200
 201         if ((err = aty_var_to_pll_ct(info, 39726, 8, &pll))) return err;
 202 //        if ((err = aty_pll_ct.var_to_pll(info, 39726, 8, &pll))) return err;
 203
 204
 205         aty_st_pll(LVDS_CNTL0, 0x00, info);
 206         aty_st_pll(DLL2_CNTL, card->dll2_cntl, info);
 207         aty_st_pll(V2PLL_CNTL, 0x10, info);
 208         aty_st_pll(MPLL_CNTL, MPLL_GAIN, info);
 209         aty_st_pll(VPLL_CNTL, VPLL_GAIN, info);
 210         aty_st_pll(PLL_VCLK_CNTL, 0x00, info);
 211         aty_st_pll(VFC_CNTL, 0x1B, info);
 212         aty_st_pll(PLL_REF_DIV, pll.ct.pll_ref_div, info);
 213         aty_st_pll(PLL_EXT_CNTL, pll.ct.pll_ext_cntl, info);
 214         aty_st_pll(SPLL_CNTL2, 0x03, info);
 215         aty_st_pll(PLL_GEN_CNTL, 0x44, info);
 216
 217         reset_clocks(info, &pll.ct, 0);
 218         mdelay(10);
 219
 220         aty_st_pll(VCLK_POST_DIV, 0x03, info);
 221         aty_st_pll(VCLK0_FB_DIV, 0xDA, info);
 222         aty_st_pll(VCLK_POST_DIV, 0x0F, info);
 223         aty_st_pll(VCLK1_FB_DIV, 0xF5, info);
 224         aty_st_pll(VCLK_POST_DIV, 0x3F, info);
 225         aty_st_pll(PLL_EXT_CNTL, 0x40 | pll.ct.pll_ext_cntl, info);
 226         aty_st_pll(VCLK2_FB_DIV, 0x00, info);
 227         aty_st_pll(VCLK_POST_DIV, 0xFF, info);
 228         aty_st_pll(PLL_EXT_CNTL, 0xC0 | pll.ct.pll_ext_cntl, info);
 229         aty_st_pll(VCLK3_FB_DIV, 0x00, info);
 230
 231         aty_st_8(BUS_CNTL, 0x01, info);
 232         aty_st_le32(BUS_CNTL, card->bus_cntl | 0x08000000, info);
 233
 234         aty_st_le32(CRTC_GEN_CNTL, 0x04000200, info);
 235         aty_st_le16(CONFIG_STAT0, 0x0020, info);
 236         aty_st_le32(MEM_CNTL, 0x10151A33, info);
 237         aty_st_le32(EXT_MEM_CNTL, 0xE0000C01, info);
 238         aty_st_le16(CRTC_GEN_CNTL+2, 0x0000, info);
 239         aty_st_le32(DAC_CNTL, card->dac_cntl, info);
 240         aty_st_le16(GEN_TEST_CNTL, 0x0100, info);
 241         aty_st_le32(CUSTOM_MACRO_CNTL, 0x003C0171, info);
 242         aty_st_le32(MEM_BUF_CNTL, 0x00382848, info);
 243
 244         aty_st_le32(HW_DEBUG, card->hw_debug, info);
 245         aty_st_le16(MEM_ADDR_CONFIG, 0x0000, info);
 246         aty_st_le16(GP_IO+2, 0x0000, info);
 247         aty_st_le16(GEN_TEST_CNTL, 0x0000, info);
 248         aty_st_le16(EXT_DAC_REGS+2, 0x0000, info);
 249         aty_st_le32(CRTC_INT_CNTL, 0x00000000, info);
 250         aty_st_le32(TIMER_CONFIG, 0x00000000, info);
 251         aty_st_le32(0xEC, 0x00000000, info);
 252         aty_st_le32(0xFC, 0x00000000, info);
 253
 254         for (i=0; i<sizeof(lcd_tbl)/sizeof(lcd_tbl_t); i++) {
 255                 aty_st_lcd(lcd_tbl[i].lcd_reg, lcd_tbl[i].val, info);
 256         }
 257
 258         aty_st_le16(CONFIG_STAT0, 0x00A4, info);
 259         mdelay(10);
 260
 261         aty_st_8(BUS_CNTL+1, 0xA0, info);
 262         mdelay(10);
 263
 264         reset_clocks(info, &pll.ct, 1);
 265         mdelay(10);
 266
 267         // something about power management
 268         aty_st_8(LCD_INDEX, 0x08, info);
 269         aty_st_8(LCD_DATA, 0x0A, info);
 270         aty_st_8(LCD_INDEX, 0x08, info);
 271         aty_st_8(LCD_DATA+3, 0x02, info);
 272         aty_st_8(LCD_INDEX, 0x08, info);
 273         aty_st_8(LCD_DATA, 0x0B, info);
 274         mdelay(2);
 275
 276         // enable display requests, enable CRTC
 277         aty_st_8(CRTC_GEN_CNTL+3, 0x02, info);
 278         // disable display
 279         aty_st_8(CRTC_GEN_CNTL, 0x40, info);
 280         // disable display requests, disable CRTC
 281         aty_st_8(CRTC_GEN_CNTL+3, 0x04, info);
 282         mdelay(10);
 283
 284         aty_st_pll(PLL_YCLK_CNTL, 0x25, info);
 285
 286         aty_st_le16(CUSTOM_MACRO_CNTL, 0x0179, info);
 287         aty_st_le16(CUSTOM_MACRO_CNTL+2, 0x005E, info);
 288         aty_st_le16(CUSTOM_MACRO_CNTL+2, card->custom_macro_cntl>>16, info);
 289         aty_st_8(CUSTOM_MACRO_CNTL+1,
 290                  (card->custom_macro_cntl>>8) & 0xff, info);
 291
 292         aty_st_le32(MEM_ADDR_CONFIG, card->mem_addr_config, info);
 293         aty_st_le32(MEM_CNTL, card->mem_cntl, info);
 294         aty_st_le32(EXT_MEM_CNTL, card->ext_mem_cntl, info);
 295
 296         aty_st_8(CONFIG_STAT0, 0xA0 | card->mem_type, info);
 297
 298         aty_st_pll(PLL_YCLK_CNTL, 0x01, info);
 299         mdelay(15);
 300         aty_st_pll(PLL_YCLK_CNTL, card->pll_yclk_cntl, info);
 301         mdelay(1);
 302
 303         reset_clocks(info, &pll.ct, 0);
 304         mdelay(50);
 305         reset_clocks(info, &pll.ct, 0);
 306         mdelay(50);
 307
 308         // enable extended register block
 309         aty_st_8(BUS_CNTL+3, 0x7B, info);
 310         mdelay(1);
 311         // disable extended register block
 312         aty_st_8(BUS_CNTL+3, 0x73, info);
 313
 314         aty_st_8(CONFIG_STAT0, 0x80 | card->mem_type, info);
 315
 316         // disable display requests, disable CRTC
 317         aty_st_8(CRTC_GEN_CNTL+3, 0x04, info);
 318         // disable mapping registers in VGA aperture
 319         aty_st_8(CONFIG_CNTL, aty_ld_8(CONFIG_CNTL, info) & ~0x04, info);
 320         mdelay(50);
 321         // enable display requests, enable CRTC
 322         aty_st_8(CRTC_GEN_CNTL+3, 0x02, info);
 323
 324         // make GPIO's 14,15,16 all inputs
 325         aty_st_8(LCD_INDEX, 0x07, info);
 326         aty_st_8(LCD_DATA+3, 0x00, info);
 327
 328         // enable the display
 329         aty_st_8(CRTC_GEN_CNTL, 0x00, info);
 330         mdelay(17);
 331         // reset the memory controller
 332         aty_st_8(GEN_TEST_CNTL+1, 0x02, info);
 333         mdelay(15);
 334         aty_st_8(GEN_TEST_CNTL+1, 0x00, info);
 335         mdelay(30);
 336
 337         // enable extended register block
 338         aty_st_8(BUS_CNTL+3,
 339                  (u8)(aty_ld_8(BUS_CNTL+3, info) | 0x08),
 340                  info);
 341         // set FIFO size to 512 (PIO)
 342         aty_st_le32(GUI_CNTL,
 343                     aty_ld_le32(GUI_CNTL, info) & ~0x3,
 344                     info);
 345
 346         // enable CRT and disable lcd
 347         aty_st_8(LCD_INDEX, 0x01, info);
 348         temp = aty_ld_le32(LCD_DATA, info);
 349         temp = (temp | 0x01) & ~0x02;
 350         aty_st_le32(LCD_DATA, temp, info);
 351
 352         return 0;
 353 }
 354
 355 static char m64n_xl_33[] = "3D RAGE (XL PCI-33MHz)";
 356 static char m64n_xl_66[] = "3D RAGE (XL PCI-66MHz)";
 357
 358 static struct {
 359     u16 pci_id, chip_type;
 360     u8 rev_mask, rev_val;
 361     const char *name;
 362     int pll, mclk, xclk;
 363     u32 features;
 364 } aty_chips[] = {
 365     /* 3D RAGE XL PCI-66/BGA */
 366     { 0x474f, 0x474f, 0x00, 0x00, m64n_xl_66, 230, 83, 63, M64F_GT | M64F_INTEGRATED | M64F_RESET_3D | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL | M64F_EXTRA_BRIGHT | M64F_XL_DLL | M64F_MFB_TIMES_4 },
 367     /* 3D RAGE XL PCI-33/BGA */
 368     { 0x4752, 0x4752, 0x00, 0x00, m64n_xl_33, 230, 83, 63, M64F_GT | M64F_INTEGRATED | M64F_RESET_3D | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL | M64F_EXTRA_BRIGHT | M64F_XL_DLL | M64F_MFB_TIMES_4 },
 369 };
 370 #if 0
 371 static void aty_calc_mem_refresh(struct fb_info_aty *info,
 372                                         u16 id,
 373                                         int xclk)
 374 {
 375         int i, size;
 376         const int ragepro_tbl[] = {
 377                 44, 50, 55, 66, 75, 80, 100
 378         };
 379         const int ragexl_tbl[] = {
 380                 50, 66, 75, 83, 90, 95, 100, 105,
 381                 110, 115, 120, 125, 133, 143, 166
 382         };
 383         const int *refresh_tbl;
 384
 385         if (IS_XL(id)) {
 386                 refresh_tbl = ragexl_tbl;
 387                 size = sizeof(ragexl_tbl)/sizeof(int);
 388         } else {
 389                 refresh_tbl = ragepro_tbl;
 390                 size = sizeof(ragepro_tbl)/sizeof(int);
 391         }
 392
 393         for (i=0; i < size; i++) {
 394                 if (xclk < refresh_tbl[i])
 395                         break;
 396         }
 397
 398         info->mem_refresh_rate = i;
 399 }
 400 #endif
 401 static void ati_ragexl_init(device_t dev) {
 402         u32 chip_id;
 403         u32 i;
 404         int j, k;
 405         u16 type;
 406         u8 rev;
 407         const char *chipname = NULL;
 408         int pll, mclk, xclk;
 409
 410         struct fb_info_aty *info;
 411         struct fb_info_aty info_t;
 412         struct resource *res;
 413         info = &info_t;
 414
 415 #define USE_AUX_REG 1
 416
 417 #if USE_AUX_REG==0
 418         res = &dev->resource[0];
 419         if(res->flags & IORESOURCE_IO) {
 420                 res = &dev->resource[1];
 421         }
 422         info->ati_regbase = res->base+0x7ff000+0xc00;
 423 #else
 424         res = &dev->resource[2];
 425         if(res->flags & IORESOURCE_MEM) {
 426                 info->ati_regbase = res->base+0x400; //using auxiliary register
 427         }
 428
 429 #endif
 430         printk_debug("ati_regbase = 0x%08x\r\n", info->ati_regbase);
 431
 432         chip_id = aty_ld_le32(CONFIG_CHIP_ID, info);
 433         type = chip_id & CFG_CHIP_TYPE;
 434         rev = (chip_id & CFG_CHIP_REV)>>24;
 435         for (j = 0; j < (sizeof(aty_chips)/sizeof(*aty_chips)); j++)
 436                 if (type == aty_chips[j].chip_type &&
 437                         (rev & aty_chips[j].rev_mask) == aty_chips[j].rev_val) {
 438                         chipname = aty_chips[j].name;
 439                         pll = aty_chips[j].pll;
 440                         mclk = aty_chips[j].mclk;
 441                         xclk = aty_chips[j].xclk;
 442                         info->features = aty_chips[j].features;
 443                         goto found;
 444         }
 445         printk_debug("ati_ragexl_init: Unknown mach64 0x%04x rev 0x%04x\n", type, rev);
 446         return ;
 447
 448 found:
 449         printk_debug("ati_ragexl_init: %s [0x%04x rev 0x%02x] ", chipname, type, rev);
 450
 451         if (M64_HAS(INTEGRATED)) {
 452                 /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
 453                 if (mclk == 67 && info->ram_type < SDRAM)
 454                         mclk = 63;
 455         }
 456
 457 //    aty_calc_mem_refresh(info, type, xclk);
 458         info->pll_per = 1000000/pll;
 459         info->mclk_per = 1000000/mclk;
 460         info->xclk_per = 1000000/xclk;
 461
 462 //        info->dac_ops = &aty_dac_ct;
 463 //        info->pll_ops = &aty_pll_ct;
 464         info->bus_type = PCI;
 465
 466
 467         atyfb_xl_init(info);
 468 }
 469
 470 static struct device_operations ati_ragexl_graph_ops  = {
 471         .read_resources   = pci_dev_read_resources,
 472         .set_resources    = pci_dev_set_resources,
 473         .enable_resources = pci_dev_enable_resources,
 474         .init             = ati_ragexl_init,
 475         .scan_bus         = 0,
 476 };
 477
 478 static struct pci_driver ati_ragexl_graph_driver __pci_driver = {
 479         .ops    = &ati_ragexl_graph_ops,
 480         .vendor = PCI_VENDOR_ID_ATI,
 481         .device = PCI_DEVICE_ID_ATI_215XL,
 482 };
 483
 484