src/drivers/ati/ragexl/xlinit.c

   1 /*
   2  *  ATI Rage XL Initialization. Support for Xpert98 and Victoria
   3  *  PCI cards.
   4  *
   5  *  Copyright (C) 2002 MontaVista Software Inc.
   6  *  Author: MontaVista Software, Inc.
   7  *              stevel@mvista.com or source@mvista.com
   8  *  Copyright (C) 2004 Tyan Computer.
   9  *  Auther: Yinghai Lu   yhlu@tyan.com
  10  *         move to coreboot
  11  * This code is distributed without warranty under the GPL v2 (see COPYING) *
  12  */
  13 #include <delay.h>
  14 #include <stdlib.h>
  15 #include <string.h>
  16 #include <arch/io.h>
  17
  18 #include <console/console.h>
  19 #include <device/device.h>
  20 #include <device/pci.h>
  21 #include <device/pci_ids.h>
  22 #include <device/pci_ops.h>
  23
  24 #if CONFIG_CONSOLE_BTEXT==1
  25
  26 #define PLL_CRTC_DECODE 0
  27 #define SUPPORT_8_BPP_ABOVE 0
  28
  29 #include "fb.h"
  30 #include "fbcon.h"
  31
  32 struct aty_cmap_regs {
  33         u8 windex;
  34         u8 lut;
  35         u8 mask;
  36         u8 rindex;
  37         u8 cntl;
  38 };
  39
  40 #include <console/btext.h>
  41
  42 #endif /*CONFIG_CONSOLE_BTEXT*/
  43
  44 #include "mach64.h"
  45
  46 #include "atyfb.h"
  47
  48 #include "mach64_ct.c"
  49
  50 #define MPLL_GAIN       0xad
  51 #define VPLL_GAIN       0xd5
  52
  53 #define HAS_VICTORIA 0
  54
  55 enum {
  56 #if HAS_VICTORIA==1
  57         VICTORIA = 0,
  58         XPERT98,
  59 #else
  60         XPERT98=0,
  61 #endif
  62         NUM_XL_CARDS
  63 };
  64
  65 //static struct aty_pll_ops aty_pll_ct;
  66
  67 #define DEFAULT_CARD XPERT98
  68 static int xl_card = DEFAULT_CARD;
  69
  70 static const struct xl_card_cfg_t {
  71         int ref_crystal; // 10^4 Hz
  72         int mem_type;
  73         int mem_size;
  74         u32 mem_cntl;
  75         u32 ext_mem_cntl;
  76         u32 mem_addr_config;
  77         u32 bus_cntl;
  78         u32 dac_cntl;
  79         u32 hw_debug;
  80         u32 custom_macro_cntl;
  81         u8  dll2_cntl;
  82         u8  pll_yclk_cntl;
  83 } card_cfg[NUM_XL_CARDS] = {
  84 #if HAS_VICTORIA==1
  85         // VICTORIA
  86         {       2700, SDRAM, 0x800000,
  87                 0x10757A3B, 0x64000C81, 0x00110202, 0x7b33A040,
  88                 0x82010102, 0x48803800, 0x005E0179,
  89                 0x50, 0x25
  90         },
  91 #endif
  92         // XPERT98
  93         {       1432,  WRAM, 0x800000,
  94                 0x00165A2B, 0xE0000CF1, 0x00200213, 0x7333A001,
  95                 0x8000000A, 0x48833800, 0x007F0779,
  96                 0x10, 0x19
  97         }
  98 };
  99
 100 typedef struct {
 101         u8 lcd_reg;
 102         u32 val;
 103 } lcd_tbl_t;
 104
 105 static const lcd_tbl_t lcd_tbl[] = {
 106         { 0x01, 0x000520C0 },
 107         { 0x08, 0x02000408 },
 108         { 0x03, 0x00000F00 },
 109         { 0x00, 0x00000000 },
 110         { 0x02, 0x00000000 },
 111         { 0x04, 0x00000000 },
 112         { 0x05, 0x00000000 },
 113         { 0x06, 0x00000000 },
 114         { 0x33, 0x00000000 },
 115         { 0x34, 0x00000000 },
 116         { 0x35, 0x00000000 },
 117         { 0x36, 0x00000000 },
 118         { 0x37, 0x00000000 }
 119 };
 120
 121 static inline u32 aty_ld_lcd(u8 lcd_reg, struct fb_info_aty *info)
 122 {
 123         aty_st_8(LCD_INDEX, lcd_reg, info);
 124         return aty_ld_le32(LCD_DATA, info);
 125 }
 126
 127 static inline void aty_st_lcd(u8 lcd_reg, u32 val,
 128                               struct fb_info_aty *info)
 129 {
 130         aty_st_8(LCD_INDEX, lcd_reg, info);
 131         aty_st_le32(LCD_DATA, val, info);
 132 }
 133
 134 static void reset_gui(struct fb_info_aty *info)
 135 {
 136         aty_st_8(GEN_TEST_CNTL+1, 0x01, info);
 137         aty_st_8(GEN_TEST_CNTL+1, 0x00, info);
 138         aty_st_8(GEN_TEST_CNTL+1, 0x02, info);
 139         mdelay(5);
 140 }
 141
 142
 143 static void reset_sdram(struct fb_info_aty *info)
 144 {
 145         u8 temp;
 146
 147         temp = aty_ld_8(EXT_MEM_CNTL, info);
 148         temp |= 0x02;
 149         aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_SDRAM_RESET = 1b
 150         temp |= 0x08;
 151         aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_CYC_TEST    = 10b
 152         temp |= 0x0c;
 153         aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_CYC_TEST    = 11b
 154         mdelay(5);
 155         temp &= 0xf3;
 156         aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_CYC_TEST    = 00b
 157         temp &= 0xfd;
 158         aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_SDRAM_REST  = 0b
 159         mdelay(5);
 160 }
 161
 162 static void init_dll(struct fb_info_aty *info)
 163 {
 164         // enable DLL
 165         aty_st_pll(PLL_GEN_CNTL,
 166                    aty_ld_pll(PLL_GEN_CNTL, info) & 0x7f,
 167                    info);
 168
 169         // reset DLL
 170         aty_st_pll(DLL_CNTL, 0x82, info);
 171         aty_st_pll(DLL_CNTL, 0xE2, info);
 172         mdelay(5);
 173         aty_st_pll(DLL_CNTL, 0x82, info);
 174         mdelay(6);
 175 }
 176
 177 static void reset_clocks(struct fb_info_aty *info, struct pll_ct *pll,
 178                          int hsync_enb)
 179 {
 180         reset_gui(info);
 181         aty_st_pll(MCLK_FB_DIV, pll->mclk_fb_div, info);
 182         aty_st_pll(SCLK_FB_DIV, pll->sclk_fb_div, info);
 183
 184         mdelay(15);
 185         init_dll(info);
 186         aty_st_8(GEN_TEST_CNTL+1, 0x00, info);
 187         mdelay(5);
 188         aty_st_8(CRTC_GEN_CNTL+3, 0x04, info);
 189         mdelay(6);
 190         reset_sdram(info);
 191         aty_st_8(CRTC_GEN_CNTL+3,
 192                  hsync_enb ? 0x00 : 0x04, info);
 193
 194         aty_st_pll(SPLL_CNTL2, pll->spll_cntl2, info);
 195         aty_st_pll(PLL_GEN_CNTL, pll->pll_gen_cntl, info);
 196         aty_st_pll(PLL_VCLK_CNTL, pll->pll_vclk_cntl, info);
 197 }
 198
 199 static int atyfb_xl_init(struct fb_info_aty *info)
 200 {
 201         int i, err;
 202         u32 temp;
 203         union aty_pll pll;
 204         const struct xl_card_cfg_t * card = &card_cfg[xl_card];
 205
 206         aty_st_8(CONFIG_STAT0, 0x85, info);
 207         mdelay(10);
 208
 209         /*
 210          * The following needs to be set before the call
 211          * to var_to_pll() below. They'll be re-set again
 212          * to the same values in aty_init().
 213          */
 214         info->ref_clk_per = 100000000UL/card->ref_crystal;
 215         info->ram_type = card->mem_type;
 216         info->total_vram = card->mem_size;
 217 #if HAS_VICTORIA == 1
 218         if (xl_card == VICTORIA) {
 219                 // the MCLK, XCLK are 120MHz on victoria card
 220                 info->mclk_per = 1000000/120;
 221                 info->xclk_per = 1000000/120;
 222                 info->features &= ~M64F_MFB_TIMES_4;
 223         }
 224 #endif
 225
 226         /*
 227          * Calculate mclk and xclk dividers, etc. The passed
 228          * pixclock and bpp values don't matter yet, the vclk
 229          * isn't programmed until later.
 230          */
 231         if ((err = aty_var_to_pll_ct(info, 39726, 8, &pll))) return err;
 232 //        if ((err = aty_pll_ct.var_to_pll(info, 39726, 8, &pll))) return err;
 233
 234
 235         aty_st_pll(LVDS_CNTL0, 0x00, info);
 236         aty_st_pll(DLL2_CNTL, card->dll2_cntl, info);
 237         aty_st_pll(V2PLL_CNTL, 0x10, info);
 238         aty_st_pll(MPLL_CNTL, MPLL_GAIN, info);
 239         aty_st_pll(VPLL_CNTL, VPLL_GAIN, info);
 240         aty_st_pll(PLL_VCLK_CNTL, 0x00, info);
 241         aty_st_pll(VFC_CNTL, 0x1B, info);
 242         aty_st_pll(PLL_REF_DIV, pll.ct.pll_ref_div, info);
 243         aty_st_pll(PLL_EXT_CNTL, pll.ct.pll_ext_cntl, info);
 244         aty_st_pll(SPLL_CNTL2, 0x03, info);
 245         aty_st_pll(PLL_GEN_CNTL, 0x44, info);
 246
 247         reset_clocks(info, &pll.ct, 0);
 248         mdelay(10);
 249
 250         aty_st_pll(VCLK_POST_DIV, 0x03, info);
 251         aty_st_pll(VCLK0_FB_DIV, 0xDA, info);
 252         aty_st_pll(VCLK_POST_DIV, 0x0F, info);
 253         aty_st_pll(VCLK1_FB_DIV, 0xF5, info);
 254         aty_st_pll(VCLK_POST_DIV, 0x3F, info);
 255         aty_st_pll(PLL_EXT_CNTL, 0x40 | pll.ct.pll_ext_cntl, info);
 256         aty_st_pll(VCLK2_FB_DIV, 0x00, info);
 257         aty_st_pll(VCLK_POST_DIV, 0xFF, info);
 258         aty_st_pll(PLL_EXT_CNTL, 0xC0 | pll.ct.pll_ext_cntl, info);
 259         aty_st_pll(VCLK3_FB_DIV, 0x00, info);
 260
 261         aty_st_8(BUS_CNTL, 0x01, info);
 262         aty_st_le32(BUS_CNTL, card->bus_cntl | 0x08000000, info);
 263
 264         aty_st_le32(CRTC_GEN_CNTL, 0x04000200, info);
 265         aty_st_le16(CONFIG_STAT0, 0x0020, info);
 266         aty_st_le32(MEM_CNTL, 0x10151A33, info);
 267         aty_st_le32(EXT_MEM_CNTL, 0xE0000C01, info);
 268         aty_st_le16(CRTC_GEN_CNTL+2, 0x0000, info);
 269         aty_st_le32(DAC_CNTL, card->dac_cntl, info);
 270         aty_st_le16(GEN_TEST_CNTL, 0x0100, info);
 271         aty_st_le32(CUSTOM_MACRO_CNTL, 0x003C0171, info);
 272         aty_st_le32(MEM_BUF_CNTL, 0x00382848, info);
 273
 274         aty_st_le32(HW_DEBUG, card->hw_debug, info);
 275         aty_st_le16(MEM_ADDR_CONFIG, 0x0000, info);
 276         aty_st_le16(GP_IO+2, 0x0000, info);
 277         aty_st_le16(GEN_TEST_CNTL, 0x0000, info);
 278         aty_st_le16(EXT_DAC_REGS+2, 0x0000, info);
 279         aty_st_le32(CRTC_INT_CNTL, 0x00000000, info);
 280         aty_st_le32(TIMER_CONFIG, 0x00000000, info);
 281         aty_st_le32(0xEC, 0x00000000, info);
 282         aty_st_le32(0xFC, 0x00000000, info);
 283
 284         for (i=0; i<ARRAY_SIZE(lcd_tbl); i++) {
 285                 aty_st_lcd(lcd_tbl[i].lcd_reg, lcd_tbl[i].val, info);
 286         }
 287
 288         aty_st_le16(CONFIG_STAT0, 0x00A4, info);
 289         mdelay(10);
 290
 291         aty_st_8(BUS_CNTL+1, 0xA0, info);
 292         mdelay(10);
 293
 294         reset_clocks(info, &pll.ct, 1);
 295         mdelay(10);
 296
 297         // something about power management
 298         aty_st_8(LCD_INDEX, 0x08, info);
 299         aty_st_8(LCD_DATA, 0x0A, info);
 300         aty_st_8(LCD_INDEX, 0x08, info);
 301         aty_st_8(LCD_DATA+3, 0x02, info);
 302         aty_st_8(LCD_INDEX, 0x08, info);
 303         aty_st_8(LCD_DATA, 0x0B, info);
 304         mdelay(2);
 305
 306         // enable display requests, enable CRTC
 307         aty_st_8(CRTC_GEN_CNTL+3, 0x02, info);
 308         // disable display
 309         aty_st_8(CRTC_GEN_CNTL, 0x40, info);
 310         // disable display requests, disable CRTC
 311         aty_st_8(CRTC_GEN_CNTL+3, 0x04, info);
 312         mdelay(10);
 313
 314         aty_st_pll(PLL_YCLK_CNTL, 0x25, info);
 315
 316         aty_st_le16(CUSTOM_MACRO_CNTL, 0x0179, info);
 317         aty_st_le16(CUSTOM_MACRO_CNTL+2, 0x005E, info);
 318         aty_st_le16(CUSTOM_MACRO_CNTL+2, card->custom_macro_cntl>>16, info);
 319         aty_st_8(CUSTOM_MACRO_CNTL+1,
 320                  (card->custom_macro_cntl>>8) & 0xff, info);
 321
 322         aty_st_le32(MEM_ADDR_CONFIG, card->mem_addr_config, info);
 323         aty_st_le32(MEM_CNTL, card->mem_cntl, info);
 324         aty_st_le32(EXT_MEM_CNTL, card->ext_mem_cntl, info);
 325
 326         aty_st_8(CONFIG_STAT0, 0xA0 | card->mem_type, info);
 327
 328         aty_st_pll(PLL_YCLK_CNTL, 0x01, info);
 329         mdelay(15);
 330         aty_st_pll(PLL_YCLK_CNTL, card->pll_yclk_cntl, info);
 331         mdelay(1);
 332
 333         reset_clocks(info, &pll.ct, 0);
 334         mdelay(50);
 335         reset_clocks(info, &pll.ct, 0);
 336         mdelay(50);
 337
 338         // enable extended register block
 339         aty_st_8(BUS_CNTL+3, 0x7B, info);
 340         mdelay(1);
 341         // disable extended register block
 342         aty_st_8(BUS_CNTL+3, 0x73, info);
 343
 344         aty_st_8(CONFIG_STAT0, 0x80 | card->mem_type, info);
 345
 346         // disable display requests, disable CRTC
 347         aty_st_8(CRTC_GEN_CNTL+3, 0x04, info);
 348         // disable mapping registers in VGA aperture
 349         aty_st_8(CONFIG_CNTL, aty_ld_8(CONFIG_CNTL, info) & ~0x04, info);
 350         mdelay(50);
 351         // enable display requests, enable CRTC
 352         aty_st_8(CRTC_GEN_CNTL+3, 0x02, info);
 353
 354         // make GPIO's 14,15,16 all inputs
 355         aty_st_8(LCD_INDEX, 0x07, info);
 356         aty_st_8(LCD_DATA+3, 0x00, info);
 357
 358         // enable the display
 359         aty_st_8(CRTC_GEN_CNTL, 0x00, info);
 360         mdelay(17);
 361         // reset the memory controller
 362         aty_st_8(GEN_TEST_CNTL+1, 0x02, info);
 363         mdelay(15);
 364         aty_st_8(GEN_TEST_CNTL+1, 0x00, info);
 365         mdelay(30);
 366
 367         // enable extended register block
 368         aty_st_8(BUS_CNTL+3,
 369                  (u8)(aty_ld_8(BUS_CNTL+3, info) | 0x08),
 370                  info);
 371         // set FIFO size to 512 (PIO)
 372         aty_st_le32(GUI_CNTL,
 373                     aty_ld_le32(GUI_CNTL, info) & ~0x3,
 374                     info);
 375
 376         // enable CRT and disable lcd
 377         aty_st_8(LCD_INDEX, 0x01, info);
 378         temp = aty_ld_le32(LCD_DATA, info);
 379         temp = (temp | 0x01) & ~0x02;
 380         aty_st_le32(LCD_DATA, temp, info);
 381
 382         return 0;
 383 }
 384
 385 static char m64n_xl_33[] = "3D RAGE (XL PCI-33MHz)";
 386 static char m64n_xl_66[] = "3D RAGE (XL PCI-66MHz)";
 387
 388
 389 #if CONFIG_CONSOLE_BTEXT==1
 390 static void aty_set_crtc(const struct fb_info_aty *info,
 391                          const struct crtc *crtc);
 392 static int aty_var_to_crtc(const struct fb_info_aty *info,
 393                            const struct fb_var_screeninfo *var,
 394                            struct crtc *crtc);
 395 #if PLL_CRTC_DECODE==1
 396 static int aty_crtc_to_var(const struct crtc *crtc,
 397                            struct fb_var_screeninfo *var);
 398 #endif
 399
 400 static void atyfb_set_par(const struct atyfb_par *par,
 401                           struct fb_info_aty *info);
 402 static int atyfb_decode_var(const struct fb_var_screeninfo *var,
 403                             struct atyfb_par *par,
 404                             const struct fb_info_aty *info);
 405 #if PLL_CRTC_DECODE==1
 406 static int atyfb_encode_var(struct fb_var_screeninfo *var,
 407                             const struct atyfb_par *par,
 408                             const struct fb_info_aty *info);
 409 #endif
 410
 411 static void do_install_cmap(int con, struct fb_info_aty *info);
 412
 413 #if 0
 414 static u32 default_vram  = 0;
 415 #endif
 416
 417 unsigned char color_table[] = { 0, 4, 2, 6, 1, 5, 3, 7,
 418                                        8,12,10,14, 9,13,11,15 };
 419 #if 0
 420 /* the default colour table, for VGA+ colour systems */
 421 int default_red[] = {0x00,0xaa,0x00,0xaa,0x00,0xaa,0x00,0xaa,
 422     0x55,0xff,0x55,0xff,0x55,0xff,0x55,0xff};
 423 int default_grn[] = {0x00,0x00,0xaa,0x55,0x00,0x00,0xaa,0xaa,
 424     0x55,0x55,0xff,0xff,0x55,0x55,0xff,0xff};
 425 int default_blu[] = {0x00,0x00,0x00,0x00,0xaa,0xaa,0xaa,0xaa,
 426     0x55,0x55,0x55,0x55,0xff,0xff,0xff,0xff};
 427 #endif
 428
 429 struct fb_var_screeninfo default_var = {
 430         /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
 431         640, 480, 640, 480, 0, 0, 8, 0,
 432         {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
 433         0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
 434         0, FB_VMODE_NONINTERLACED
 435 };
 436
 437 #endif /*CONFIG_CONSOLE_BTEXT*/
 438
 439 static struct {
 440         u16 pci_id, chip_type;
 441         u8 rev_mask, rev_val;
 442         const char *name;
 443         int pll, mclk, xclk;
 444         u32 features;
 445 } aty_chips[] = {
 446         /* 3D RAGE XL PCI-66/BGA */
 447         { 0x474f, 0x474f, 0x00, 0x00, m64n_xl_66, 230, 83, 63, M64F_GT | M64F_INTEGRATED | M64F_RESET_3D | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL | M64F_EXTRA_BRIGHT | M64F_XL_DLL | M64F_MFB_TIMES_4 },
 448         /* 3D RAGE XL PCI-33/BGA */
 449         { 0x4752, 0x4752, 0x00, 0x00, m64n_xl_33, 230, 83, 63, M64F_GT | M64F_INTEGRATED | M64F_RESET_3D | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL | M64F_EXTRA_BRIGHT | M64F_XL_DLL | M64F_MFB_TIMES_4 },
 450 };
 451 #if CONFIG_CONSOLE_BTEXT==1
 452 static void aty_calc_mem_refresh(struct fb_info_aty *info, u16 id, int xclk)
 453 {
 454         int i, size;
 455 #if 0
 456         const int ragepro_tbl[] = {
 457                 44, 50, 55, 66, 75, 80, 100
 458         };
 459 #endif
 460         const int ragexl_tbl[] = {
 461                 50, 66, 75, 83, 90, 95, 100, 105,
 462                 110, 115, 120, 125, 133, 143, 166
 463         };
 464         const int *refresh_tbl;
 465 #if 0
 466         if (IS_XL(id)) {
 467 #endif
 468                 refresh_tbl = ragexl_tbl;
 469                 size = sizeof(ragexl_tbl)/sizeof(int);
 470 #if 0
 471         } else {
 472                 refresh_tbl = ragepro_tbl;
 473                 size = sizeof(ragepro_tbl)/sizeof(int);
 474         }
 475 #endif
 476
 477         for (i=0; i < size; i++) {
 478                 if (xclk < refresh_tbl[i])
 479                         break;
 480         }
 481
 482         info->mem_refresh_rate = i;
 483 }
 484 #endif /*CONFIG_CONSOLE_BTEXT */
 485 static void ati_ragexl_init(device_t dev)
 486 {
 487         u32 chip_id;
 488         int j;
 489         u16 type;
 490         u8 rev;
 491         const char *chipname = NULL;
 492 #if CONFIG_CONSOLE_BTEXT
 493         u32 i;
 494         const char *xtal;
 495 #endif
 496         int pll, mclk, xclk;
 497
 498 #if CONFIG_CONSOLE_BTEXT==1
 499
 500 #if 0
 501         int gtb_memsize, k;
 502 #endif
 503
 504         struct fb_var_screeninfo var;
 505 #if 0
 506         struct display *disp;
 507 #endif
 508
 509 #if 0
 510         u8 pll_ref_div;
 511 #endif
 512
 513 #endif /*CONFIG_CONSOLE_BTEXT==1 */
 514
 515         struct fb_info_aty *info;
 516         struct fb_info_aty info_t;
 517         struct resource *res;
 518         info = &info_t;
 519
 520 #define USE_AUX_REG 1
 521
 522
 523         res = &dev->resource[0];
 524         if(res->flags & IORESOURCE_IO) {
 525                 res = &dev->resource[1];
 526         }
 527
 528 #if CONFIG_CONSOLE_BTEXT==1
 529         info->frame_buffer = res->base;
 530 #endif /* CONFIG_CONSOLE_BTEXT */
 531
 532 #if USE_AUX_REG==0
 533         info->ati_regbase = res->base+0x7ff000+0xc00;
 534 #else
 535         res = &dev->resource[2];
 536         if(res->flags & IORESOURCE_MEM) {
 537                 info->ati_regbase = res->base+0x400; //using auxiliary register
 538         }
 539
 540 #endif
 541
 542 #if CONFIG_CONSOLE_BTEXT==1
 543         info->aty_cmap_regs = (struct aty_cmap_regs *)(info->ati_regbase+0xc0);
 544 #endif
 545
 546 #if 0
 547         printk(BIOS_DEBUG, "ati_regbase = 0x%08x, frame_buffer = 0x%08x\n", info->ati_regbase, info->frame_buffer);
 548 #endif
 549
 550         chip_id = aty_ld_le32(CONFIG_CHIP_ID, info);
 551         type = chip_id & CFG_CHIP_TYPE;
 552         rev = (chip_id & CFG_CHIP_REV)>>24;
 553         for (j = 0; j < ARRAY_SIZE(aty_chips); j++)
 554                 if (type == aty_chips[j].chip_type &&
 555                         (rev & aty_chips[j].rev_mask) == aty_chips[j].rev_val) {
 556                         chipname = aty_chips[j].name;
 557                         pll = aty_chips[j].pll;
 558                         mclk = aty_chips[j].mclk;
 559                         xclk = aty_chips[j].xclk;
 560                         info->features = aty_chips[j].features;
 561                         goto found;
 562         }
 563         printk(BIOS_SPEW, "ati_ragexl_init: Unknown mach64 0x%04x rev 0x%04x\n", type, rev);
 564         return ;
 565
 566 found:
 567         printk(BIOS_INFO, "ati_ragexl_init: %s [0x%04x rev 0x%02x]\n", chipname, type, rev);
 568 #if 0
 569         if (M64_HAS(INTEGRATED)) {
 570                 /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
 571                 if (mclk == 67 && info->ram_type < SDRAM)
 572                         mclk = 63;
 573         }
 574 #endif
 575 #if CONFIG_CONSOLE_BTEXT==1
 576         aty_calc_mem_refresh(info, type, xclk);
 577 #endif /* CONFIG_CONSOLE_BTEXT */
 578
 579         info->pll_per = 1000000/pll;
 580         info->mclk_per = 1000000/mclk;
 581         info->xclk_per = 1000000/xclk;
 582
 583 //        info->dac_ops = &aty_dac_ct;
 584 //        info->pll_ops = &aty_pll_ct;
 585         info->bus_type = PCI;
 586
 587
 588         atyfb_xl_init(info);
 589
 590 #if CONFIG_CONSOLE_BTEXT==1
 591
 592         info->ram_type = (aty_ld_le32(CONFIG_STAT0, info) & 0x07);
 593
 594         info->ref_clk_per = 1000000000000ULL/14318180;
 595         xtal = "14.31818";
 596 #if 0
 597         if (M64_HAS(GTB_DSP) && (pll_ref_div = aty_ld_pll(PLL_REF_DIV, info))) {
 598                 int diff1, diff2;
 599                 diff1 = 510*14/pll_ref_div-pll;
 600                 diff2 = 510*29/pll_ref_div-pll;
 601                 if (diff1 < 0)
 602                         diff1 = -diff1;
 603                 if (diff2 < 0)
 604                         diff2 = -diff2;
 605                 if (diff2 < diff1) {
 606                         info->ref_clk_per = 1000000000000ULL/29498928;
 607                         xtal = "29.498928";
 608                 }
 609         }
 610 #endif
 611
 612     i = aty_ld_le32(MEM_CNTL, info);
 613 #if 0
 614     gtb_memsize = M64_HAS(GTB_DSP);
 615     if (gtb_memsize)  // We have
 616 #endif
 617         switch (i & 0xF) {      /* 0xF used instead of MEM_SIZE_ALIAS */
 618             case MEM_SIZE_512K:
 619                 info->total_vram = 0x80000;
 620                 break;
 621             case MEM_SIZE_1M:
 622                 info->total_vram = 0x100000;
 623                 break;
 624             case MEM_SIZE_2M_GTB:
 625                 info->total_vram = 0x200000;
 626                 break;
 627             case MEM_SIZE_4M_GTB:
 628                 info->total_vram = 0x400000;
 629                 break;
 630             case MEM_SIZE_6M_GTB:
 631                 info->total_vram = 0x600000;
 632                 break;
 633             case MEM_SIZE_8M_GTB:
 634                 info->total_vram = 0x800000;
 635                 break;
 636             default:
 637                 info->total_vram = 0x80000;
 638         }
 639 #if 0
 640     else
 641         switch (i & MEM_SIZE_ALIAS) {
 642             case MEM_SIZE_512K:
 643                 info->total_vram = 0x80000;
 644                 break;
 645             case MEM_SIZE_1M:
 646                 info->total_vram = 0x100000;
 647                 break;
 648             case MEM_SIZE_2M:
 649                 info->total_vram = 0x200000;
 650                 break;
 651             case MEM_SIZE_4M:
 652                 info->total_vram = 0x400000;
 653                 break;
 654             case MEM_SIZE_6M:
 655                 info->total_vram = 0x600000;
 656                 break;
 657             case MEM_SIZE_8M:
 658                 info->total_vram = 0x800000;
 659                 break;
 660             default:
 661                 info->total_vram = 0x80000;
 662        }
 663 #endif
 664
 665     if (M64_HAS(MAGIC_VRAM_SIZE)) {
 666         if (aty_ld_le32(CONFIG_STAT1, info) & 0x40000000)
 667           info->total_vram += 0x400000;
 668     }
 669 #if 0
 670     if (default_vram) {
 671         info->total_vram = default_vram*1024;
 672         i = i & ~(gtb_memsize ? 0xF : MEM_SIZE_ALIAS);
 673         if (info->total_vram <= 0x80000)
 674             i |= MEM_SIZE_512K;
 675         else if (info->total_vram <= 0x100000)
 676             i |= MEM_SIZE_1M;
 677         else if (info->total_vram <= 0x200000)
 678             i |= gtb_memsize ? MEM_SIZE_2M_GTB : MEM_SIZE_2M;
 679         else if (info->total_vram <= 0x400000)
 680             i |= gtb_memsize ? MEM_SIZE_4M_GTB : MEM_SIZE_4M;
 681         else if (info->total_vram <= 0x600000)
 682             i |= gtb_memsize ? MEM_SIZE_6M_GTB : MEM_SIZE_6M;
 683         else
 684             i |= gtb_memsize ? MEM_SIZE_8M_GTB : MEM_SIZE_8M;
 685         aty_st_le32(MEM_CNTL, i, info);
 686     }
 687 #endif
 688
 689     /* Clear the video memory */
 690 //    fb_memset((void *)info->frame_buffer, 0, info->total_vram);
 691 #if 0
 692         disp = &info->disp;
 693
 694 //    strcpy(info->fb_info.modename, atyfb_name);
 695     info->fb_info.node = -1;
 696 //    info->fb_info.fbops = &atyfb_ops;
 697     info->fb_info.disp = disp;
 698 //    strcpy(info->fb_info.fontname, fontname);
 699     info->fb_info.changevar = NULL;
 700 //    info->fb_info.switch_con = &atyfbcon_switch;
 701 //    info->fb_info.updatevar = &atyfbcon_updatevar;
 702 //    info->fb_info.blank = &atyfbcon_blank;
 703     info->fb_info.flags = FBINFO_FLAG_DEFAULT;
 704 #endif
 705         var = default_var;
 706
 707 #if 0
 708     if (noaccel)  // We has noaccel in default
 709         var.accel_flags &= ~FB_ACCELF_TEXT;
 710     else
 711         var.accel_flags |= FB_ACCELF_TEXT;
 712 #endif
 713
 714     if (var.yres == var.yres_virtual) {
 715         u32 vram = info->total_vram ;
 716         var.yres_virtual = ((vram * 8) / var.bits_per_pixel) / var.xres_virtual;
 717         if (var.yres_virtual < var.yres)
 718                 var.yres_virtual = var.yres;
 719     }
 720
 721     if (atyfb_decode_var(&var, &info->default_par, info)) {
 722 #if 0
 723         printk(BIOS_DEBUG, "atyfb: can't set default video mode\n");
 724 #endif
 725         return ;
 726     }
 727 #if 0
 728     for (j = 0; j < 16; j++) {
 729         k = color_table[j];
 730         info->palette[j].red = default_red[k];
 731         info->palette[j].green = default_grn[k];
 732         info->palette[j].blue = default_blu[k];
 733     }
 734 #endif
 735
 736 #if 0
 737     if (curblink && M64_HAS(INTEGRATED)) {
 738         info->cursor = aty_init_cursor(info);
 739         if (info->cursor) {
 740             info->dispsw.cursor = atyfb_cursor;
 741             info->dispsw.set_font = atyfb_set_font;
 742         }
 743     }
 744 #endif
 745
 746 #if PLL_CRTC_DECODE==1
 747         atyfb_set_var(&var, -1, &info->fb_info);
 748 #else
 749             atyfb_set_par(&info->default_par, info);
 750 //            do_install_cmap(-1, &info->fb_info);
 751             do_install_cmap(-1, info);
 752 #endif
 753
 754 #if PLL_CRTC_DECODE==1
 755
 756     printk(BIOS_SPEW, "framebuffer=0x%08x, width=%d, height=%d, bpp=%d, pitch=%d\n",info->frame_buffer,
 757                          (((info->current_par.crtc.h_tot_disp>>16) & 0xff)+1)*8,
 758                          ((info->current_par.crtc.v_tot_disp>>16) & 0x7ff)+1,
 759                          info->current_par.crtc.bpp,
 760                          info->current_par.crtc.vxres*info->default_par.crtc.bpp/8
 761                         );
 762  btext_setup_display(
 763                          (((info->current_par.crtc.h_tot_disp>>16) & 0xff)+1)*8,
 764                          ((info->current_par.crtc.v_tot_disp>>16) & 0x7ff)+1,
 765                          info->current_par.crtc.bpp,
 766                          info->current_par.crtc.vxres*info->current_par.crtc.bpp/8,info->frame_buffer);
 767 #else
 768     printk(BIOS_SPEW, "framebuffer=0x%08x, width=%d, height=%d, bpp=%d, pitch=%d\n",info->frame_buffer,
 769                          (((info->default_par.crtc.h_tot_disp>>16) & 0xff)+1)*8,
 770                          ((info->default_par.crtc.v_tot_disp>>16) & 0x7ff)+1,
 771                          info->default_par.crtc.bpp,
 772                          info->default_par.crtc.vxres*info->default_par.crtc.bpp/8
 773                         );
 774  btext_setup_display(
 775                          (((info->default_par.crtc.h_tot_disp>>16) & 0xff)+1)*8,
 776                          ((info->default_par.crtc.v_tot_disp>>16) & 0x7ff)+1,
 777                          info->default_par.crtc.bpp,
 778                          info->default_par.crtc.vxres*info->default_par.crtc.bpp/8,info->frame_buffer);
 779 #endif
 780
 781  btext_clearscreen();
 782
 783  map_boot_text();
 784
 785 #if 0
 786
 787  btext_drawstring("test framebuffer\n");
 788
 789  mdelay(10000);
 790 // test end
 791 #endif
 792
 793 #endif /* CONFIG_CONSOLE_BTEXT */
 794
 795 }
 796
 797 #if CONFIG_CONSOLE_BTEXT==1
 798
 799 static int atyfb_decode_var(const struct fb_var_screeninfo *var,
 800                             struct atyfb_par *par,
 801                             const struct fb_info_aty *info)
 802 {
 803     int err;
 804
 805     if ((err = aty_var_to_crtc(info, var, &par->crtc)) ||
 806         (err = aty_var_to_pll_ct(info, var->pixclock, par->crtc.bpp,
 807                                          &par->pll)))
 808         return err;
 809
 810 #if 0
 811     if (var->accel_flags & FB_ACCELF_TEXT)
 812         par->accel_flags = FB_ACCELF_TEXT;
 813     else
 814 #endif
 815         par->accel_flags = 0;
 816
 817 #if 0 /* fbmon is not done. uncomment for 2.5.x -brad */
 818     if (!fbmon_valid_timings(var->pixclock, htotal, vtotal, info))
 819         return -EINVAL;
 820 #endif
 821
 822     return 0;
 823 }
 824 #if PLL_CRTC_DECODE==1
 825 static int atyfb_encode_var(struct fb_var_screeninfo *var,
 826                             const struct atyfb_par *par,
 827                             const struct fb_info_aty *info)
 828 {
 829     int err;
 830
 831     memset(var, 0, sizeof(struct fb_var_screeninfo));
 832
 833     if ((err = aty_crtc_to_var(&par->crtc, var)))
 834         return err;
 835     var->pixclock = aty_pll_ct_to_var(info, &par->pll);
 836
 837     var->height = -1;
 838     var->width = -1;
 839     var->accel_flags = par->accel_flags;
 840
 841     return 0;
 842 }
 843 #endif
 844 static void aty_set_crtc(const struct fb_info_aty *info,
 845                          const struct crtc *crtc)
 846 {
 847     aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_tot_disp, info);
 848     aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid, info);
 849     aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_tot_disp, info);
 850     aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid, info);
 851     aty_st_le32(CRTC_VLINE_CRNT_VLINE, 0, info);
 852     aty_st_le32(CRTC_OFF_PITCH, crtc->off_pitch, info);
 853     aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl, info);
 854 }
 855
 856 static int aty_var_to_crtc(const struct fb_info_aty *info,
 857                            const struct fb_var_screeninfo *var,
 858                            struct crtc *crtc)
 859 {
 860     u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp;
 861     u32 left, right, upper, lower, hslen, vslen, sync, vmode;
 862     u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol;
 863     u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
 864     u32 pix_width, dp_pix_width, dp_chain_mask;
 865
 866     /* input */
 867     xres = var->xres;
 868     yres = var->yres;
 869     vxres = var->xres_virtual;
 870     vyres = var->yres_virtual;
 871     xoffset = var->xoffset;
 872     yoffset = var->yoffset;
 873     bpp = var->bits_per_pixel;
 874     left = var->left_margin;
 875     right = var->right_margin;
 876     upper = var->upper_margin;
 877     lower = var->lower_margin;
 878     hslen = var->hsync_len;
 879     vslen = var->vsync_len;
 880     sync = var->sync;
 881     vmode = var->vmode;
 882
 883     /* convert (and round up) and validate */
 884     xres = (xres+7) & ~7;
 885     xoffset = (xoffset+7) & ~7;
 886     vxres = (vxres+7) & ~7;
 887     if (vxres < xres+xoffset)
 888         vxres = xres+xoffset;
 889     h_disp = xres/8-1;
 890     if (h_disp > 0xff)
 891         FAIL("h_disp too large");
 892     h_sync_strt = h_disp+(right/8);
 893     if (h_sync_strt > 0x1ff)
 894         FAIL("h_sync_start too large");
 895     h_sync_dly = right & 7;
 896     h_sync_wid = (hslen+7)/8;
 897     if (h_sync_wid > 0x1f)
 898         FAIL("h_sync_wid too large");
 899     h_total = h_sync_strt+h_sync_wid+(h_sync_dly+left+7)/8;
 900     if (h_total > 0x1ff)
 901      FAIL("h_total too large");
 902     h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
 903
 904     if (vyres < yres+yoffset)
 905         vyres = yres+yoffset;
 906     v_disp = yres-1;
 907     if (v_disp > 0x7ff)
 908         FAIL("v_disp too large");
 909     v_sync_strt = v_disp+lower;
 910     if (v_sync_strt > 0x7ff)
 911         FAIL("v_sync_strt too large");
 912     v_sync_wid = vslen;
 913     if (v_sync_wid > 0x1f)
 914         FAIL("v_sync_wid too large");
 915     v_total = v_sync_strt+v_sync_wid+upper;
 916     if (v_total > 0x7ff)
 917         FAIL("v_total too large");
 918     v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
 919
 920     c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? CRTC_CSYNC_EN : 0;
 921
 922     if (bpp <= 8) {
 923         bpp = 8;
 924         pix_width = CRTC_PIX_WIDTH_8BPP;
 925         dp_pix_width = HOST_8BPP | SRC_8BPP | DST_8BPP | BYTE_ORDER_LSB_TO_MSB;
 926         dp_chain_mask = 0x8080;
 927     }
 928 #if SUPPORT_8_BPP_ABOVE==1
 929    else if (bpp <= 16) {
 930         bpp = 16;
 931         pix_width = CRTC_PIX_WIDTH_15BPP;
 932         dp_pix_width = HOST_15BPP | SRC_15BPP | DST_15BPP |
 933                        BYTE_ORDER_LSB_TO_MSB;
 934         dp_chain_mask = 0x4210;
 935     } else if (bpp <= 24 && M64_HAS(INTEGRATED)) {
 936         bpp = 24;
 937         pix_width = CRTC_PIX_WIDTH_24BPP;
 938         dp_pix_width = HOST_8BPP | SRC_8BPP | DST_8BPP | BYTE_ORDER_LSB_TO_MSB;
 939         dp_chain_mask = 0x8080;
 940     } else if (bpp <= 32) {
 941         bpp = 32;
 942         pix_width = CRTC_PIX_WIDTH_32BPP;
 943         dp_pix_width = HOST_32BPP | SRC_32BPP | DST_32BPP |
 944                        BYTE_ORDER_LSB_TO_MSB;
 945         dp_chain_mask = 0x8080;
 946     }
 947 #endif
 948 else
 949         FAIL("invalid bpp");
 950
 951     if (vxres*vyres*bpp/8 > info->total_vram)
 952         FAIL("not enough video RAM");
 953   if ((vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
 954         FAIL("invalid vmode");
 955
 956     /* output */
 957     crtc->vxres = vxres;
 958     crtc->vyres = vyres;
 959     crtc->xoffset = xoffset;
 960     crtc->yoffset = yoffset;
 961     crtc->bpp = bpp;
 962     crtc->h_tot_disp = h_total | (h_disp<<16);
 963     crtc->h_sync_strt_wid = (h_sync_strt & 0xff) | (h_sync_dly<<8) |
 964                             ((h_sync_strt & 0x100)<<4) | (h_sync_wid<<16) |
 965                             (h_sync_pol<<21);
 966     crtc->v_tot_disp = v_total | (v_disp<<16);
 967     crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid<<16) | (v_sync_pol<<21);
 968     crtc->off_pitch = ((yoffset*vxres+xoffset)*bpp/64) | (vxres<<19);
 969     crtc->gen_cntl = pix_width | c_sync | CRTC_EXT_DISP_EN | CRTC_ENABLE;
 970     if (M64_HAS(MAGIC_FIFO)) {
 971         /* Not VTB/GTB */
 972         /* FIXME: magic FIFO values */
 973         crtc->gen_cntl |= aty_ld_le32(CRTC_GEN_CNTL, info) & 0x000e0000;
 974     }
 975     crtc->dp_pix_width = dp_pix_width;
 976     crtc->dp_chain_mask = dp_chain_mask;
 977
 978     return 0;
 979 }
 980 #if PLL_CRTC_DECODE==1
 981 static int aty_crtc_to_var(const struct crtc *crtc,
 982                            struct fb_var_screeninfo *var)
 983 {
 984     u32 xres, yres, bpp, left, right, upper, lower, hslen, vslen, sync;
 985     u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol;
 986     u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
 987     u32 pix_width;
 988
 989     /* input */
 990     h_total = crtc->h_tot_disp & 0x1ff;
 991     h_disp = (crtc->h_tot_disp>>16) & 0xff;
 992     h_sync_strt = (crtc->h_sync_strt_wid & 0xff) |
 993                   ((crtc->h_sync_strt_wid>>4) & 0x100);
 994     h_sync_dly = (crtc->h_sync_strt_wid>>8) & 0x7;
 995     h_sync_wid = (crtc->h_sync_strt_wid>>16) & 0x1f;
 996     h_sync_pol = (crtc->h_sync_strt_wid>>21) & 0x1;
 997     v_total = crtc->v_tot_disp & 0x7ff;
 998     v_disp = (crtc->v_tot_disp>>16) & 0x7ff;
 999     v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1000     v_sync_wid = (crtc->v_sync_strt_wid>>16) & 0x1f;
1001     v_sync_pol = (crtc->v_sync_strt_wid>>21) & 0x1;
1002     c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1003     pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1004
1005     /* convert */
1006     xres = (h_disp+1)*8;
1007     yres = v_disp+1;
1008     left = (h_total-h_sync_strt-h_sync_wid)*8-h_sync_dly;
1009     right = (h_sync_strt-h_disp)*8+h_sync_dly;
1010     hslen = h_sync_wid*8;
1011     upper = v_total-v_sync_strt-v_sync_wid;
1012     lower = v_sync_strt-v_disp;
1013     vslen = v_sync_wid;
1014     sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1015            (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1016            (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1017
1018     switch (pix_width) {
1019 #if 0
1020         case CRTC_PIX_WIDTH_4BPP:
1021             bpp = 4;
1022             var->red.offset = 0;
1023             var->red.length = 8;
1024             var->green.offset = 0;
1025             var->green.length = 8;
1026             var->blue.offset = 0;
1027             var->blue.length = 8;
1028             var->transp.offset = 0;
1029             var->transp.length = 0;
1030             break;
1031 #endif
1032         case CRTC_PIX_WIDTH_8BPP:
1033             bpp = 8;
1034             var->red.offset = 0;
1035             var->red.length = 8;
1036             var->green.offset = 0;
1037             var->green.length = 8;
1038             var->blue.offset = 0;
1039             var->blue.length = 8;
1040             var->transp.offset = 0;
1041             var->transp.length = 0;
1042             break;
1043 #if SUPPORT_8_BPP_ABOVE==1
1044         case CRTC_PIX_WIDTH_15BPP:      /* RGB 555 */
1045             bpp = 16;
1046             var->red.offset = 10;
1047             var->red.length = 5;
1048             var->green.offset = 5;
1049             var->green.length = 5;
1050             var->blue.offset = 0;
1051             var->blue.length = 5;
1052             var->transp.offset = 0;
1053             var->transp.length = 0;
1054             break;
1055         case CRTC_PIX_WIDTH_16BPP:      /* RGB 565 */
1056             bpp = 16;
1057             var->red.offset = 11;
1058             var->red.length = 5;
1059             var->green.offset = 5;
1060             var->green.length = 6;
1061             var->blue.offset = 0;
1062             var->blue.length = 5;
1063             var->transp.offset = 0;
1064             var->transp.length = 0;
1065             break;
1066         case CRTC_PIX_WIDTH_24BPP:      /* RGB 888 */
1067             bpp = 24;
1068             var->red.offset = 16;
1069             var->red.length = 8;
1070             var->green.offset = 8;
1071             var->green.length = 8;
1072             var->blue.offset = 0;
1073             var->blue.length = 8;
1074            var->transp.offset = 0;
1075             var->transp.length = 0;
1076             break;
1077         case CRTC_PIX_WIDTH_32BPP:      /* ARGB 8888 */
1078             bpp = 32;
1079             var->red.offset = 16;
1080             var->red.length = 8;
1081             var->green.offset = 8;
1082             var->green.length = 8;
1083             var->blue.offset = 0;
1084             var->blue.length = 8;
1085             var->transp.offset = 24;
1086             var->transp.length = 8;
1087             break;
1088 #endif
1089         default:
1090             FAIL("Invalid pixel width");
1091     }
1092
1093     /* output */
1094     var->xres = xres;
1095     var->yres = yres;
1096     var->xres_virtual = crtc->vxres;
1097     var->yres_virtual = crtc->vyres;
1098     var->bits_per_pixel = bpp;
1099     var->xoffset = crtc->xoffset;
1100     var->yoffset = crtc->yoffset;
1101     var->left_margin = left;
1102     var->right_margin = right;
1103     var->upper_margin = upper;
1104     var->lower_margin = lower;
1105     var->hsync_len = hslen;
1106     var->vsync_len = vslen;
1107     var->sync = sync;
1108     var->vmode = FB_VMODE_NONINTERLACED;
1109
1110     return 0;
1111 }
1112 #endif
1113
1114 #if 0
1115 static int encode_fix(struct fb_fix_screeninfo *fix,
1116                       const struct atyfb_par *par,
1117                       const struct fb_info_aty *info)
1118 {
1119     memset(fix, 0, sizeof(struct fb_fix_screeninfo));
1120
1121    // strcpy(fix->id, atyfb_name);
1122          memcpy(fix->id, "atyfb", 5);
1123     fix->smem_start = info->frame_buffer;
1124     fix->smem_len = (u32)info->total_vram;
1125
1126     /*
1127      *  Reg Block 0 (CT-compatible block) is at ati_regbase_phys
1128      *  Reg Block 1 (multimedia extensions) is at ati_regbase_phys-0x400
1129      */
1130     if (M64_HAS(GX)) {
1131         fix->mmio_start = info->ati_regbase;
1132         fix->mmio_len = 0x400;
1133         fix->accel = FB_ACCEL_ATI_MACH64GX;
1134     } else if (M64_HAS(CT)) {
1135         fix->mmio_start = info->ati_regbase;
1136         fix->mmio_len = 0x400;
1137         fix->accel = FB_ACCEL_ATI_MACH64CT;
1138     } else if (M64_HAS(VT)) {
1139         fix->mmio_start = info->ati_regbase-0x400;
1140         fix->mmio_len = 0x800;
1141         fix->accel = FB_ACCEL_ATI_MACH64VT;
1142     } else /* if (M64_HAS(GT)) */ {
1143         fix->mmio_start = info->ati_regbase-0x400;
1144         fix->mmio_len = 0x800;
1145         fix->accel = FB_ACCEL_ATI_MACH64GT;
1146     }
1147     fix->type = FB_TYPE_PACKED_PIXELS;
1148     fix->type_aux = 0;
1149     fix->line_length = par->crtc.vxres*par->crtc.bpp/8;
1150     fix->visual = par->crtc.bpp <= 8 ? FB_VISUAL_PSEUDOCOLOR
1151                                      : FB_VISUAL_DIRECTCOLOR;
1152     fix->ywrapstep = 0;
1153     fix->xpanstep = 8;
1154     fix->ypanstep = 1;
1155
1156     return 0;
1157 }
1158 #endif
1159    /*
1160      *  Set the User Defined Part of the Display
1161      */
1162 #if PLL_CRTC_DECODE==1
1163 static int atyfb_set_var(struct fb_var_screeninfo *var, int con,
1164                          struct fb_info *fb)
1165 {
1166     struct fb_info_aty *info = (struct fb_info_aty *)fb;
1167     struct atyfb_par par;
1168 #if 0
1169     struct display *display;
1170     int oldxres, oldyres, oldvxres, oldvyres, oldbpp, oldaccel, accel;
1171 #endif
1172     int err;
1173     int activate = var->activate;
1174
1175 #if 0
1176     if (con >= 0)
1177         display = &fb_display[con];
1178     else
1179 #endif
1180 #if 0
1181         display = fb->disp;     /* used during initialization */
1182 #endif
1183
1184     if ((err = atyfb_decode_var(var, &par, info)))
1185         return err;
1186
1187     atyfb_encode_var(var, &par, (struct fb_info_aty *)info);
1188
1189 #if 0
1190     printk(BIOS_INFO, "atyfb_set_var: activate=%d\n", activate & FB_ACTIVATE_MASK);
1191 #endif
1192
1193     if ((activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) {
1194 #if 0
1195         oldxres = display->var.xres;
1196         oldyres = display->var.yres;
1197         oldvxres = display->var.xres_virtual;
1198         oldvyres = display->var.yres_virtual;
1199         oldbpp = display->var.bits_per_pixel;
1200         oldaccel = display->var.accel_flags;
1201         display->var = *var;
1202         accel = var->accel_flags & FB_ACCELF_TEXT;
1203         if (oldxres != var->xres || oldyres != var->yres ||
1204             oldvxres != var->xres_virtual || oldvyres != var->yres_virtual ||
1205             oldbpp != var->bits_per_pixel || oldaccel != var->accel_flags) {
1206             struct fb_fix_screeninfo fix;
1207
1208             encode_fix(&fix, &par, info);
1209             display->screen_base = (char *)info->frame_buffer;
1210             display->visual = fix.visual;
1211             display->type = fix.type;
1212             display->type_aux = fix.type_aux;
1213             display->ypanstep = fix.ypanstep;
1214             display->ywrapstep = fix.ywrapstep;
1215             display->line_length = fix.line_length;
1216             display->can_soft_blank = 1;
1217             display->inverse = 0;
1218 #if 0
1219            if (accel)
1220                 display->scrollmode = (info->bus_type == PCI) ? SCROLL_YNOMOVE : 0;
1221             else
1222 #endif
1223                 display->scrollmode = SCROLL_YREDRAW;
1224 #if 0
1225             if (info->fb_info.changevar)
1226                 (*info->fb_info.changevar)(con);
1227 #endif
1228         }
1229 #endif
1230 //        if (!info->fb_info.display_fg ||
1231 //            info->fb_info.display_fg->vc_num == con) {
1232             atyfb_set_par(&par, info);
1233 #if 0
1234             atyfb_set_dispsw(display, info, par.crtc.bpp, accel);
1235 #endif
1236 //        }
1237 #if 0
1238         if (oldbpp != var->bits_per_pixel) {
1239             if ((err = fb_alloc_cmap(&display->cmap, 0, 0)))
1240                 return err;
1241 #endif
1242             do_install_cmap(con, info);
1243 #if 0
1244         }
1245 #endif
1246     }
1247
1248     return 0;
1249 }
1250
1251 #endif
1252 /* ------------------------------------------------------------------------- */
1253
1254 static void atyfb_set_par(const struct atyfb_par *par,
1255                           struct fb_info_aty *info)
1256 {
1257     u32 i;
1258     int accelmode;
1259     u8 tmp;
1260
1261     accelmode = par->accel_flags;  /* hack */
1262
1263 #if PLL_CRTC_DECODE==1
1264     info->current_par = *par;
1265 #endif
1266
1267     if (info->blitter_may_be_busy)
1268         wait_for_idle(info);
1269     tmp = aty_ld_8(CRTC_GEN_CNTL + 3, info);
1270     aty_set_crtc(info, &par->crtc);
1271     aty_st_8(CLOCK_CNTL + info->clk_wr_offset, 0, info);
1272                                         /* better call aty_StrobeClock ?? */
1273     aty_st_8(CLOCK_CNTL + info->clk_wr_offset, CLOCK_STROBE, info);
1274
1275     //info->dac_ops->set_dac(info, &par->pll, par->crtc.bpp, accelmode);
1276     //info->pll_ops->set_pll(info, &par->pll);
1277    aty_set_pll_ct(info, &par->pll);
1278
1279
1280     if (!M64_HAS(INTEGRATED)) {
1281         /* Don't forget MEM_CNTL */
1282         i = aty_ld_le32(MEM_CNTL, info) & 0xf0ffffff;
1283         switch (par->crtc.bpp) {
1284             case 8:
1285                 i |= 0x02000000;
1286                 break;
1287 #if SUPPORT_8_BPP_ABOVE==1
1288             case 16:
1289                 i |= 0x03000000;
1290                 break;
1291             case 32:
1292                 i |= 0x06000000;
1293                 break;
1294 #endif
1295         }
1296         aty_st_le32(MEM_CNTL, i, info);
1297     } else {
1298         i = aty_ld_le32(MEM_CNTL, info) & 0xf00fffff;
1299         if (!M64_HAS(MAGIC_POSTDIV))
1300                 i |= info->mem_refresh_rate << 20;
1301         switch (par->crtc.bpp) {
1302             case 8:
1303 #if SUPPORT_8_BPP_ABOVE==1
1304             case 24:
1305 #endif
1306                 i |= 0x00000000;
1307                break;
1308 #if SUPPORT_8_BPP_ABOVE==1
1309             case 16:
1310                 i |= 0x04000000;
1311                 break;
1312             case 32:
1313                 i |= 0x08000000;
1314                 break;
1315 #endif
1316         }
1317         if (M64_HAS(CT_BUS)) {
1318             aty_st_le32(DAC_CNTL, 0x87010184, info);
1319             aty_st_le32(BUS_CNTL, 0x680000f9, info);
1320         } else if (M64_HAS(VT_BUS)) {
1321             aty_st_le32(DAC_CNTL, 0x87010184, info);
1322             aty_st_le32(BUS_CNTL, 0x680000f9, info);
1323         }  else if (M64_HAS(MOBIL_BUS)) {
1324             aty_st_le32(DAC_CNTL, 0x80010102, info);
1325             aty_st_le32(BUS_CNTL, 0x7b33a040, info);
1326         }  else {
1327             /* GT */
1328             aty_st_le32(DAC_CNTL, 0x86010102, info);
1329             aty_st_le32(BUS_CNTL, 0x7b23a040, info);
1330             aty_st_le32(EXT_MEM_CNTL,
1331                         aty_ld_le32(EXT_MEM_CNTL, info) | 0x5000001, info);
1332         }
1333
1334         aty_st_le32(MEM_CNTL, i, info);
1335     }
1336     aty_st_8(DAC_MASK, 0xff, info);
1337
1338     /* Initialize the graphics engine */
1339 #if 0
1340     if (par->accel_flags & FB_ACCELF_TEXT)
1341         aty_init_engine(par, info);
1342 #endif
1343
1344
1345 }
1346 #if 0
1347 static u16 red2[] = {
1348     0x0000, 0xaaaa
1349 };
1350 static u16 green2[] = {
1351     0x0000, 0xaaaa
1352 };
1353 static u16 blue2[] = {
1354     0x0000, 0xaaaa
1355 };
1356
1357 static u16 red4[] = {
1358     0x0000, 0xaaaa, 0x5555, 0xffff
1359 };
1360 static u16 green4[] = {
1361     0x0000, 0xaaaa, 0x5555, 0xffff
1362 };
1363 static u16 blue4[] = {
1364     0x0000, 0xaaaa, 0x5555, 0xffff
1365 };
1366
1367 static u16 red8[] = {
1368     0x0000, 0x0000, 0x0000, 0x0000, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa
1369 };
1370 static u16 green8[] = {
1371     0x0000, 0x0000, 0xaaaa, 0xaaaa, 0x0000, 0x0000, 0x5555, 0xaaaa
1372 };
1373 static u16 blue8[] = {
1374     0x0000, 0xaaaa, 0x0000, 0xaaaa, 0x0000, 0xaaaa, 0x0000, 0xaaaa
1375 };
1376 #endif
1377 static u16 red16[] = {
1378     0x0000, 0x0000, 0x0000, 0x0000, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa,
1379     0x5555, 0x5555, 0x5555, 0x5555, 0xffff, 0xffff, 0xffff, 0xffff
1380 };
1381 static u16 green16[] = {
1382     0x0000, 0x0000, 0xaaaa, 0xaaaa, 0x0000, 0x0000, 0x5555, 0xaaaa,
1383     0x5555, 0x5555, 0xffff, 0xffff, 0x5555, 0x5555, 0xffff, 0xffff
1384 };
1385 static u16 blue16[] = {
1386     0x0000, 0xaaaa, 0x0000, 0xaaaa, 0x0000, 0xaaaa, 0x0000, 0xaaaa,
1387     0x5555, 0xffff, 0x5555, 0xffff, 0x5555, 0xffff, 0x5555, 0xffff
1388 };
1389 #if 0
1390 static struct fb_cmap default_2_colors = {
1391     0, 2, red2, green2, blue2, NULL
1392 };
1393 static struct fb_cmap default_8_colors = {
1394     0, 8, red8, green8, blue8, NULL
1395 };
1396 static struct fb_cmap default_4_colors = {
1397     0, 4, red4, green4, blue4, NULL
1398 };
1399 #endif
1400 static struct fb_cmap default_16_colors = {
1401     0, 16, red16, green16, blue16, NULL
1402 };
1403
1404
1405
1406 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
1407                            u_int transp, struct fb_info_aty *info)
1408 {
1409     int i, scale;
1410
1411     if (regno > 255)
1412         return 1;
1413     red >>= 8;
1414     green >>= 8;
1415     blue >>= 8;
1416 #if 0
1417 //We don't need to store it
1418     info->palette[regno].red = red;
1419     info->palette[regno].green = green;
1420     info->palette[regno].blue = blue;
1421 #endif
1422     i = aty_ld_8(DAC_CNTL, info) & 0xfc;
1423     if (M64_HAS(EXTRA_BRIGHT))
1424         i |= 0x2;       /*DAC_CNTL|0x2 turns off the extra brightness for gt*/
1425     aty_st_8(DAC_CNTL, i, info);
1426     aty_st_8(DAC_MASK, 0xff, info);
1427 #if PLL_CRTC_DECODE==1
1428     scale = (M64_HAS(INTEGRATED) && info->current_par.crtc.bpp == 16) ? 3 : 0;
1429 #else
1430     scale = (M64_HAS(INTEGRATED) && info->default_par.crtc.bpp == 16) ? 3 : 0;
1431 #endif
1432     writeb(regno << scale, &info->aty_cmap_regs->windex);
1433     writeb(red, &info->aty_cmap_regs->lut);
1434     writeb(green, &info->aty_cmap_regs->lut);
1435     writeb(blue, &info->aty_cmap_regs->lut);
1436     return 0;
1437 }
1438
1439 int fb_set_cmap(struct fb_cmap *cmap, int kspc,
1440                 int (*setcolreg)(u_int, u_int, u_int, u_int, u_int,
1441                                  struct fb_info_aty *),
1442                 struct fb_info_aty *info)
1443 {
1444     int i, start;
1445     u16 *red, *green, *blue, *transp;
1446     u_int hred, hgreen, hblue, htransp;
1447
1448     red = cmap->red;
1449     green = cmap->green;
1450     blue = cmap->blue;
1451     transp = cmap->transp;
1452     start = cmap->start;
1453
1454     if (start < 0)
1455         return -EINVAL;
1456     for (i = 0; i < cmap->len; i++) {
1457             hred = *red;
1458             hgreen = *green;
1459             hblue = *blue;
1460             htransp = transp ? *transp : 0;
1461         red++;
1462         green++;
1463         blue++;
1464         if (transp)
1465             transp++;
1466         if (setcolreg(start++, hred, hgreen, hblue, htransp, info))
1467             return 0;
1468     }
1469     return 0;
1470 }
1471
1472 struct fb_cmap *fb_default_cmap(int len)
1473 {
1474 #if 0
1475     if (len <= 2)
1476         return &default_2_colors;
1477     if (len <= 4)
1478         return &default_4_colors;
1479     if (len <= 8)
1480         return &default_8_colors;
1481 #endif
1482     return &default_16_colors;
1483 }
1484
1485 static void do_install_cmap(int con, struct fb_info_aty *info)
1486 {
1487 #if PLL_CRTC_DECODE==1
1488         int size = info->current_par.crtc.bpp == 16 ? 32 : 256;
1489 #else
1490         int size = 256;
1491 #endif
1492         fb_set_cmap(fb_default_cmap(size), 1, atyfb_setcolreg, info);
1493 }
1494
1495 #endif /*CONFIG_CONSOLE_BTEXT */
1496
1497 static struct device_operations ati_ragexl_graph_ops  = {
1498         .read_resources   = pci_dev_read_resources,
1499         .set_resources    = pci_dev_set_resources,
1500         .enable_resources = pci_dev_enable_resources,
1501         .init             = ati_ragexl_init,
1502         .scan_bus         = 0,
1503 };
1504
1505 static const struct pci_driver ati_ragexl_graph_driver __pci_driver = {
1506         .ops    = &ati_ragexl_graph_ops,
1507         .vendor = PCI_VENDOR_ID_ATI,
1508         .device = PCI_DEVICE_ID_ATI_215XL,
1509 };
1510
1511