src/drivers/ati/ragexl/xlinit.c

   1 /*
   2  *  ATI Rage XL Initialization. Support for Xpert98 and Victoria
   3  *  PCI cards.
   4  *
   5  *  Copyright (C) 2002 MontaVista Software Inc.
   6  *  Author: MontaVista Software, Inc.
   7  *              stevel@mvista.com or source@mvista.com
   8  *  Copyright (C) 2004 Tyan Computer.
   9  *  Auther: Yinghai Lu   yhlu@tyan.com
  10  *         move to LinuxBIOS
  11  * This code is distributed without warranty under the GPL v2 (see COPYING) *
  12  */
  13 #include <delay.h>
  14 #include <stdlib.h>
  15 #include <string.h>
  16 #include <arch/io.h>
  17
  18 #include <console/console.h>
  19 #include <device/device.h>
  20 #include <device/pci.h>
  21 #include <device/pci_ids.h>
  22 #include <device/pci_ops.h>
  23
  24 #include "fb.h"
  25 #include "fbcon.h"
  26 #include "mach64.h"
  27
  28 struct aty_cmap_regs {
  29     u8 windex;
  30     u8 lut;
  31     u8 mask;
  32     u8 rindex;
  33     u8 cntl;
  34 };
  35
  36 #include "atyfb.h"
  37
  38 #include <console/btext.h>
  39
  40 #include "mach64_ct.c"
  41
  42 #define MPLL_GAIN       0xad
  43 #define VPLL_GAIN       0xd5
  44
  45 enum {
  46         VICTORIA = 0,
  47         XPERT98,
  48         NUM_XL_CARDS
  49 };
  50
  51 //static struct aty_pll_ops aty_pll_ct;
  52
  53 #define DEFAULT_CARD XPERT98
  54 static int xl_card = DEFAULT_CARD;
  55
  56 static const struct xl_card_cfg_t {
  57         int ref_crystal; // 10^4 Hz
  58         int mem_type;
  59         int mem_size;
  60         u32 mem_cntl;
  61         u32 ext_mem_cntl;
  62         u32 mem_addr_config;
  63         u32 bus_cntl;
  64         u32 dac_cntl;
  65         u32 hw_debug;
  66         u32 custom_macro_cntl;
  67         u8  dll2_cntl;
  68         u8  pll_yclk_cntl;
  69 } card_cfg[NUM_XL_CARDS] = {
  70         // VICTORIA
  71         {       2700, SDRAM, 0x800000,
  72                 0x10757A3B, 0x64000C81, 0x00110202, 0x7b33A040,
  73                 0x82010102, 0x48803800, 0x005E0179,
  74                 0x50, 0x25
  75         },
  76         // XPERT98
  77         {       1432,  WRAM, 0x800000,
  78                 0x00165A2B, 0xE0000CF1, 0x00200213, 0x7333A001,
  79                 0x8000000A, 0x48833800, 0x007F0779,
  80                 0x10, 0x19
  81         }
  82 };
  83
  84 typedef struct {
  85         u8 lcd_reg;
  86         u32 val;
  87 } lcd_tbl_t;
  88
  89 static const lcd_tbl_t lcd_tbl[] = {
  90         { 0x01, 0x000520C0 },
  91         { 0x08, 0x02000408 },
  92         { 0x03, 0x00000F00 },
  93         { 0x00, 0x00000000 },
  94         { 0x02, 0x00000000 },
  95         { 0x04, 0x00000000 },
  96         { 0x05, 0x00000000 },
  97         { 0x06, 0x00000000 },
  98         { 0x33, 0x00000000 },
  99         { 0x34, 0x00000000 },
 100         { 0x35, 0x00000000 },
 101         { 0x36, 0x00000000 },
 102         { 0x37, 0x00000000 }
 103 };
 104
 105 static inline u32 aty_ld_lcd(u8 lcd_reg, struct fb_info_aty *info)
 106 {
 107         aty_st_8(LCD_INDEX, lcd_reg, info);
 108         return aty_ld_le32(LCD_DATA, info);
 109 }
 110
 111 static inline void aty_st_lcd(u8 lcd_reg, u32 val,
 112                               struct fb_info_aty *info)
 113 {
 114         aty_st_8(LCD_INDEX, lcd_reg, info);
 115         aty_st_le32(LCD_DATA, val, info);
 116 }
 117
 118 static void reset_gui(struct fb_info_aty *info)
 119 {
 120         aty_st_8(GEN_TEST_CNTL+1, 0x01, info);
 121         aty_st_8(GEN_TEST_CNTL+1, 0x00, info);
 122         aty_st_8(GEN_TEST_CNTL+1, 0x02, info);
 123         mdelay(5);
 124 }
 125
 126
 127 static void reset_sdram(struct fb_info_aty *info)
 128 {
 129         u8 temp;
 130
 131         temp = aty_ld_8(EXT_MEM_CNTL, info);
 132         temp |= 0x02;
 133         aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_SDRAM_RESET = 1b
 134         temp |= 0x08;
 135         aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_CYC_TEST    = 10b
 136         temp |= 0x0c;
 137         aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_CYC_TEST    = 11b
 138         mdelay(5);
 139         temp &= 0xf3;
 140         aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_CYC_TEST    = 00b
 141         temp &= 0xfd;
 142         aty_st_8(EXT_MEM_CNTL, temp, info); // MEM_SDRAM_REST  = 0b
 143         mdelay(5);
 144 }
 145
 146 static void init_dll(struct fb_info_aty *info)
 147 {
 148         // enable DLL
 149         aty_st_pll(PLL_GEN_CNTL,
 150                    aty_ld_pll(PLL_GEN_CNTL, info) & 0x7f,
 151                    info);
 152
 153         // reset DLL
 154         aty_st_pll(DLL_CNTL, 0x82, info);
 155         aty_st_pll(DLL_CNTL, 0xE2, info);
 156         mdelay(5);
 157         aty_st_pll(DLL_CNTL, 0x82, info);
 158         mdelay(6);
 159 }
 160
 161 static void reset_clocks(struct fb_info_aty *info, struct pll_ct *pll,
 162                          int hsync_enb)
 163 {
 164         reset_gui(info);
 165         aty_st_pll(MCLK_FB_DIV, pll->mclk_fb_div, info);
 166         aty_st_pll(SCLK_FB_DIV, pll->sclk_fb_div, info);
 167
 168         mdelay(15);
 169         init_dll(info);
 170         aty_st_8(GEN_TEST_CNTL+1, 0x00, info);
 171         mdelay(5);
 172         aty_st_8(CRTC_GEN_CNTL+3, 0x04, info);
 173         mdelay(6);
 174         reset_sdram(info);
 175         aty_st_8(CRTC_GEN_CNTL+3,
 176                  hsync_enb ? 0x00 : 0x04, info);
 177
 178         aty_st_pll(SPLL_CNTL2, pll->spll_cntl2, info);
 179         aty_st_pll(PLL_GEN_CNTL, pll->pll_gen_cntl, info);
 180         aty_st_pll(PLL_VCLK_CNTL, pll->pll_vclk_cntl, info);
 181 }
 182
 183 static int atyfb_xl_init(struct fb_info_aty *info)
 184 {
 185         int i, err;
 186         u32 temp;
 187         union aty_pll pll;
 188         const struct xl_card_cfg_t * card = &card_cfg[xl_card];
 189
 190         aty_st_8(CONFIG_STAT0, 0x85, info);
 191         mdelay(10);
 192
 193         /*
 194          * The following needs to be set before the call
 195          * to var_to_pll() below. They'll be re-set again
 196          * to the same values in aty_init().
 197          */
 198         info->ref_clk_per = 100000000UL/card->ref_crystal;
 199         info->ram_type = card->mem_type;
 200         info->total_vram = card->mem_size;
 201         if (xl_card == VICTORIA) {
 202                 // the MCLK, XCLK are 120MHz on victoria card
 203                 info->mclk_per = 1000000/120;
 204                 info->xclk_per = 1000000/120;
 205                 info->features &= ~M64F_MFB_TIMES_4;
 206         }
 207
 208         /*
 209          * Calculate mclk and xclk dividers, etc. The passed
 210          * pixclock and bpp values don't matter yet, the vclk
 211          * isn't programmed until later.
 212          */
 213         if ((err = aty_var_to_pll_ct(info, 39726, 8, &pll))) return err;
 214 //        if ((err = aty_pll_ct.var_to_pll(info, 39726, 8, &pll))) return err;
 215
 216
 217         aty_st_pll(LVDS_CNTL0, 0x00, info);
 218         aty_st_pll(DLL2_CNTL, card->dll2_cntl, info);
 219         aty_st_pll(V2PLL_CNTL, 0x10, info);
 220         aty_st_pll(MPLL_CNTL, MPLL_GAIN, info);
 221         aty_st_pll(VPLL_CNTL, VPLL_GAIN, info);
 222         aty_st_pll(PLL_VCLK_CNTL, 0x00, info);
 223         aty_st_pll(VFC_CNTL, 0x1B, info);
 224         aty_st_pll(PLL_REF_DIV, pll.ct.pll_ref_div, info);
 225         aty_st_pll(PLL_EXT_CNTL, pll.ct.pll_ext_cntl, info);
 226         aty_st_pll(SPLL_CNTL2, 0x03, info);
 227         aty_st_pll(PLL_GEN_CNTL, 0x44, info);
 228
 229         reset_clocks(info, &pll.ct, 0);
 230         mdelay(10);
 231
 232         aty_st_pll(VCLK_POST_DIV, 0x03, info);
 233         aty_st_pll(VCLK0_FB_DIV, 0xDA, info);
 234         aty_st_pll(VCLK_POST_DIV, 0x0F, info);
 235         aty_st_pll(VCLK1_FB_DIV, 0xF5, info);
 236         aty_st_pll(VCLK_POST_DIV, 0x3F, info);
 237         aty_st_pll(PLL_EXT_CNTL, 0x40 | pll.ct.pll_ext_cntl, info);
 238         aty_st_pll(VCLK2_FB_DIV, 0x00, info);
 239         aty_st_pll(VCLK_POST_DIV, 0xFF, info);
 240         aty_st_pll(PLL_EXT_CNTL, 0xC0 | pll.ct.pll_ext_cntl, info);
 241         aty_st_pll(VCLK3_FB_DIV, 0x00, info);
 242
 243         aty_st_8(BUS_CNTL, 0x01, info);
 244         aty_st_le32(BUS_CNTL, card->bus_cntl | 0x08000000, info);
 245
 246         aty_st_le32(CRTC_GEN_CNTL, 0x04000200, info);
 247         aty_st_le16(CONFIG_STAT0, 0x0020, info);
 248         aty_st_le32(MEM_CNTL, 0x10151A33, info);
 249         aty_st_le32(EXT_MEM_CNTL, 0xE0000C01, info);
 250         aty_st_le16(CRTC_GEN_CNTL+2, 0x0000, info);
 251         aty_st_le32(DAC_CNTL, card->dac_cntl, info);
 252         aty_st_le16(GEN_TEST_CNTL, 0x0100, info);
 253         aty_st_le32(CUSTOM_MACRO_CNTL, 0x003C0171, info);
 254         aty_st_le32(MEM_BUF_CNTL, 0x00382848, info);
 255
 256         aty_st_le32(HW_DEBUG, card->hw_debug, info);
 257         aty_st_le16(MEM_ADDR_CONFIG, 0x0000, info);
 258         aty_st_le16(GP_IO+2, 0x0000, info);
 259         aty_st_le16(GEN_TEST_CNTL, 0x0000, info);
 260         aty_st_le16(EXT_DAC_REGS+2, 0x0000, info);
 261         aty_st_le32(CRTC_INT_CNTL, 0x00000000, info);
 262         aty_st_le32(TIMER_CONFIG, 0x00000000, info);
 263         aty_st_le32(0xEC, 0x00000000, info);
 264         aty_st_le32(0xFC, 0x00000000, info);
 265
 266         for (i=0; i<sizeof(lcd_tbl)/sizeof(lcd_tbl_t); i++) {
 267                 aty_st_lcd(lcd_tbl[i].lcd_reg, lcd_tbl[i].val, info);
 268         }
 269
 270         aty_st_le16(CONFIG_STAT0, 0x00A4, info);
 271         mdelay(10);
 272
 273         aty_st_8(BUS_CNTL+1, 0xA0, info);
 274         mdelay(10);
 275
 276         reset_clocks(info, &pll.ct, 1);
 277         mdelay(10);
 278
 279         // something about power management
 280         aty_st_8(LCD_INDEX, 0x08, info);
 281         aty_st_8(LCD_DATA, 0x0A, info);
 282         aty_st_8(LCD_INDEX, 0x08, info);
 283         aty_st_8(LCD_DATA+3, 0x02, info);
 284         aty_st_8(LCD_INDEX, 0x08, info);
 285         aty_st_8(LCD_DATA, 0x0B, info);
 286         mdelay(2);
 287
 288         // enable display requests, enable CRTC
 289         aty_st_8(CRTC_GEN_CNTL+3, 0x02, info);
 290         // disable display
 291         aty_st_8(CRTC_GEN_CNTL, 0x40, info);
 292         // disable display requests, disable CRTC
 293         aty_st_8(CRTC_GEN_CNTL+3, 0x04, info);
 294         mdelay(10);
 295
 296         aty_st_pll(PLL_YCLK_CNTL, 0x25, info);
 297
 298         aty_st_le16(CUSTOM_MACRO_CNTL, 0x0179, info);
 299         aty_st_le16(CUSTOM_MACRO_CNTL+2, 0x005E, info);
 300         aty_st_le16(CUSTOM_MACRO_CNTL+2, card->custom_macro_cntl>>16, info);
 301         aty_st_8(CUSTOM_MACRO_CNTL+1,
 302                  (card->custom_macro_cntl>>8) & 0xff, info);
 303
 304         aty_st_le32(MEM_ADDR_CONFIG, card->mem_addr_config, info);
 305         aty_st_le32(MEM_CNTL, card->mem_cntl, info);
 306         aty_st_le32(EXT_MEM_CNTL, card->ext_mem_cntl, info);
 307
 308         aty_st_8(CONFIG_STAT0, 0xA0 | card->mem_type, info);
 309
 310         aty_st_pll(PLL_YCLK_CNTL, 0x01, info);
 311         mdelay(15);
 312         aty_st_pll(PLL_YCLK_CNTL, card->pll_yclk_cntl, info);
 313         mdelay(1);
 314
 315         reset_clocks(info, &pll.ct, 0);
 316         mdelay(50);
 317         reset_clocks(info, &pll.ct, 0);
 318         mdelay(50);
 319
 320         // enable extended register block
 321         aty_st_8(BUS_CNTL+3, 0x7B, info);
 322         mdelay(1);
 323         // disable extended register block
 324         aty_st_8(BUS_CNTL+3, 0x73, info);
 325
 326         aty_st_8(CONFIG_STAT0, 0x80 | card->mem_type, info);
 327
 328         // disable display requests, disable CRTC
 329         aty_st_8(CRTC_GEN_CNTL+3, 0x04, info);
 330         // disable mapping registers in VGA aperture
 331         aty_st_8(CONFIG_CNTL, aty_ld_8(CONFIG_CNTL, info) & ~0x04, info);
 332         mdelay(50);
 333         // enable display requests, enable CRTC
 334         aty_st_8(CRTC_GEN_CNTL+3, 0x02, info);
 335
 336         // make GPIO's 14,15,16 all inputs
 337         aty_st_8(LCD_INDEX, 0x07, info);
 338         aty_st_8(LCD_DATA+3, 0x00, info);
 339
 340         // enable the display
 341         aty_st_8(CRTC_GEN_CNTL, 0x00, info);
 342         mdelay(17);
 343         // reset the memory controller
 344         aty_st_8(GEN_TEST_CNTL+1, 0x02, info);
 345         mdelay(15);
 346         aty_st_8(GEN_TEST_CNTL+1, 0x00, info);
 347         mdelay(30);
 348
 349         // enable extended register block
 350         aty_st_8(BUS_CNTL+3,
 351                  (u8)(aty_ld_8(BUS_CNTL+3, info) | 0x08),
 352                  info);
 353         // set FIFO size to 512 (PIO)
 354         aty_st_le32(GUI_CNTL,
 355                     aty_ld_le32(GUI_CNTL, info) & ~0x3,
 356                     info);
 357
 358         // enable CRT and disable lcd
 359         aty_st_8(LCD_INDEX, 0x01, info);
 360         temp = aty_ld_le32(LCD_DATA, info);
 361         temp = (temp | 0x01) & ~0x02;
 362         aty_st_le32(LCD_DATA, temp, info);
 363
 364         return 0;
 365 }
 366
 367 static char m64n_xl_33[] = "3D RAGE (XL PCI-33MHz)";
 368 static char m64n_xl_66[] = "3D RAGE (XL PCI-66MHz)";
 369
 370 static void aty_set_crtc(const struct fb_info_aty *info,
 371                          const struct crtc *crtc);
 372 static int aty_var_to_crtc(const struct fb_info_aty *info,
 373                            const struct fb_var_screeninfo *var,
 374                            struct crtc *crtc);
 375 #if 0
 376 static int aty_crtc_to_var(const struct crtc *crtc,
 377                            struct fb_var_screeninfo *var);
 378 #endif
 379
 380 static void atyfb_set_par(const struct atyfb_par *par,
 381                           struct fb_info_aty *info);
 382 static int atyfb_decode_var(const struct fb_var_screeninfo *var,
 383                             struct atyfb_par *par,
 384                             const struct fb_info_aty *info);
 385 #if 0
 386 static int atyfb_encode_var(struct fb_var_screeninfo *var,
 387                             const struct atyfb_par *par,
 388                             const struct fb_info_aty *info);
 389 #endif
 390
 391 static void do_install_cmap(int con, struct fb_info *fb);
 392
 393 #if 0
 394 static u32 default_vram  = 0;
 395 #endif
 396
 397 unsigned char color_table[] = { 0, 4, 2, 6, 1, 5, 3, 7,
 398                                        8,12,10,14, 9,13,11,15 };
 399 #if 0
 400 /* the default colour table, for VGA+ colour systems */
 401 int default_red[] = {0x00,0xaa,0x00,0xaa,0x00,0xaa,0x00,0xaa,
 402     0x55,0xff,0x55,0xff,0x55,0xff,0x55,0xff};
 403 int default_grn[] = {0x00,0x00,0xaa,0x55,0x00,0x00,0xaa,0xaa,
 404     0x55,0x55,0xff,0xff,0x55,0x55,0xff,0xff};
 405 int default_blu[] = {0x00,0x00,0x00,0x00,0xaa,0xaa,0xaa,0xaa,
 406     0x55,0x55,0x55,0x55,0xff,0xff,0xff,0xff};
 407 #endif
 408
 409 struct fb_var_screeninfo default_var = {
 410     /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
 411     640, 480, 640, 480, 0, 0, 8, 0,
 412     {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
 413     0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
 414     0, FB_VMODE_NONINTERLACED
 415 };
 416
 417 static struct {
 418     u16 pci_id, chip_type;
 419     u8 rev_mask, rev_val;
 420     const char *name;
 421     int pll, mclk, xclk;
 422     u32 features;
 423 } aty_chips[] = {
 424     /* 3D RAGE XL PCI-66/BGA */
 425     { 0x474f, 0x474f, 0x00, 0x00, m64n_xl_66, 230, 83, 63, M64F_GT | M64F_INTEGRATED | M64F_RESET_3D | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL | M64F_EXTRA_BRIGHT | M64F_XL_DLL | M64F_MFB_TIMES_4 },
 426     /* 3D RAGE XL PCI-33/BGA */
 427     { 0x4752, 0x4752, 0x00, 0x00, m64n_xl_33, 230, 83, 63, M64F_GT | M64F_INTEGRATED | M64F_RESET_3D | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL | M64F_EXTRA_BRIGHT | M64F_XL_DLL | M64F_MFB_TIMES_4 },
 428 };
 429 #if 1
 430 static void aty_calc_mem_refresh(struct fb_info_aty *info,
 431                                         u16 id,
 432                                         int xclk)
 433 {
 434         int i, size;
 435 #if 0
 436         const int ragepro_tbl[] = {
 437                 44, 50, 55, 66, 75, 80, 100
 438         };
 439 #endif
 440         const int ragexl_tbl[] = {
 441                 50, 66, 75, 83, 90, 95, 100, 105,
 442                 110, 115, 120, 125, 133, 143, 166
 443         };
 444         const int *refresh_tbl;
 445 #if 0
 446         if (IS_XL(id)) {
 447 #endif
 448                 refresh_tbl = ragexl_tbl;
 449                 size = sizeof(ragexl_tbl)/sizeof(int);
 450 #if 0
 451         } else {
 452                 refresh_tbl = ragepro_tbl;
 453                 size = sizeof(ragepro_tbl)/sizeof(int);
 454         }
 455 #endif
 456
 457         for (i=0; i < size; i++) {
 458                 if (xclk < refresh_tbl[i])
 459                         break;
 460         }
 461
 462         info->mem_refresh_rate = i;
 463 }
 464 #endif
 465 static void ati_ragexl_init(device_t dev) {
 466         u32 chip_id;
 467         u32 i;
 468         int j;
 469         u16 type;
 470         u8 rev;
 471         const char *chipname = NULL, *xtal;
 472         int pll, mclk, xclk;
 473 #if 0
 474         int gtb_memsize, k;
 475 #endif
 476
 477         struct fb_info_aty *info;
 478         struct fb_info_aty info_t;
 479         struct resource *res;
 480         info = &info_t;
 481
 482         struct fb_var_screeninfo var;
 483 #if 0
 484         struct display *disp;
 485 #endif
 486
 487 #if 0
 488         u8 pll_ref_div;
 489 #endif
 490
 491 #define USE_AUX_REG 1
 492
 493         res = &dev->resource[0];
 494         if(res->flags & IORESOURCE_IO) {
 495                 res = &dev->resource[1];
 496         }
 497         info->frame_buffer = res->base;
 498 #if USE_AUX_REG==0
 499         info->ati_regbase = res->base+0x7ff000+0xc00;
 500 #else
 501         res = &dev->resource[2];
 502         if(res->flags & IORESOURCE_MEM) {
 503                 info->ati_regbase = res->base+0x400; //using auxiliary register
 504         }
 505
 506 #endif
 507         printk_info("ati_regbase = 0x%08x, frame_buffer = 0x%08x\r\n", info->ati_regbase, info->frame_buffer);
 508
 509         info->aty_cmap_regs = (struct aty_cmap_regs *)(info->ati_regbase+0xc0);
 510
 511         chip_id = aty_ld_le32(CONFIG_CHIP_ID, info);
 512         type = chip_id & CFG_CHIP_TYPE;
 513         rev = (chip_id & CFG_CHIP_REV)>>24;
 514         for (j = 0; j < (sizeof(aty_chips)/sizeof(*aty_chips)); j++)
 515                 if (type == aty_chips[j].chip_type &&
 516                         (rev & aty_chips[j].rev_mask) == aty_chips[j].rev_val) {
 517                         chipname = aty_chips[j].name;
 518                         pll = aty_chips[j].pll;
 519                         mclk = aty_chips[j].mclk;
 520                         xclk = aty_chips[j].xclk;
 521                         info->features = aty_chips[j].features;
 522                         goto found;
 523         }
 524         printk_debug("ati_ragexl_init: Unknown mach64 0x%04x rev 0x%04x\n", type, rev);
 525         return ;
 526
 527 found:
 528         printk_info("ati_ragexl_init: %s [0x%04x rev 0x%02x]\r\n", chipname, type, rev);
 529 #if 0
 530         if (M64_HAS(INTEGRATED)) {
 531                 /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
 532                 if (mclk == 67 && info->ram_type < SDRAM)
 533                         mclk = 63;
 534         }
 535 #endif
 536         aty_calc_mem_refresh(info, type, xclk);
 537         info->pll_per = 1000000/pll;
 538         info->mclk_per = 1000000/mclk;
 539         info->xclk_per = 1000000/xclk;
 540
 541 //        info->dac_ops = &aty_dac_ct;
 542 //        info->pll_ops = &aty_pll_ct;
 543         info->bus_type = PCI;
 544
 545
 546         atyfb_xl_init(info);
 547
 548         info->ram_type = (aty_ld_le32(CONFIG_STAT0, info) & 0x07);
 549
 550         info->ref_clk_per = 1000000000000ULL/14318180;
 551         xtal = "14.31818";
 552 #if 0
 553         if (M64_HAS(GTB_DSP) && (pll_ref_div = aty_ld_pll(PLL_REF_DIV, info))) {
 554                 int diff1, diff2;
 555                 diff1 = 510*14/pll_ref_div-pll;
 556                 diff2 = 510*29/pll_ref_div-pll;
 557                 if (diff1 < 0)
 558                         diff1 = -diff1;
 559                 if (diff2 < 0)
 560                         diff2 = -diff2;
 561                 if (diff2 < diff1) {
 562                         info->ref_clk_per = 1000000000000ULL/29498928;
 563                         xtal = "29.498928";
 564                 }
 565         }
 566 #endif
 567
 568     i = aty_ld_le32(MEM_CNTL, info);
 569 #if 0
 570     gtb_memsize = M64_HAS(GTB_DSP);
 571     if (gtb_memsize)  // We have
 572 #endif
 573         switch (i & 0xF) {      /* 0xF used instead of MEM_SIZE_ALIAS */
 574             case MEM_SIZE_512K:
 575                 info->total_vram = 0x80000;
 576                 break;
 577             case MEM_SIZE_1M:
 578                 info->total_vram = 0x100000;
 579                 break;
 580             case MEM_SIZE_2M_GTB:
 581                 info->total_vram = 0x200000;
 582                 break;
 583             case MEM_SIZE_4M_GTB:
 584                 info->total_vram = 0x400000;
 585                 break;
 586             case MEM_SIZE_6M_GTB:
 587                 info->total_vram = 0x600000;
 588                 break;
 589             case MEM_SIZE_8M_GTB:
 590                 info->total_vram = 0x800000;
 591                 break;
 592             default:
 593                 info->total_vram = 0x80000;
 594         }
 595 #if 0
 596     else
 597         switch (i & MEM_SIZE_ALIAS) {
 598             case MEM_SIZE_512K:
 599                 info->total_vram = 0x80000;
 600                 break;
 601             case MEM_SIZE_1M:
 602                 info->total_vram = 0x100000;
 603                 break;
 604             case MEM_SIZE_2M:
 605                 info->total_vram = 0x200000;
 606                 break;
 607             case MEM_SIZE_4M:
 608                 info->total_vram = 0x400000;
 609                 break;
 610             case MEM_SIZE_6M:
 611                 info->total_vram = 0x600000;
 612                 break;
 613             case MEM_SIZE_8M:
 614                 info->total_vram = 0x800000;
 615                 break;
 616             default:
 617                 info->total_vram = 0x80000;
 618        }
 619 #endif
 620
 621     if (M64_HAS(MAGIC_VRAM_SIZE)) {
 622         if (aty_ld_le32(CONFIG_STAT1, info) & 0x40000000)
 623           info->total_vram += 0x400000;
 624     }
 625 #if 0
 626     if (default_vram) {
 627         info->total_vram = default_vram*1024;
 628         i = i & ~(gtb_memsize ? 0xF : MEM_SIZE_ALIAS);
 629         if (info->total_vram <= 0x80000)
 630             i |= MEM_SIZE_512K;
 631         else if (info->total_vram <= 0x100000)
 632             i |= MEM_SIZE_1M;
 633         else if (info->total_vram <= 0x200000)
 634             i |= gtb_memsize ? MEM_SIZE_2M_GTB : MEM_SIZE_2M;
 635         else if (info->total_vram <= 0x400000)
 636             i |= gtb_memsize ? MEM_SIZE_4M_GTB : MEM_SIZE_4M;
 637         else if (info->total_vram <= 0x600000)
 638             i |= gtb_memsize ? MEM_SIZE_6M_GTB : MEM_SIZE_6M;
 639         else
 640             i |= gtb_memsize ? MEM_SIZE_8M_GTB : MEM_SIZE_8M;
 641         aty_st_le32(MEM_CNTL, i, info);
 642     }
 643 #endif
 644
 645     /* Clear the video memory */
 646 //    fb_memset((void *)info->frame_buffer, 0, info->total_vram);
 647 #if 0
 648         disp = &info->disp;
 649
 650 //    strcpy(info->fb_info.modename, atyfb_name);
 651     info->fb_info.node = -1;
 652 //    info->fb_info.fbops = &atyfb_ops;
 653     info->fb_info.disp = disp;
 654 //    strcpy(info->fb_info.fontname, fontname);
 655     info->fb_info.changevar = NULL;
 656 //    info->fb_info.switch_con = &atyfbcon_switch;
 657 //    info->fb_info.updatevar = &atyfbcon_updatevar;
 658 //    info->fb_info.blank = &atyfbcon_blank;
 659     info->fb_info.flags = FBINFO_FLAG_DEFAULT;
 660 #endif
 661         var = default_var;
 662
 663 #if 0
 664     if (noaccel)  // We has noaccel in default
 665         var.accel_flags &= ~FB_ACCELF_TEXT;
 666     else
 667         var.accel_flags |= FB_ACCELF_TEXT;
 668 #endif
 669
 670     if (var.yres == var.yres_virtual) {
 671         u32 vram = info->total_vram ;
 672         var.yres_virtual = ((vram * 8) / var.bits_per_pixel) / var.xres_virtual;
 673         if (var.yres_virtual < var.yres)
 674                 var.yres_virtual = var.yres;
 675     }
 676
 677     if (atyfb_decode_var(&var, &info->default_par, info)) {
 678         printk_debug("atyfb: can't set default video mode\n");
 679         return ;
 680     }
 681 #if 0
 682     for (j = 0; j < 16; j++) {
 683         k = color_table[j];
 684         info->palette[j].red = default_red[k];
 685         info->palette[j].green = default_grn[k];
 686         info->palette[j].blue = default_blu[k];
 687     }
 688 #endif
 689
 690 #if 0
 691     if (curblink && M64_HAS(INTEGRATED)) {
 692         info->cursor = aty_init_cursor(info);
 693         if (info->cursor) {
 694             info->dispsw.cursor = atyfb_cursor;
 695             info->dispsw.set_font = atyfb_set_font;
 696         }
 697     }
 698 #endif
 699
 700 #if 0
 701         atyfb_set_var(&var, -1, &info->fb_info);
 702 #else
 703             atyfb_set_par(&info->default_par, info);
 704             do_install_cmap(-1, &info->fb_info);
 705 #endif
 706
 707 #if 0
 708
 709     printk_info("framebuffer=0x%08x, width=%d, height=%d, bpp=%d, pitch=%d\n",info->frame_buffer,
 710                          (((info->current_par.crtc.h_tot_disp>>16) & 0xff)+1)*8,
 711                          ((info->current_par.crtc.v_tot_disp>>16) & 0x7ff)+1,
 712                          info->current_par.crtc.bpp,
 713                          info->current_par.crtc.vxres*info->default_par.crtc.bpp/8
 714                         );
 715  btext_setup_display(
 716                          (((info->current_par.crtc.h_tot_disp>>16) & 0xff)+1)*8,
 717                          ((info->current_par.crtc.v_tot_disp>>16) & 0x7ff)+1,
 718                          info->current_par.crtc.bpp,
 719                          info->current_par.crtc.vxres*info->current_par.crtc.bpp/8,info->frame_buffer);
 720 #else
 721     printk_debug("framebuffer=0x%08x, width=%d, height=%d, bpp=%d, pitch=%d\n",info->frame_buffer,
 722                          (((info->default_par.crtc.h_tot_disp>>16) & 0xff)+1)*8,
 723                          ((info->default_par.crtc.v_tot_disp>>16) & 0x7ff)+1,
 724                          info->default_par.crtc.bpp,
 725                          info->default_par.crtc.vxres*info->default_par.crtc.bpp/8
 726                         );
 727  btext_setup_display(
 728                          (((info->default_par.crtc.h_tot_disp>>16) & 0xff)+1)*8,
 729                          ((info->default_par.crtc.v_tot_disp>>16) & 0x7ff)+1,
 730                          info->default_par.crtc.bpp,
 731                          info->default_par.crtc.vxres*info->default_par.crtc.bpp/8,info->frame_buffer);
 732 #endif
 733
 734  btext_clearscreen();
 735
 736  map_boot_text();
 737
 738 #if 0
 739  btext_drawstring("1\n");
 740  btext_drawstring("2\n");
 741  btext_drawstring("3\n");
 742  btext_drawstring("4\n");
 743  btext_drawstring("test framebuffer 5\n");
 744  btext_drawstring("test framebuffer 6\n");
 745  btext_drawstring("test framebuffer 7\n");
 746  btext_drawstring("test framebuffer 8\n");
 747  btext_drawstring("test framebuffer 9\n");
 748  btext_drawstring("test framebuffer 10\n");
 749  btext_drawstring("test framebuffer 11\n");
 750  btext_drawstring("test framebuffer 12\n");
 751  btext_drawstring("test framebuffer 13\n");
 752  btext_drawstring("test framebuffer 14\n");
 753  btext_drawstring("test framebuffer 15\n");
 754  btext_drawstring("test framebuffer 16\n");
 755  btext_drawstring("test framebuffer 17\n");
 756  btext_drawstring("test framebuffer 18\n");
 757  btext_drawstring("test framebuffer 19\n");
 758  btext_drawstring("test framebuffer 20\n");
 759  btext_drawstring("test framebuffer 21\n");
 760  btext_drawstring("test framebuffer 22\n");
 761  btext_drawstring("test framebuffer 23\n");
 762  btext_drawstring("test framebuffer 24\n");
 763
 764  mdelay(10000);
 765 // test end
 766 #endif
 767
 768 }
 769
 770 static int atyfb_decode_var(const struct fb_var_screeninfo *var,
 771                             struct atyfb_par *par,
 772                             const struct fb_info_aty *info)
 773 {
 774     int err;
 775
 776     if ((err = aty_var_to_crtc(info, var, &par->crtc)) ||
 777         (err = aty_var_to_pll_ct(info, var->pixclock, par->crtc.bpp,
 778                                          &par->pll)))
 779         return err;
 780
 781 #if 0
 782     if (var->accel_flags & FB_ACCELF_TEXT)
 783         par->accel_flags = FB_ACCELF_TEXT;
 784     else
 785 #endif
 786         par->accel_flags = 0;
 787
 788 #if 0 /* fbmon is not done. uncomment for 2.5.x -brad */
 789     if (!fbmon_valid_timings(var->pixclock, htotal, vtotal, info))
 790         return -EINVAL;
 791 #endif
 792
 793     return 0;
 794 }
 795 #if 0
 796 static int atyfb_encode_var(struct fb_var_screeninfo *var,
 797                             const struct atyfb_par *par,
 798                             const struct fb_info_aty *info)
 799 {
 800     int err;
 801
 802     memset(var, 0, sizeof(struct fb_var_screeninfo));
 803
 804     if ((err = aty_crtc_to_var(&par->crtc, var)))
 805         return err;
 806     var->pixclock = aty_pll_ct_to_var(info, &par->pll);
 807
 808     var->height = -1;
 809     var->width = -1;
 810     var->accel_flags = par->accel_flags;
 811
 812     return 0;
 813 }
 814 #endif
 815 static void aty_set_crtc(const struct fb_info_aty *info,
 816                          const struct crtc *crtc)
 817 {
 818     aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_tot_disp, info);
 819     aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid, info);
 820     aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_tot_disp, info);
 821     aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid, info);
 822     aty_st_le32(CRTC_VLINE_CRNT_VLINE, 0, info);
 823     aty_st_le32(CRTC_OFF_PITCH, crtc->off_pitch, info);
 824     aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl, info);
 825 }
 826
 827 static int aty_var_to_crtc(const struct fb_info_aty *info,
 828                            const struct fb_var_screeninfo *var,
 829                            struct crtc *crtc)
 830 {
 831     u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp;
 832     u32 left, right, upper, lower, hslen, vslen, sync, vmode;
 833     u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol;
 834     u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
 835     u32 pix_width, dp_pix_width, dp_chain_mask;
 836
 837     /* input */
 838     xres = var->xres;
 839     yres = var->yres;
 840     vxres = var->xres_virtual;
 841     vyres = var->yres_virtual;
 842     xoffset = var->xoffset;
 843     yoffset = var->yoffset;
 844     bpp = var->bits_per_pixel;
 845     left = var->left_margin;
 846     right = var->right_margin;
 847     upper = var->upper_margin;
 848     lower = var->lower_margin;
 849     hslen = var->hsync_len;
 850     vslen = var->vsync_len;
 851     sync = var->sync;
 852     vmode = var->vmode;
 853
 854     /* convert (and round up) and validate */
 855     xres = (xres+7) & ~7;
 856     xoffset = (xoffset+7) & ~7;
 857     vxres = (vxres+7) & ~7;
 858     if (vxres < xres+xoffset)
 859         vxres = xres+xoffset;
 860     h_disp = xres/8-1;
 861     if (h_disp > 0xff)
 862         FAIL("h_disp too large");
 863     h_sync_strt = h_disp+(right/8);
 864     if (h_sync_strt > 0x1ff)
 865         FAIL("h_sync_start too large");
 866     h_sync_dly = right & 7;
 867     h_sync_wid = (hslen+7)/8;
 868     if (h_sync_wid > 0x1f)
 869         FAIL("h_sync_wid too large");
 870     h_total = h_sync_strt+h_sync_wid+(h_sync_dly+left+7)/8;
 871     if (h_total > 0x1ff)
 872      FAIL("h_total too large");
 873     h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
 874
 875     if (vyres < yres+yoffset)
 876         vyres = yres+yoffset;
 877     v_disp = yres-1;
 878     if (v_disp > 0x7ff)
 879         FAIL("v_disp too large");
 880     v_sync_strt = v_disp+lower;
 881     if (v_sync_strt > 0x7ff)
 882         FAIL("v_sync_strt too large");
 883     v_sync_wid = vslen;
 884     if (v_sync_wid > 0x1f)
 885         FAIL("v_sync_wid too large");
 886     v_total = v_sync_strt+v_sync_wid+upper;
 887     if (v_total > 0x7ff)
 888         FAIL("v_total too large");
 889     v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
 890
 891     c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? CRTC_CSYNC_EN : 0;
 892
 893     if (bpp <= 8) {
 894         bpp = 8;
 895         pix_width = CRTC_PIX_WIDTH_8BPP;
 896         dp_pix_width = HOST_8BPP | SRC_8BPP | DST_8BPP | BYTE_ORDER_LSB_TO_MSB;
 897         dp_chain_mask = 0x8080;
 898     }
 899 #if 0
 900    else if (bpp <= 16) {
 901         bpp = 16;
 902         pix_width = CRTC_PIX_WIDTH_15BPP;
 903         dp_pix_width = HOST_15BPP | SRC_15BPP | DST_15BPP |
 904                        BYTE_ORDER_LSB_TO_MSB;
 905         dp_chain_mask = 0x4210;
 906     } else if (bpp <= 24 && M64_HAS(INTEGRATED)) {
 907         bpp = 24;
 908         pix_width = CRTC_PIX_WIDTH_24BPP;
 909         dp_pix_width = HOST_8BPP | SRC_8BPP | DST_8BPP | BYTE_ORDER_LSB_TO_MSB;
 910         dp_chain_mask = 0x8080;
 911     } else if (bpp <= 32) {
 912         bpp = 32;
 913         pix_width = CRTC_PIX_WIDTH_32BPP;
 914         dp_pix_width = HOST_32BPP | SRC_32BPP | DST_32BPP |
 915                        BYTE_ORDER_LSB_TO_MSB;
 916         dp_chain_mask = 0x8080;
 917     }
 918 #endif
 919 else
 920         FAIL("invalid bpp");
 921
 922     if (vxres*vyres*bpp/8 > info->total_vram)
 923         FAIL("not enough video RAM");
 924   if ((vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
 925         FAIL("invalid vmode");
 926
 927     /* output */
 928     crtc->vxres = vxres;
 929     crtc->vyres = vyres;
 930     crtc->xoffset = xoffset;
 931     crtc->yoffset = yoffset;
 932     crtc->bpp = bpp;
 933     crtc->h_tot_disp = h_total | (h_disp<<16);
 934     crtc->h_sync_strt_wid = (h_sync_strt & 0xff) | (h_sync_dly<<8) |
 935                             ((h_sync_strt & 0x100)<<4) | (h_sync_wid<<16) |
 936                             (h_sync_pol<<21);
 937     crtc->v_tot_disp = v_total | (v_disp<<16);
 938     crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid<<16) | (v_sync_pol<<21);
 939     crtc->off_pitch = ((yoffset*vxres+xoffset)*bpp/64) | (vxres<<19);
 940     crtc->gen_cntl = pix_width | c_sync | CRTC_EXT_DISP_EN | CRTC_ENABLE;
 941     if (M64_HAS(MAGIC_FIFO)) {
 942         /* Not VTB/GTB */
 943         /* FIXME: magic FIFO values */
 944         crtc->gen_cntl |= aty_ld_le32(CRTC_GEN_CNTL, info) & 0x000e0000;
 945     }
 946     crtc->dp_pix_width = dp_pix_width;
 947     crtc->dp_chain_mask = dp_chain_mask;
 948
 949     return 0;
 950 }
 951 #if 0
 952 static int aty_crtc_to_var(const struct crtc *crtc,
 953                            struct fb_var_screeninfo *var)
 954 {
 955     u32 xres, yres, bpp, left, right, upper, lower, hslen, vslen, sync;
 956     u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol;
 957     u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
 958     u32 pix_width;
 959
 960     /* input */
 961     h_total = crtc->h_tot_disp & 0x1ff;
 962     h_disp = (crtc->h_tot_disp>>16) & 0xff;
 963     h_sync_strt = (crtc->h_sync_strt_wid & 0xff) |
 964                   ((crtc->h_sync_strt_wid>>4) & 0x100);
 965     h_sync_dly = (crtc->h_sync_strt_wid>>8) & 0x7;
 966     h_sync_wid = (crtc->h_sync_strt_wid>>16) & 0x1f;
 967     h_sync_pol = (crtc->h_sync_strt_wid>>21) & 0x1;
 968     v_total = crtc->v_tot_disp & 0x7ff;
 969     v_disp = (crtc->v_tot_disp>>16) & 0x7ff;
 970     v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
 971     v_sync_wid = (crtc->v_sync_strt_wid>>16) & 0x1f;
 972     v_sync_pol = (crtc->v_sync_strt_wid>>21) & 0x1;
 973     c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
 974     pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
 975
 976     /* convert */
 977     xres = (h_disp+1)*8;
 978     yres = v_disp+1;
 979     left = (h_total-h_sync_strt-h_sync_wid)*8-h_sync_dly;
 980     right = (h_sync_strt-h_disp)*8+h_sync_dly;
 981     hslen = h_sync_wid*8;
 982     upper = v_total-v_sync_strt-v_sync_wid;
 983     lower = v_sync_strt-v_disp;
 984     vslen = v_sync_wid;
 985     sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
 986            (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
 987            (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
 988
 989     switch (pix_width) {
 990 #if 0
 991         case CRTC_PIX_WIDTH_4BPP:
 992             bpp = 4;
 993             var->red.offset = 0;
 994             var->red.length = 8;
 995             var->green.offset = 0;
 996             var->green.length = 8;
 997             var->blue.offset = 0;
 998             var->blue.length = 8;
 999             var->transp.offset = 0;
1000             var->transp.length = 0;
1001             break;
1002 #endif
1003         case CRTC_PIX_WIDTH_8BPP:
1004             bpp = 8;
1005             var->red.offset = 0;
1006             var->red.length = 8;
1007             var->green.offset = 0;
1008             var->green.length = 8;
1009             var->blue.offset = 0;
1010             var->blue.length = 8;
1011             var->transp.offset = 0;
1012             var->transp.length = 0;
1013             break;
1014 #if 0
1015         case CRTC_PIX_WIDTH_15BPP:      /* RGB 555 */
1016             bpp = 16;
1017             var->red.offset = 10;
1018             var->red.length = 5;
1019             var->green.offset = 5;
1020             var->green.length = 5;
1021             var->blue.offset = 0;
1022             var->blue.length = 5;
1023             var->transp.offset = 0;
1024             var->transp.length = 0;
1025             break;
1026 #endif
1027 #if 0
1028         case CRTC_PIX_WIDTH_16BPP:      /* RGB 565 */
1029             bpp = 16;
1030             var->red.offset = 11;
1031             var->red.length = 5;
1032             var->green.offset = 5;
1033             var->green.length = 6;
1034             var->blue.offset = 0;
1035             var->blue.length = 5;
1036             var->transp.offset = 0;
1037             var->transp.length = 0;
1038             break;
1039 #endif
1040 #if 0
1041         case CRTC_PIX_WIDTH_24BPP:      /* RGB 888 */
1042             bpp = 24;
1043             var->red.offset = 16;
1044             var->red.length = 8;
1045             var->green.offset = 8;
1046             var->green.length = 8;
1047             var->blue.offset = 0;
1048             var->blue.length = 8;
1049            var->transp.offset = 0;
1050             var->transp.length = 0;
1051             break;
1052         case CRTC_PIX_WIDTH_32BPP:      /* ARGB 8888 */
1053             bpp = 32;
1054             var->red.offset = 16;
1055             var->red.length = 8;
1056             var->green.offset = 8;
1057             var->green.length = 8;
1058             var->blue.offset = 0;
1059             var->blue.length = 8;
1060             var->transp.offset = 24;
1061             var->transp.length = 8;
1062             break;
1063 #endif
1064         default:
1065             FAIL("Invalid pixel width");
1066     }
1067
1068     /* output */
1069     var->xres = xres;
1070     var->yres = yres;
1071     var->xres_virtual = crtc->vxres;
1072     var->yres_virtual = crtc->vyres;
1073     var->bits_per_pixel = bpp;
1074     var->xoffset = crtc->xoffset;
1075     var->yoffset = crtc->yoffset;
1076     var->left_margin = left;
1077     var->right_margin = right;
1078     var->upper_margin = upper;
1079     var->lower_margin = lower;
1080     var->hsync_len = hslen;
1081     var->vsync_len = vslen;
1082     var->sync = sync;
1083     var->vmode = FB_VMODE_NONINTERLACED;
1084
1085     return 0;
1086 }
1087 #endif
1088
1089 #if 0
1090 static int encode_fix(struct fb_fix_screeninfo *fix,
1091                       const struct atyfb_par *par,
1092                       const struct fb_info_aty *info)
1093 {
1094     memset(fix, 0, sizeof(struct fb_fix_screeninfo));
1095
1096    // strcpy(fix->id, atyfb_name);
1097          memcpy(fix->id, "atyfb", 5);
1098     fix->smem_start = info->frame_buffer;
1099     fix->smem_len = (u32)info->total_vram;
1100
1101     /*
1102      *  Reg Block 0 (CT-compatible block) is at ati_regbase_phys
1103      *  Reg Block 1 (multimedia extensions) is at ati_regbase_phys-0x400
1104      */
1105     if (M64_HAS(GX)) {
1106         fix->mmio_start = info->ati_regbase;
1107         fix->mmio_len = 0x400;
1108         fix->accel = FB_ACCEL_ATI_MACH64GX;
1109     } else if (M64_HAS(CT)) {
1110         fix->mmio_start = info->ati_regbase;
1111         fix->mmio_len = 0x400;
1112         fix->accel = FB_ACCEL_ATI_MACH64CT;
1113     } else if (M64_HAS(VT)) {
1114         fix->mmio_start = info->ati_regbase-0x400;
1115         fix->mmio_len = 0x800;
1116         fix->accel = FB_ACCEL_ATI_MACH64VT;
1117     } else /* if (M64_HAS(GT)) */ {
1118         fix->mmio_start = info->ati_regbase-0x400;
1119         fix->mmio_len = 0x800;
1120         fix->accel = FB_ACCEL_ATI_MACH64GT;
1121     }
1122     fix->type = FB_TYPE_PACKED_PIXELS;
1123     fix->type_aux = 0;
1124     fix->line_length = par->crtc.vxres*par->crtc.bpp/8;
1125     fix->visual = par->crtc.bpp <= 8 ? FB_VISUAL_PSEUDOCOLOR
1126                                      : FB_VISUAL_DIRECTCOLOR;
1127     fix->ywrapstep = 0;
1128     fix->xpanstep = 8;
1129     fix->ypanstep = 1;
1130
1131     return 0;
1132 }
1133 #endif
1134    /*
1135      *  Set the User Defined Part of the Display
1136      */
1137 #if 0
1138 static int atyfb_set_var(struct fb_var_screeninfo *var, int con,
1139                          struct fb_info *fb)
1140 {
1141     struct fb_info_aty *info = (struct fb_info_aty *)fb;
1142     struct atyfb_par par;
1143 #if 0
1144     struct display *display;
1145     int oldxres, oldyres, oldvxres, oldvyres, oldbpp, oldaccel, accel;
1146 #endif
1147     int err;
1148     int activate = var->activate;
1149
1150 #if 0
1151     if (con >= 0)
1152         display = &fb_display[con];
1153     else
1154 #endif
1155 #if 0
1156         display = fb->disp;     /* used during initialization */
1157 #endif
1158
1159     if ((err = atyfb_decode_var(var, &par, info)))
1160         return err;
1161
1162     atyfb_encode_var(var, &par, (struct fb_info_aty *)info);
1163
1164 #if 0
1165     printk_info("atyfb_set_var: activate=%d\n", activate & FB_ACTIVATE_MASK);
1166 #endif
1167
1168     if ((activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) {
1169 #if 0
1170         oldxres = display->var.xres;
1171         oldyres = display->var.yres;
1172         oldvxres = display->var.xres_virtual;
1173         oldvyres = display->var.yres_virtual;
1174         oldbpp = display->var.bits_per_pixel;
1175         oldaccel = display->var.accel_flags;
1176         display->var = *var;
1177         accel = var->accel_flags & FB_ACCELF_TEXT;
1178         if (oldxres != var->xres || oldyres != var->yres ||
1179             oldvxres != var->xres_virtual || oldvyres != var->yres_virtual ||
1180             oldbpp != var->bits_per_pixel || oldaccel != var->accel_flags) {
1181             struct fb_fix_screeninfo fix;
1182
1183             encode_fix(&fix, &par, info);
1184             display->screen_base = (char *)info->frame_buffer;
1185             display->visual = fix.visual;
1186             display->type = fix.type;
1187             display->type_aux = fix.type_aux;
1188             display->ypanstep = fix.ypanstep;
1189             display->ywrapstep = fix.ywrapstep;
1190             display->line_length = fix.line_length;
1191             display->can_soft_blank = 1;
1192             display->inverse = 0;
1193 #if 0
1194            if (accel)
1195                 display->scrollmode = (info->bus_type == PCI) ? SCROLL_YNOMOVE : 0;
1196             else
1197 #endif
1198                 display->scrollmode = SCROLL_YREDRAW;
1199 #if 0
1200             if (info->fb_info.changevar)
1201                 (*info->fb_info.changevar)(con);
1202 #endif
1203         }
1204 #endif
1205 //        if (!info->fb_info.display_fg ||
1206 //            info->fb_info.display_fg->vc_num == con) {
1207             atyfb_set_par(&par, info);
1208 #if 0
1209             atyfb_set_dispsw(display, info, par.crtc.bpp, accel);
1210 #endif
1211 //        }
1212 #if 0
1213         if (oldbpp != var->bits_per_pixel) {
1214             if ((err = fb_alloc_cmap(&display->cmap, 0, 0)))
1215                 return err;
1216 #endif
1217             do_install_cmap(con, &info->fb_info);
1218 #if 0
1219         }
1220 #endif
1221     }
1222
1223     return 0;
1224 }
1225
1226 #endif
1227 /* ------------------------------------------------------------------------- */
1228
1229 static void atyfb_set_par(const struct atyfb_par *par,
1230                           struct fb_info_aty *info)
1231 {
1232     u32 i;
1233     int accelmode;
1234     u8 tmp;
1235
1236     accelmode = par->accel_flags;  /* hack */
1237
1238 #if 0
1239 //    We only use default_par
1240     info->current_par = *par;
1241 #endif
1242
1243     if (info->blitter_may_be_busy)
1244         wait_for_idle(info);
1245     tmp = aty_ld_8(CRTC_GEN_CNTL + 3, info);
1246     aty_set_crtc(info, &par->crtc);
1247     aty_st_8(CLOCK_CNTL + info->clk_wr_offset, 0, info);
1248                                         /* better call aty_StrobeClock ?? */
1249     aty_st_8(CLOCK_CNTL + info->clk_wr_offset, CLOCK_STROBE, info);
1250
1251     //info->dac_ops->set_dac(info, &par->pll, par->crtc.bpp, accelmode);
1252     //info->pll_ops->set_pll(info, &par->pll);
1253    aty_set_pll_ct(info, &par->pll);
1254
1255
1256     if (!M64_HAS(INTEGRATED)) {
1257         /* Don't forget MEM_CNTL */
1258         i = aty_ld_le32(MEM_CNTL, info) & 0xf0ffffff;
1259         switch (par->crtc.bpp) {
1260             case 8:
1261                 i |= 0x02000000;
1262                 break;
1263 #if 0
1264             case 16:
1265                 i |= 0x03000000;
1266                 break;
1267             case 32:
1268                 i |= 0x06000000;
1269                 break;
1270 #endif
1271         }
1272         aty_st_le32(MEM_CNTL, i, info);
1273     } else {
1274         i = aty_ld_le32(MEM_CNTL, info) & 0xf00fffff;
1275         if (!M64_HAS(MAGIC_POSTDIV))
1276                 i |= info->mem_refresh_rate << 20;
1277         switch (par->crtc.bpp) {
1278             case 8:
1279 //            case 24:
1280                 i |= 0x00000000;
1281                break;
1282 #if 0
1283             case 16:
1284                 i |= 0x04000000;
1285                 break;
1286             case 32:
1287                 i |= 0x08000000;
1288                 break;
1289 #endif
1290         }
1291         if (M64_HAS(CT_BUS)) {
1292             aty_st_le32(DAC_CNTL, 0x87010184, info);
1293             aty_st_le32(BUS_CNTL, 0x680000f9, info);
1294         } else if (M64_HAS(VT_BUS)) {
1295             aty_st_le32(DAC_CNTL, 0x87010184, info);
1296             aty_st_le32(BUS_CNTL, 0x680000f9, info);
1297         }  else if (M64_HAS(MOBIL_BUS)) {
1298             aty_st_le32(DAC_CNTL, 0x80010102, info);
1299             aty_st_le32(BUS_CNTL, 0x7b33a040, info);
1300         }  else {
1301             /* GT */
1302             aty_st_le32(DAC_CNTL, 0x86010102, info);
1303             aty_st_le32(BUS_CNTL, 0x7b23a040, info);
1304             aty_st_le32(EXT_MEM_CNTL,
1305                         aty_ld_le32(EXT_MEM_CNTL, info) | 0x5000001, info);
1306         }
1307
1308         aty_st_le32(MEM_CNTL, i, info);
1309     }
1310     aty_st_8(DAC_MASK, 0xff, info);
1311
1312     /* Initialize the graphics engine */
1313 #if 0
1314     if (par->accel_flags & FB_ACCELF_TEXT)
1315         aty_init_engine(par, info);
1316 #endif
1317
1318
1319 #if 0
1320     btext_update_display(info->frame_buffer_phys,
1321                          (((par->crtc.h_tot_disp>>16) & 0xff)+1)*8,
1322                          ((par->crtc.v_tot_disp>>16) & 0x7ff)+1,
1323                          par->crtc.bpp,
1324                          par->crtc.vxres*par->crtc.bpp/8);
1325 #endif
1326 }
1327 #if 0
1328 static u16 red2[] = {
1329     0x0000, 0xaaaa
1330 };
1331 static u16 green2[] = {
1332     0x0000, 0xaaaa
1333 };
1334 static u16 blue2[] = {
1335     0x0000, 0xaaaa
1336 };
1337
1338 static u16 red4[] = {
1339     0x0000, 0xaaaa, 0x5555, 0xffff
1340 };
1341 static u16 green4[] = {
1342     0x0000, 0xaaaa, 0x5555, 0xffff
1343 };
1344 static u16 blue4[] = {
1345     0x0000, 0xaaaa, 0x5555, 0xffff
1346 };
1347
1348 static u16 red8[] = {
1349     0x0000, 0x0000, 0x0000, 0x0000, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa
1350 };
1351 static u16 green8[] = {
1352     0x0000, 0x0000, 0xaaaa, 0xaaaa, 0x0000, 0x0000, 0x5555, 0xaaaa
1353 };
1354 static u16 blue8[] = {
1355     0x0000, 0xaaaa, 0x0000, 0xaaaa, 0x0000, 0xaaaa, 0x0000, 0xaaaa
1356 };
1357 #endif
1358 static u16 red16[] = {
1359     0x0000, 0x0000, 0x0000, 0x0000, 0xaaaa, 0xaaaa, 0xaaaa, 0xaaaa,
1360     0x5555, 0x5555, 0x5555, 0x5555, 0xffff, 0xffff, 0xffff, 0xffff
1361 };
1362 static u16 green16[] = {
1363     0x0000, 0x0000, 0xaaaa, 0xaaaa, 0x0000, 0x0000, 0x5555, 0xaaaa,
1364     0x5555, 0x5555, 0xffff, 0xffff, 0x5555, 0x5555, 0xffff, 0xffff
1365 };
1366 static u16 blue16[] = {
1367     0x0000, 0xaaaa, 0x0000, 0xaaaa, 0x0000, 0xaaaa, 0x0000, 0xaaaa,
1368     0x5555, 0xffff, 0x5555, 0xffff, 0x5555, 0xffff, 0x5555, 0xffff
1369 };
1370 #if 0
1371 static struct fb_cmap default_2_colors = {
1372     0, 2, red2, green2, blue2, NULL
1373 };
1374 static struct fb_cmap default_8_colors = {
1375     0, 8, red8, green8, blue8, NULL
1376 };
1377 static struct fb_cmap default_4_colors = {
1378     0, 4, red4, green4, blue4, NULL
1379 };
1380 #endif
1381 static struct fb_cmap default_16_colors = {
1382     0, 16, red16, green16, blue16, NULL
1383 };
1384
1385
1386
1387 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
1388                            u_int transp, struct fb_info *fb)
1389 {
1390     struct fb_info_aty *info = (struct fb_info_aty *)fb;
1391     int i, scale;
1392
1393     if (regno > 255)
1394         return 1;
1395     red >>= 8;
1396     green >>= 8;
1397     blue >>= 8;
1398 #if 0
1399 //We don't need to store it
1400     info->palette[regno].red = red;
1401     info->palette[regno].green = green;
1402     info->palette[regno].blue = blue;
1403 #endif
1404     i = aty_ld_8(DAC_CNTL, info) & 0xfc;
1405     if (M64_HAS(EXTRA_BRIGHT))
1406         i |= 0x2;       /*DAC_CNTL|0x2 turns off the extra brightness for gt*/
1407     aty_st_8(DAC_CNTL, i, info);
1408     aty_st_8(DAC_MASK, 0xff, info);
1409 #if 0
1410     scale = (M64_HAS(INTEGRATED) && info->current_par.crtc.bpp == 16) ? 3 : 0;
1411 #else
1412     scale = (M64_HAS(INTEGRATED) && info->default_par.crtc.bpp == 16) ? 3 : 0;
1413 #endif
1414     writeb(regno << scale, &info->aty_cmap_regs->windex);
1415     writeb(red, &info->aty_cmap_regs->lut);
1416     writeb(green, &info->aty_cmap_regs->lut);
1417     writeb(blue, &info->aty_cmap_regs->lut);
1418     return 0;
1419 }
1420
1421 int fb_set_cmap(struct fb_cmap *cmap, int kspc,
1422                 int (*setcolreg)(u_int, u_int, u_int, u_int, u_int,
1423                                  struct fb_info *),
1424                 struct fb_info *fb)
1425 {
1426     int i, start;
1427     u16 *red, *green, *blue, *transp;
1428     u_int hred, hgreen, hblue, htransp;
1429
1430     red = cmap->red;
1431     green = cmap->green;
1432     blue = cmap->blue;
1433     transp = cmap->transp;
1434     start = cmap->start;
1435
1436     if (start < 0)
1437         return -EINVAL;
1438     for (i = 0; i < cmap->len; i++) {
1439             hred = *red;
1440             hgreen = *green;
1441             hblue = *blue;
1442             htransp = transp ? *transp : 0;
1443         red++;
1444         green++;
1445         blue++;
1446         if (transp)
1447             transp++;
1448         if (setcolreg(start++, hred, hgreen, hblue, htransp, fb))
1449             return 0;
1450     }
1451     return 0;
1452 }
1453
1454 struct fb_cmap *fb_default_cmap(int len)
1455 {
1456 #if 0
1457     if (len <= 2)
1458         return &default_2_colors;
1459     if (len <= 4)
1460         return &default_4_colors;
1461     if (len <= 8)
1462         return &default_8_colors;
1463 #endif
1464     return &default_16_colors;
1465 }
1466
1467 static void do_install_cmap(int con, struct fb_info *fb)
1468 {
1469 #if 0
1470         struct fb_info_aty *info = (struct fb_info_aty *)fb;
1471         int size = info->current_par.crtc.bpp == 16 ? 32 : 256;
1472 #else
1473         int size = 256;
1474 #endif
1475         fb_set_cmap(fb_default_cmap(size), 1, atyfb_setcolreg, fb);
1476 }
1477
1478
1479 static struct device_operations ati_ragexl_graph_ops  = {
1480         .read_resources   = pci_dev_read_resources,
1481         .set_resources    = pci_dev_set_resources,
1482         .enable_resources = pci_dev_enable_resources,
1483         .init             = ati_ragexl_init,
1484         .scan_bus         = 0,
1485 };
1486
1487 static struct pci_driver ati_ragexl_graph_driver __pci_driver = {
1488         .ops    = &ati_ragexl_graph_ops,
1489         .vendor = PCI_VENDOR_ID_ATI,
1490         .device = PCI_DEVICE_ID_ATI_215XL,
1491 };
1492
1493