2 * This file is part of the coreboot project.
4 * It was originally based on the Linux kernel (drivers/pci/pci.c).
7 * Copyright (C) 2003-2004 Linux Networx
8 * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
9 * Copyright (C) 2003-2006 Ronald G. Minnich <rminnich@gmail.com>
10 * Copyright (C) 2004-2005 Li-Ta Lo <ollie@lanl.gov>
11 * Copyright (C) 2005-2006 Tyan
12 * (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
13 * Copyright (C) 2005-2007 Stefan Reinauer <stepan@openbios.org>
17 * PCI Bus Services, see include/linux/pci.h for further explanation.
19 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
20 * David Mosberger-Tang
22 * Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
25 #include <console/console.h>
31 #include <device/device.h>
32 #include <device/pci.h>
33 #include <device/pci_ids.h>
34 #include <part/hard_reset.h>
35 #include <part/fallback_boot.h>
37 #if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1
38 #include <device/hypertransport.h>
40 #if CONFIG_PCIX_PLUGIN_SUPPORT == 1
41 #include <device/pcix.h>
43 #if CONFIG_PCIEXP_PLUGIN_SUPPORT == 1
44 #include <device/pciexp.h>
46 #if CONFGI_AGP_PLUGIN_SUPPORT == 1
47 #include <device/agp.h>
49 #if CONFIG_CARDBUS_PLUGIN_SUPPORT == 1
50 #include <device/cardbus.h>
53 uint8_t pci_moving_config8(struct device *dev, unsigned reg)
55 uint8_t value, ones, zeroes;
56 value = pci_read_config8(dev, reg);
58 pci_write_config8(dev, reg, 0xff);
59 ones = pci_read_config8(dev, reg);
61 pci_write_config8(dev, reg, 0x00);
62 zeroes = pci_read_config8(dev, reg);
64 pci_write_config8(dev, reg, value);
69 uint16_t pci_moving_config16(struct device *dev, unsigned reg)
71 uint16_t value, ones, zeroes;
72 value = pci_read_config16(dev, reg);
74 pci_write_config16(dev, reg, 0xffff);
75 ones = pci_read_config16(dev, reg);
77 pci_write_config16(dev, reg, 0x0000);
78 zeroes = pci_read_config16(dev, reg);
80 pci_write_config16(dev, reg, value);
85 uint32_t pci_moving_config32(struct device *dev, unsigned reg)
87 uint32_t value, ones, zeroes;
88 value = pci_read_config32(dev, reg);
90 pci_write_config32(dev, reg, 0xffffffff);
91 ones = pci_read_config32(dev, reg);
93 pci_write_config32(dev, reg, 0x00000000);
94 zeroes = pci_read_config32(dev, reg);
96 pci_write_config32(dev, reg, value);
101 unsigned pci_find_next_capability(device_t dev, unsigned cap, unsigned last)
107 status = pci_read_config16(dev, PCI_STATUS);
108 if (!(status & PCI_STATUS_CAP_LIST)) {
111 switch(dev->hdr_type & 0x7f) {
112 case PCI_HEADER_TYPE_NORMAL:
113 case PCI_HEADER_TYPE_BRIDGE:
114 pos = PCI_CAPABILITY_LIST;
116 case PCI_HEADER_TYPE_CARDBUS:
117 pos = PCI_CB_CAPABILITY_LIST;
122 pos = pci_read_config8(dev, pos);
123 while(reps-- && (pos >= 0x40)) { /* loop through the linked list */
126 this_cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID);
127 printk_spew("Capability: 0x%02x @ 0x%02x\n", cap, pos);
128 if (this_cap == 0xff) {
131 if (!last && (this_cap == cap)) {
137 pos = pci_read_config8(dev, pos + PCI_CAP_LIST_NEXT);
142 unsigned pci_find_capability(device_t dev, unsigned cap)
144 return pci_find_next_capability(dev, cap, 0);
148 /** Given a device and register, read the size of the BAR for that register.
149 * @param dev Pointer to the device structure
150 * @param resource Pointer to the resource structure
151 * @param index Address of the pci configuration register
153 struct resource *pci_get_resource(struct device *dev, unsigned long index)
155 struct resource *resource;
156 unsigned long value, attr;
157 resource_t moving, limit;
159 /* Initialize the resources to nothing */
160 resource = new_resource(dev, index);
162 /* Get the initial value */
163 value = pci_read_config32(dev, index);
165 /* See which bits move */
166 moving = pci_moving_config32(dev, index);
168 /* Initialize attr to the bits that do not move */
169 attr = value & ~moving;
171 /* If it is a 64bit resource look at the high half as well */
172 if (((attr & PCI_BASE_ADDRESS_SPACE_IO) == 0) &&
173 ((attr & PCI_BASE_ADDRESS_MEM_LIMIT_MASK) == PCI_BASE_ADDRESS_MEM_LIMIT_64))
175 /* Find the high bits that move */
176 moving |= ((resource_t)pci_moving_config32(dev, index + 4)) << 32;
178 /* Find the resource constraints.
180 * Start by finding the bits that move. From there:
181 * - Size is the least significant bit of the bits that move.
182 * - Limit is all of the bits that move plus all of the lower bits.
183 * See PCI Spec 6.2.5.1 ...
188 resource->align = resource->gran = 0;
189 while(!(moving & resource->size)) {
190 resource->size <<= 1;
191 resource->align += 1;
194 resource->limit = limit = moving | (resource->size - 1);
197 * some broken hardware has read-only registers that do not
198 * really size correctly.
199 * Example: the acer m7229 has BARs 1-4 normally read-only.
200 * so BAR1 at offset 0x10 reads 0x1f1. If you size that register
201 * by writing 0xffffffff to it, it will read back as 0x1f1 -- a
202 * violation of the spec.
203 * We catch this case and ignore it by observing which bits move,
204 * This also catches the common case unimplemented registers
205 * that always read back as 0.
210 "%s register %02x(%08x), read-only ignoring it\n",
211 dev_path(dev), index, value);
215 else if (attr & PCI_BASE_ADDRESS_SPACE_IO) {
216 /* An I/O mapped base address */
217 attr &= PCI_BASE_ADDRESS_IO_ATTR_MASK;
218 resource->flags |= IORESOURCE_IO;
219 /* I don't want to deal with 32bit I/O resources */
220 resource->limit = 0xffff;
223 /* A Memory mapped base address */
224 attr &= PCI_BASE_ADDRESS_MEM_ATTR_MASK;
225 resource->flags |= IORESOURCE_MEM;
226 if (attr & PCI_BASE_ADDRESS_MEM_PREFETCH) {
227 resource->flags |= IORESOURCE_PREFETCH;
229 attr &= PCI_BASE_ADDRESS_MEM_LIMIT_MASK;
230 if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_32) {
232 resource->limit = 0xffffffffUL;
234 else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_1M) {
236 resource->limit = 0x000fffffUL;
238 else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_64) {
240 resource->limit = 0xffffffffffffffffULL;
241 resource->flags |= IORESOURCE_PCI64;
248 /* Don't let the limit exceed which bits can move */
249 if (resource->limit > limit) {
250 resource->limit = limit;
253 if (resource->flags) {
254 printk_debug("%s %02x ->",
255 dev_path(dev), resource->index);
256 printk_debug(" value: 0x%08Lx zeroes: 0x%08Lx ones: 0x%08Lx attr: %08lx\n",
257 value, zeroes, ones, attr);
259 "%s %02x -> size: 0x%08Lx max: 0x%08Lx %s\n ",
262 resource->size, resource->limit,
263 resource_type(resource));
270 static void pci_get_rom_resource(struct device *dev, unsigned long index)
272 struct resource *resource;
274 resource_t moving, limit;
276 if ((dev->on_mainboard) && (dev->rom_address == 0)) {
277 //skip it if rom_address is not set in MB Config.lb
281 /* Initialize the resources to nothing */
282 resource = new_resource(dev, index);
284 /* Get the initial value */
285 value = pci_read_config32(dev, index);
287 /* See which bits move */
288 moving = pci_moving_config32(dev, index);
289 /* clear the Enable bit */
290 moving = moving & ~PCI_ROM_ADDRESS_ENABLE;
292 /* Find the resource constraints.
294 * Start by finding the bits that move. From there:
295 * - Size is the least significant bit of the bits that move.
296 * - Limit is all of the bits that move plus all of the lower bits.
297 * See PCI Spec 6.2.5.1 ...
303 resource->align = resource->gran = 0;
304 while (!(moving & resource->size)) {
305 resource->size <<= 1;
306 resource->align += 1;
309 resource->limit = limit = moving | (resource->size - 1);
314 printk_debug("%s register %02x(%08x), read-only ignoring it\n",
315 dev_path(dev), index, value);
319 resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY;
322 /* for on board device with embedded ROM image, the ROM image is at
323 * fixed address specified in the Config.lb, the dev->rom_address is
324 * inited by driver_pci_onboard_ops::enable_dev() */
325 if ((dev->on_mainboard) && (dev->rom_address != 0)) {
326 resource->base = dev->rom_address;
327 resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY |
328 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
331 compact_resources(dev);
334 /** Read the base address registers for a given device.
335 * @param dev Pointer to the dev structure
336 * @param howmany How many registers to read (6 for device, 2 for bridge)
338 static void pci_read_bases(struct device *dev, unsigned int howmany)
342 for(index = PCI_BASE_ADDRESS_0; (index < PCI_BASE_ADDRESS_0 + (howmany << 2)); ) {
343 struct resource *resource;
344 resource = pci_get_resource(dev, index);
345 index += (resource->flags & IORESOURCE_PCI64)?8:4;
348 compact_resources(dev);
351 static void pci_set_resource(struct device *dev, struct resource *resource);
353 static void pci_record_bridge_resource(
354 struct device *dev, resource_t moving,
355 unsigned index, unsigned long mask, unsigned long type)
357 /* Initiliaze the constraints on the current bus */
358 struct resource *resource;
363 resource = new_resource(dev, index);
367 while((moving & step) == 0) {
371 resource->gran = gran;
372 resource->align = gran;
373 resource->limit = moving | (step - 1);
374 resource->flags = type | IORESOURCE_PCI_BRIDGE;
375 compute_allocate_resource(&dev->link[0], resource, mask, type);
376 /* If there is nothing behind the resource,
377 * clear it and forget it.
379 if (resource->size == 0) {
380 resource->base = moving;
381 resource->flags |= IORESOURCE_ASSIGNED;
382 resource->flags &= ~IORESOURCE_STORED;
383 pci_set_resource(dev, resource);
390 static void pci_bridge_read_bases(struct device *dev)
392 resource_t moving_base, moving_limit, moving;
394 /* See if the bridge I/O resources are implemented */
395 moving_base = ((uint32_t)pci_moving_config8(dev, PCI_IO_BASE)) << 8;
396 moving_base |= ((uint32_t)pci_moving_config16(dev, PCI_IO_BASE_UPPER16)) << 16;
398 moving_limit = ((uint32_t)pci_moving_config8(dev, PCI_IO_LIMIT)) << 8;
399 moving_limit |= ((uint32_t)pci_moving_config16(dev, PCI_IO_LIMIT_UPPER16)) << 16;
401 moving = moving_base & moving_limit;
403 /* Initialize the io space constraints on the current bus */
404 pci_record_bridge_resource(
405 dev, moving, PCI_IO_BASE,
406 IORESOURCE_IO, IORESOURCE_IO);
409 /* See if the bridge prefmem resources are implemented */
410 moving_base = ((resource_t)pci_moving_config16(dev, PCI_PREF_MEMORY_BASE)) << 16;
411 moving_base |= ((resource_t)pci_moving_config32(dev, PCI_PREF_BASE_UPPER32)) << 32;
413 moving_limit = ((resource_t)pci_moving_config16(dev, PCI_PREF_MEMORY_LIMIT)) << 16;
414 moving_limit |= ((resource_t)pci_moving_config32(dev, PCI_PREF_LIMIT_UPPER32)) << 32;
416 moving = moving_base & moving_limit;
417 /* Initiliaze the prefetchable memory constraints on the current bus */
418 pci_record_bridge_resource(
419 dev, moving, PCI_PREF_MEMORY_BASE,
420 IORESOURCE_MEM | IORESOURCE_PREFETCH,
421 IORESOURCE_MEM | IORESOURCE_PREFETCH);
424 /* See if the bridge mem resources are implemented */
425 moving_base = ((uint32_t)pci_moving_config16(dev, PCI_MEMORY_BASE)) << 16;
426 moving_limit = ((uint32_t)pci_moving_config16(dev, PCI_MEMORY_LIMIT)) << 16;
428 moving = moving_base & moving_limit;
430 /* Initialize the memory resources on the current bus */
431 pci_record_bridge_resource(
432 dev, moving, PCI_MEMORY_BASE,
433 IORESOURCE_MEM | IORESOURCE_PREFETCH,
436 compact_resources(dev);
439 void pci_dev_read_resources(struct device *dev)
441 pci_read_bases(dev, 6);
442 pci_get_rom_resource(dev, PCI_ROM_ADDRESS);
445 void pci_bus_read_resources(struct device *dev)
447 pci_bridge_read_bases(dev);
448 pci_read_bases(dev, 2);
449 pci_get_rom_resource(dev, PCI_ROM_ADDRESS1);
452 static void pci_set_resource(struct device *dev, struct resource *resource)
454 resource_t base, end;
456 /* Make certain the resource has actually been set */
457 if (!(resource->flags & IORESOURCE_ASSIGNED)) {
458 printk_err("ERROR: %s %02x %s size: 0x%010Lx not assigned\n",
459 dev_path(dev), resource->index,
460 resource_type(resource),
465 /* If I have already stored this resource don't worry about it */
466 if (resource->flags & IORESOURCE_STORED) {
470 /* If the resources is substractive don't worry about it */
471 if (resource->flags & IORESOURCE_SUBTRACTIVE) {
475 /* Only handle PCI memory and IO resources for now */
476 if (!(resource->flags & (IORESOURCE_MEM |IORESOURCE_IO)))
479 /* Enable the resources in the command register */
480 if (resource->size) {
481 if (resource->flags & IORESOURCE_MEM) {
482 dev->command |= PCI_COMMAND_MEMORY;
484 if (resource->flags & IORESOURCE_IO) {
485 dev->command |= PCI_COMMAND_IO;
487 if (resource->flags & IORESOURCE_PCI_BRIDGE) {
488 dev->command |= PCI_COMMAND_MASTER;
491 /* Get the base address */
492 base = resource->base;
495 end = resource_end(resource);
497 /* Now store the resource */
498 resource->flags |= IORESOURCE_STORED;
499 if (!(resource->flags & IORESOURCE_PCI_BRIDGE)) {
500 unsigned long base_lo, base_hi;
502 * some chipsets allow us to set/clear the IO bit.
503 * (e.g. VIA 82c686a.) So set it to be safe)
505 base_lo = base & 0xffffffff;
506 base_hi = (base >> 32) & 0xffffffff;
507 if (resource->flags & IORESOURCE_IO) {
508 base_lo |= PCI_BASE_ADDRESS_SPACE_IO;
510 pci_write_config32(dev, resource->index, base_lo);
511 if (resource->flags & IORESOURCE_PCI64) {
512 pci_write_config32(dev, resource->index + 4, base_hi);
515 else if (resource->index == PCI_IO_BASE) {
516 /* set the IO ranges */
517 compute_allocate_resource(&dev->link[0], resource,
518 IORESOURCE_IO, IORESOURCE_IO);
519 pci_write_config8(dev, PCI_IO_BASE, base >> 8);
520 pci_write_config16(dev, PCI_IO_BASE_UPPER16, base >> 16);
521 pci_write_config8(dev, PCI_IO_LIMIT, end >> 8);
522 pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, end >> 16);
524 else if (resource->index == PCI_MEMORY_BASE) {
525 /* set the memory range */
526 compute_allocate_resource(&dev->link[0], resource,
527 IORESOURCE_MEM | IORESOURCE_PREFETCH,
529 pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);
530 pci_write_config16(dev, PCI_MEMORY_LIMIT, end >> 16);
532 else if (resource->index == PCI_PREF_MEMORY_BASE) {
533 /* set the prefetchable memory range */
534 compute_allocate_resource(&dev->link[0], resource,
535 IORESOURCE_MEM | IORESOURCE_PREFETCH,
536 IORESOURCE_MEM | IORESOURCE_PREFETCH);
537 pci_write_config16(dev, PCI_PREF_MEMORY_BASE, base >> 16);
538 pci_write_config32(dev, PCI_PREF_BASE_UPPER32, base >> 32);
539 pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, end >> 16);
540 pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, end >> 32);
543 /* Don't let me think I stored the resource */
544 resource->flags &= ~IORESOURCE_STORED;
545 printk_err("ERROR: invalid resource->index %x\n",
548 report_resource_stored(dev, resource, "");
552 void pci_dev_set_resources(struct device *dev)
554 struct resource *resource, *last;
558 last = &dev->resource[dev->resources];
560 for(resource = &dev->resource[0]; resource < last; resource++) {
561 pci_set_resource(dev, resource);
563 for(link = 0; link < dev->links; link++) {
565 bus = &dev->link[link];
567 assign_resources(bus);
571 /* set a default latency timer */
572 pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
574 /* set a default secondary latency timer */
575 if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
576 pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
579 /* zero the irq settings */
580 line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
582 pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
584 /* set the cache line size, so far 64 bytes is good for everyone */
585 pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
588 void pci_dev_enable_resources(struct device *dev)
590 const struct pci_operations *ops;
593 /* Set the subsystem vendor and device id for mainboard devices */
595 if (dev->on_mainboard && ops && ops->set_subsystem) {
596 printk_debug("%s subsystem <- %02x/%02x\n",
598 MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
599 MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
600 ops->set_subsystem(dev,
601 MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
602 MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
604 command = pci_read_config16(dev, PCI_COMMAND);
605 command |= dev->command;
606 printk_debug("%s cmd <- %02x\n", dev_path(dev), command);
607 pci_write_config16(dev, PCI_COMMAND, command);
610 void pci_bus_enable_resources(struct device *dev)
613 /* enable IO in command register if there is VGA card
614 * connected with (even it does not claim IO resource) */
615 if (dev->link[0].bridge_ctrl & PCI_BRIDGE_CTL_VGA)
616 dev->command |= PCI_COMMAND_IO;
617 ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
618 ctrl |= dev->link[0].bridge_ctrl;
619 ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error check */
620 printk_debug("%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
621 pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
623 pci_dev_enable_resources(dev);
625 enable_childrens_resources(dev);
628 void pci_bus_reset(struct bus *bus)
631 ctl = pci_read_config16(bus->dev, PCI_BRIDGE_CONTROL);
632 ctl |= PCI_BRIDGE_CTL_BUS_RESET;
633 pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, ctl);
635 ctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
636 pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, ctl);
640 void pci_dev_set_subsystem(device_t dev, unsigned vendor, unsigned device)
642 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
643 ((device & 0xffff) << 16) | (vendor & 0xffff));
646 /** default handler: only runs the relevant pci bios. */
647 void pci_dev_init(struct device *dev)
649 #if CONFIG_PCI_ROM_RUN == 1 || CONFIG_VGA_ROM_RUN == 1
650 void run_bios(struct device * dev, unsigned long addr);
651 struct rom_header *rom, *ram;
653 #if CONFIG_PCI_ROM_RUN != 1
654 /* We want to execute VGA option ROMs when CONFIG_VGA_ROM_RUN
655 * is set but CONFIG_PCI_ROM_RUN is not. In this case we skip
656 * all other option ROM types.
658 if ((dev->class>>8)!=PCI_CLASS_DISPLAY_VGA)
662 rom = pci_rom_probe(dev);
666 ram = pci_rom_load(dev, rom);
670 run_bios(dev, (unsigned long)ram);
672 #if CONFIG_CONSOLE_VGA == 1
673 /* vga_inited is a trigger of the VGA console code. */
674 if ((dev->class>>8) == PCI_CLASS_DISPLAY_VGA) {
675 extern int vga_inited;
678 #endif /* CONFIG_CONSOLE_VGA */
679 #endif /* CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN */
682 /** Default device operation for PCI devices */
683 static struct pci_operations pci_dev_ops_pci = {
684 .set_subsystem = pci_dev_set_subsystem,
687 struct device_operations default_pci_ops_dev = {
688 .read_resources = pci_dev_read_resources,
689 .set_resources = pci_dev_set_resources,
690 .enable_resources = pci_dev_enable_resources,
691 .init = pci_dev_init,
694 .ops_pci = &pci_dev_ops_pci,
697 /** Default device operations for PCI bridges */
698 static struct pci_operations pci_bus_ops_pci = {
702 struct device_operations default_pci_ops_bus = {
703 .read_resources = pci_bus_read_resources,
704 .set_resources = pci_dev_set_resources,
705 .enable_resources = pci_bus_enable_resources,
707 .scan_bus = pci_scan_bridge,
709 .reset_bus = pci_bus_reset,
710 .ops_pci = &pci_bus_ops_pci,
714 * @brief Detect the type of downstream bridge
716 * This function is a heuristic to detect which type
717 * of bus is downstream of a pci to pci bridge. This
718 * functions by looking for various capability blocks
719 * to figure out the type of downstream bridge. PCI-X
720 * PCI-E, and Hypertransport all seem to have appropriate
723 * When only a PCI-Express capability is found the type
724 * is examined to see which type of bridge we have.
728 * @return appropriate bridge operations
730 static struct device_operations *get_pci_bridge_ops(device_t dev)
734 #if CONFIG_PCIX_PLUGIN_SUPPORT == 1
735 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
737 printk_debug("%s subbordinate bus PCI-X\n", dev_path(dev));
738 return &default_pcix_ops_bus;
741 #if CONFIG_AGP_PLUGIN_SUPPORT == 1
742 /* How do I detect an PCI to AGP bridge? */
744 #if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1
746 while((pos = pci_find_next_capability(dev, PCI_CAP_ID_HT, pos))) {
748 flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
749 if ((flags >> 13) == 1) {
750 /* Host or Secondary Interface */
751 printk_debug("%s subbordinate bus Hypertransport\n",
753 return &default_ht_ops_bus;
757 #if CONFIG_PCIEXP_PLUGIN_SUPPORT == 1
758 pos = pci_find_capability(dev, PCI_CAP_ID_PCIE);
761 flags = pci_read_config16(dev, pos + PCI_EXP_FLAGS);
762 switch((flags & PCI_EXP_FLAGS_TYPE) >> 4) {
763 case PCI_EXP_TYPE_ROOT_PORT:
764 case PCI_EXP_TYPE_UPSTREAM:
765 case PCI_EXP_TYPE_DOWNSTREAM:
766 printk_debug("%s subbordinate bus PCI Express\n",
768 return &default_pciexp_ops_bus;
769 case PCI_EXP_TYPE_PCI_BRIDGE:
770 printk_debug("%s subbordinate PCI\n",
772 return &default_pci_ops_bus;
778 return &default_pci_ops_bus;
782 * @brief Set up PCI device operation
789 static void set_pci_ops(struct device *dev)
791 struct pci_driver *driver;
796 /* Look through the list of setup drivers and find one for
799 for(driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) {
800 if ((driver->vendor == dev->vendor) &&
801 (driver->device == dev->device))
803 dev->ops = driver->ops;
804 printk_spew("%s [%04x/%04x] %sops\n",
806 driver->vendor, driver->device,
807 (driver->ops->scan_bus?"bus ":""));
812 /* If I don't have a specific driver use the default operations */
813 switch(dev->hdr_type & 0x7f) { /* header type */
814 case PCI_HEADER_TYPE_NORMAL: /* standard header */
815 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
817 dev->ops = &default_pci_ops_dev;
819 case PCI_HEADER_TYPE_BRIDGE:
820 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
822 dev->ops = get_pci_bridge_ops(dev);
824 #if CONFIG_CARDBUS_PLUGIN_SUPPORT == 1
825 case PCI_HEADER_TYPE_CARDBUS:
826 dev->ops = &default_cardbus_ops_bus;
832 printk_err("%s [%04x/%04x/%06x] has unknown header "
833 "type %02x, ignoring.\n",
835 dev->vendor, dev->device,
836 dev->class >> 8, dev->hdr_type);
845 * @brief See if we have already allocated a device structure for a given devfn.
847 * Given a linked list of PCI device structures and a devfn number, find the
848 * device structure correspond to the devfn, if present. This function also
849 * removes the device structure from the linked list.
851 * @param list the device structure list
852 * @param devfn a device/function number
854 * @return pointer to the device structure found or null of we have not
855 * allocated a device for this devfn yet.
857 static struct device *pci_scan_get_dev(struct device **list, unsigned int devfn)
861 for(; *list; list = &(*list)->sibling) {
862 if ((*list)->path.type != DEVICE_PATH_PCI) {
863 printk_err("child %s not a pci device\n",
867 if ((*list)->path.u.pci.devfn == devfn) {
868 /* Unlink from the list */
870 *list = (*list)->sibling;
875 /* Just like alloc_dev add the device to the list of device on the bus.
876 * When the list of devices was formed we removed all of the parents
877 * children, and now we are interleaving static and dynamic devices in
882 /* Find the last child of our parent */
883 for(child = dev->bus->children; child && child->sibling; ) {
884 child = child->sibling;
886 /* Place the device on the list of children of it's parent. */
888 child->sibling = dev;
890 dev->bus->children = dev;
898 * @brief Scan a PCI bus.
900 * Determine the existence of a given PCI device.
902 * @param bus pointer to the bus structure
903 * @param devfn to look at
905 * @return The device structure for hte device (if found)
906 * or the NULL if no device is found.
908 device_t pci_probe_dev(device_t dev, struct bus *bus, unsigned devfn)
913 /* Detect if a device is present */
917 dummy.path.type = DEVICE_PATH_PCI;
918 dummy.path.u.pci.devfn = devfn;
919 id = pci_read_config32(&dummy, PCI_VENDOR_ID);
920 /* Have we found somthing?
921 * Some broken boards return 0 if a slot is empty.
923 if ( (id == 0xffffffff) || (id == 0x00000000) ||
924 (id == 0x0000ffff) || (id == 0xffff0000))
926 printk_spew("%s, bad id 0x%x\n", dev_path(&dummy), id);
929 dev = alloc_dev(bus, &dummy.path);
932 /* Enable/disable the device. Once we have
933 * found the device specific operations this
934 * operations we will disable the device with
937 * This is geared toward devices that have subfunctions
938 * that do not show up by default.
940 * If a device is a stuff option on the motherboard
941 * it may be absent and enable_dev must cope.
944 /* Run the magice enable sequence for the device */
945 if (dev->chip_ops && dev->chip_ops->enable_dev) {
946 dev->chip_ops->enable_dev(dev);
948 /* Now read the vendor and device id */
949 id = pci_read_config32(dev, PCI_VENDOR_ID);
952 /* If the device does not have a pci id disable it.
953 * Possibly this is because we have already disabled
954 * the device. But this also handles optional devices
955 * that may not always show up.
957 /* If the chain is fully enumerated quit */
958 if ( (id == 0xffffffff) || (id == 0x00000000) ||
959 (id == 0x0000ffff) || (id == 0xffff0000))
962 printk_info("Disabling static device: %s\n",
969 /* Read the rest of the pci configuration information */
970 hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
971 class = pci_read_config32(dev, PCI_CLASS_REVISION);
973 /* Store the interesting information in the device structure */
974 dev->vendor = id & 0xffff;
975 dev->device = (id >> 16) & 0xffff;
976 dev->hdr_type = hdr_type;
977 /* class code, the upper 3 bytes of PCI_CLASS_REVISION */
978 dev->class = class >> 8;
981 /* Architectural/System devices always need to
984 if ((dev->class >> 16) == PCI_BASE_CLASS_SYSTEM) {
985 dev->command |= PCI_COMMAND_MASTER;
987 /* Look at the vendor and device id, or at least the
988 * header type and class and figure out which set of
989 * configuration methods to use. Unless we already
994 /* Now run the magic enable/disable sequence for the device */
995 if (dev->ops && dev->ops->enable) {
996 dev->ops->enable(dev);
1000 /* Display the device and error if we don't have some pci operations
1003 printk_debug("%s [%04x/%04x] %s%s\n",
1005 dev->vendor, dev->device,
1006 dev->enabled?"enabled": "disabled",
1007 dev->ops?"" : " No operations"
1014 * @brief Scan a PCI bus.
1016 * Determine the existence of devices and bridges on a PCI bus. If there are
1017 * bridges on the bus, recursively scan the buses behind the bridges.
1019 * This function is the default scan_bus() method for the root device
1022 * @param bus pointer to the bus structure
1023 * @param min_devfn minimum devfn to look at in the scan usually 0x00
1024 * @param max_devfn maximum devfn to look at in the scan usually 0xff
1025 * @param max current bus number
1027 * @return The maximum bus number found, after scanning all subordinate busses
1029 unsigned int pci_scan_bus(struct bus *bus,
1030 unsigned min_devfn, unsigned max_devfn,
1034 device_t old_devices;
1037 #if PCI_BUS_SEGN_BITS
1038 printk_debug("PCI: pci_scan_bus for bus %04x:%02x\n", bus->secondary >> 8, bus->secondary & 0xff);
1040 printk_debug("PCI: pci_scan_bus for bus %02x\n", bus->secondary);
1043 old_devices = bus->children;
1047 /* probe all devices/functions on this bus with some optimization for
1048 * non-existence and single funcion devices
1050 for (devfn = min_devfn; devfn <= max_devfn; devfn++) {
1053 /* First thing setup the device structure */
1054 dev = pci_scan_get_dev(&old_devices, devfn);
1056 /* See if a device is present and setup the device
1059 dev = pci_probe_dev(dev, bus, devfn);
1061 /* if this is not a multi function device,
1062 * or the device is not present don't waste
1063 * time probing another function.
1064 * Skip to next device.
1066 if ((PCI_FUNC(devfn) == 0x00) &&
1067 (!dev || (dev->enabled && ((dev->hdr_type & 0x80) != 0x80))))
1074 /* Die if any left over static devices are are found.
1075 * There's probably a problem in the Config.lb.
1079 for(left = old_devices; left; left = left->sibling) {
1080 printk_err("%s\n", dev_path(left));
1082 printk_warning("PCI: Left over static devices. Check your mainboard Config.lb\n");
1085 /* For all children that implement scan_bus (i.e. bridges)
1086 * scan the bus behind that child.
1088 for(child = bus->children; child; child = child->sibling) {
1089 max = scan_bus(child, max);
1093 * We've scanned the bus and so we know all about what's on
1094 * the other side of any bridges that may be on this bus plus
1097 * Return how far we've got finding sub-buses.
1099 printk_debug("PCI: pci_scan_bus returning with max=%03x\n", max);
1106 * @brief Scan a PCI bridge and the buses behind the bridge.
1108 * Determine the existence of buses behind the bridge. Set up the bridge
1109 * according to the result of the scan.
1111 * This function is the default scan_bus() method for PCI bridge devices.
1113 * @param dev pointer to the bridge device
1114 * @param max the highest bus number assgined up to now
1116 * @return The maximum bus number found, after scanning all subordinate busses
1118 unsigned int do_pci_scan_bridge(struct device *dev, unsigned int max,
1119 unsigned int (*do_scan_bus)(struct bus *bus,
1120 unsigned min_devfn, unsigned max_devfn, unsigned int max))
1126 printk_spew("%s for %s\n", __func__, dev_path(dev));
1128 bus = &dev->link[0];
1132 /* Set up the primary, secondary and subordinate bus numbers. We have
1133 * no idea how many buses are behind this bridge yet, so we set the
1134 * subordinate bus number to 0xff for the moment.
1136 bus->secondary = ++max;
1137 bus->subordinate = 0xff;
1139 /* Clear all status bits and turn off memory, I/O and master enables. */
1140 cr = pci_read_config16(dev, PCI_COMMAND);
1141 pci_write_config16(dev, PCI_COMMAND, 0x0000);
1142 pci_write_config16(dev, PCI_STATUS, 0xffff);
1145 * Read the existing primary/secondary/subordinate bus
1146 * number configuration.
1148 buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
1150 /* Configure the bus numbers for this bridge: the configuration
1151 * transactions will not be propagated by the bridge if it is not
1152 * correctly configured.
1154 buses &= 0xff000000;
1155 buses |= (((unsigned int) (dev->bus->secondary) << 0) |
1156 ((unsigned int) (bus->secondary) << 8) |
1157 ((unsigned int) (bus->subordinate) << 16));
1158 pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
1160 /* Now we can scan all subordinate buses
1161 * i.e. the bus behind the bridge.
1163 max = do_scan_bus(bus, 0x00, 0xff, max);
1165 /* We know the number of buses behind this bridge. Set the subordinate
1166 * bus number to its real value.
1168 bus->subordinate = max;
1169 buses = (buses & 0xff00ffff) |
1170 ((unsigned int) (bus->subordinate) << 16);
1171 pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
1172 pci_write_config16(dev, PCI_COMMAND, cr);
1174 printk_spew("%s returns max %d\n", __func__, max);
1179 * @brief Scan a PCI bridge and the buses behind the bridge.
1181 * Determine the existence of buses behind the bridge. Set up the bridge
1182 * according to the result of the scan.
1184 * This function is the default scan_bus() method for PCI bridge devices.
1186 * @param dev pointer to the bridge device
1187 * @param max the highest bus number assgined up to now
1189 * @return The maximum bus number found, after scanning all subordinate busses
1191 unsigned int pci_scan_bridge(struct device *dev, unsigned int max)
1193 return do_pci_scan_bridge(dev, max, pci_scan_bus);
1197 Tell the EISA int controller this int must be level triggered
1198 THIS IS A KLUDGE -- sorry, this needs to get cleaned up.
1200 void pci_level_irq(unsigned char intNum)
1202 unsigned short intBits = inb(0x4d0) | (((unsigned) inb(0x4d1)) << 8);
1204 printk_spew("%s: current ints are 0x%x\n", __func__, intBits);
1205 intBits |= (1 << intNum);
1207 printk_spew("%s: try to set ints 0x%x\n", __func__, intBits);
1210 outb((unsigned char) intBits, 0x4d0);
1211 outb((unsigned char) (intBits >> 8), 0x4d1);
1213 /* this seems like an error but is not ... */
1215 if (inb(0x4d0) != (intBits & 0xff)) {
1216 printk_err("%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
1217 __func__, intBits &0xff, inb(0x4d0));
1219 if (inb(0x4d1) != ((intBits >> 8) & 0xff)) {
1220 printk_err("%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
1221 __func__, (intBits>>8) &0xff, inb(0x4d1));
1227 This function assigns IRQs for all functions contained within
1228 the indicated device address. If the device does not exist or does
1229 not require interrupts then this function has no effect.
1231 This function should be called for each PCI slot in your system.
1233 pIntAtoD is an array of IRQ #s that are assigned to PINTA through PINTD of
1235 The particular irq #s that are passed in depend on the routing inside
1236 your southbridge and on your motherboard.
1240 void pci_assign_irqs(unsigned bus, unsigned slot,
1241 const unsigned char pIntAtoD[4])
1247 unsigned char readback;
1249 /* Each slot may contain up to eight functions */
1250 for (functNum = 0; functNum < 8; functNum++) {
1251 pdev = dev_find_slot(bus, (slot << 3) + functNum);
1254 line = pci_read_config8(pdev, PCI_INTERRUPT_PIN);
1256 // PCI spec says all other values are reserved
1257 if ((line >= 1) && (line <= 4)) {
1258 irq = pIntAtoD[line - 1];
1260 printk_debug("Assigning IRQ %d to %d:%x.%d\n", \
1261 irq, bus, slot, functNum);
1263 pci_write_config8(pdev, PCI_INTERRUPT_LINE,\
1264 pIntAtoD[line - 1]);
1266 readback = pci_read_config8(pdev, PCI_INTERRUPT_LINE);
1267 printk_debug(" Readback = %d\n", readback);
1269 // Change to level triggered
1270 pci_level_irq(pIntAtoD[line - 1]);