2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
9 * Copyright 2003 -- Eric Biederman <ebiederman@lnxi.com>
12 #include <console/console.h>
18 #include <device/device.h>
19 #include <device/pci.h>
20 #include <device/pci_ids.h>
21 #include <part/hard_reset.h>
22 #include <part/fallback_boot.h>
25 static uint8_t pci_moving_config8(struct device *dev, unsigned reg)
27 uint8_t value, ones, zeroes;
28 value = pci_read_config8(dev, reg);
30 pci_write_config8(dev, reg, 0xff);
31 ones = pci_read_config8(dev, reg);
33 pci_write_config8(dev, reg, 0x00);
34 zeroes = pci_read_config8(dev, reg);
36 pci_write_config8(dev, reg, value);
41 static uint16_t pci_moving_config16(struct device *dev, unsigned reg)
43 uint16_t value, ones, zeroes;
44 value = pci_read_config16(dev, reg);
46 pci_write_config16(dev, reg, 0xffff);
47 ones = pci_read_config16(dev, reg);
49 pci_write_config16(dev, reg, 0x0000);
50 zeroes = pci_read_config16(dev, reg);
52 pci_write_config16(dev, reg, value);
57 static uint32_t pci_moving_config32(struct device *dev, unsigned reg)
59 uint32_t value, ones, zeroes;
60 value = pci_read_config32(dev, reg);
62 pci_write_config32(dev, reg, 0xffffffff);
63 ones = pci_read_config32(dev, reg);
65 pci_write_config32(dev, reg, 0x00000000);
66 zeroes = pci_read_config32(dev, reg);
68 pci_write_config32(dev, reg, value);
73 unsigned pci_find_capability(device_t dev, unsigned cap)
77 switch(dev->hdr_type & 0x7f) {
78 case PCI_HEADER_TYPE_NORMAL:
79 case PCI_HEADER_TYPE_BRIDGE:
80 pos = PCI_CAPABILITY_LIST;
83 if (pos > PCI_CAP_LIST_NEXT) {
84 pos = pci_read_config8(dev, pos);
86 while (pos != 0) { /* loop through the linked list */
88 this_cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID);
89 if (this_cap == cap) {
96 /** Given a device and register, read the size of the BAR for that register.
97 * @param dev Pointer to the device structure
98 * @param resource Pointer to the resource structure
99 * @param index Address of the pci configuration register
101 struct resource *pci_get_resource(struct device *dev, unsigned long index)
103 struct resource *resource;
104 unsigned long value, attr;
105 resource_t moving, limit;
107 /* Initialize the resources to nothing */
108 resource = new_resource(dev, index);
110 /* Get the initial value */
111 value = pci_read_config32(dev, index);
113 /* See which bits move */
114 moving = pci_moving_config32(dev, index);
116 /* Initialize attr to the bits that do not move */
117 attr = value & ~moving;
119 /* If it is a 64bit resource look at the high half as well */
120 if (((attr & PCI_BASE_ADDRESS_SPACE_IO) == 0) &&
121 ((attr & PCI_BASE_ADDRESS_MEM_LIMIT_MASK) == PCI_BASE_ADDRESS_MEM_LIMIT_64))
123 /* Find the high bits that move */
124 moving |= ((resource_t)pci_moving_config32(dev, index + 4)) << 32;
126 /* Find the resource constraints.
128 * Start by finding the bits that move. From there:
129 * - Size is the least significant bit of the bits that move.
130 * - Limit is all of the bits that move plus all of the lower bits.
131 * See PCI Spec 6.2.5.1 ...
136 resource->align = resource->gran = 0;
137 while (!(moving & resource->size)) {
138 resource->size <<= 1;
139 resource->align += 1;
142 resource->limit = limit = moving | (resource->size - 1);
145 * some broken hardware has read-only registers that do not
146 * really size correctly.
147 * Example: the acer m7229 has BARs 1-4 normally read-only.
148 * so BAR1 at offset 0x10 reads 0x1f1. If you size that register
149 * by writing 0xffffffff to it, it will read back as 0x1f1 -- a
150 * violation of the spec.
151 * We catch this case and ignore it by observing which bits move,
152 * This also catches the common case unimplemented registers
153 * that always read back as 0.
157 printk_debug("%s register %02x(%08x), read-only ignoring it\n",
158 dev_path(dev), index, value);
161 } else if (attr & PCI_BASE_ADDRESS_SPACE_IO) {
162 /* An I/O mapped base address */
163 attr &= PCI_BASE_ADDRESS_IO_ATTR_MASK;
164 resource->flags |= IORESOURCE_IO;
165 /* I don't want to deal with 32bit I/O resources */
166 resource->limit = 0xffff;
168 /* A Memory mapped base address */
169 attr &= PCI_BASE_ADDRESS_MEM_ATTR_MASK;
170 resource->flags |= IORESOURCE_MEM;
171 if (attr & PCI_BASE_ADDRESS_MEM_PREFETCH) {
172 resource->flags |= IORESOURCE_PREFETCH;
174 attr &= PCI_BASE_ADDRESS_MEM_LIMIT_MASK;
175 if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_32) {
177 resource->limit = 0xffffffffUL;
178 } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_1M) {
180 resource->limit = 0x000fffffUL;
181 } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_64) {
183 resource->limit = 0xffffffffffffffffULL;
184 resource->flags |= IORESOURCE_PCI64;
190 /* Don't let the limit exceed which bits can move */
191 if (resource->limit > limit) {
192 resource->limit = limit;
195 if (resource->flags) {
196 printk_debug("%s %02x ->",
197 dev_path(dev), resource->index);
198 printk_debug(" value: 0x%08Lx zeroes: 0x%08Lx ones: 0x%08Lx attr: %08lx\n",
199 value, zeroes, ones, attr);
201 "%s %02x -> size: 0x%08Lx max: 0x%08Lx %s%s\n ",
204 resource->size, resource->limit,
205 (resource->flags == 0) ? "unused":
206 (resource->flags & IORESOURCE_IO)? "io":
207 (resource->flags & IORESOURCE_PREFETCH)? "prefmem": "mem",
208 (resource->flags & IORESOURCE_PCI64)?"64":"");
215 static void pci_get_rom_resource(struct device *dev, unsigned long index)
217 struct resource *resource;
219 resource_t moving, limit;
221 /* Initialize the resources to nothing */
222 resource = new_resource(dev, index);
224 /* for on board device with embedded ROM image, the ROM image is at
225 * fixed address specified in the Config.lb, the dev->rom_address is
226 * inited by driver_pci_onboard_ops::enable_dev() */
227 if ((dev->on_mainboard) && (dev->rom_address == 0)) {
228 resource->base = dev->rom_address;
229 resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY |
230 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
234 /* Get the initial value */
235 value = pci_read_config32(dev, index);
237 /* See which bits move */
238 moving = pci_moving_config32(dev, index);
239 /* clear the Enable bit */
240 moving = moving & ~PCI_ROM_ADDRESS_ENABLE;
242 /* Find the resource constraints.
244 * Start by finding the bits that move. From there:
245 * - Size is the least significant bit of the bits that move.
246 * - Limit is all of the bits that move plus all of the lower bits.
247 * See PCI Spec 6.2.5.1 ...
253 resource->align = resource->gran = 0;
254 while (!(moving & resource->size)) {
255 resource->size <<= 1;
256 resource->align += 1;
259 resource->limit = limit = moving | (resource->size - 1);
264 printk_debug("%s register %02x(%08x), read-only ignoring it\n",
265 dev_path(dev), index, value);
269 resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY;
273 /** Read the base address registers for a given device.
274 * @param dev Pointer to the dev structure
275 * @param howmany How many registers to read (6 for device, 2 for bridge)
277 static void pci_read_bases(struct device *dev, unsigned int howmany, unsigned long rom)
281 for (index = PCI_BASE_ADDRESS_0; (index < PCI_BASE_ADDRESS_0 + (howmany << 2)); ) {
282 struct resource *resource;
283 resource = pci_get_resource(dev, index);
284 index += (resource->flags & IORESOURCE_PCI64)?8:4;
287 pci_get_rom_resource(dev, rom);
289 compact_resources(dev);
292 static void pci_set_resource(struct device *dev, struct resource *resource);
294 static void pci_record_bridge_resource( struct device *dev, resource_t moving,
295 unsigned index, unsigned long mask,
298 /* Initiliaze the constraints on the current bus */
299 struct resource *resource;
304 resource = new_resource(dev, index);
308 while((moving & step) == 0) {
312 resource->gran = gran;
313 resource->align = gran;
314 resource->limit = moving | (step - 1);
315 resource->flags = type | IORESOURCE_PCI_BRIDGE;
316 compute_allocate_resource(&dev->link[0], resource, mask, type);
317 /* If there is nothing behind the resource,
318 * clear it and forget it.
320 if (resource->size == 0) {
321 resource->base = moving;
322 resource->flags |= IORESOURCE_ASSIGNED;
323 resource->flags &= ~IORESOURCE_STORED;
324 pci_set_resource(dev, resource);
331 static void pci_bridge_read_bases(struct device *dev)
333 resource_t moving_base, moving_limit, moving;
335 /* See if the bridge I/O resources are implemented */
336 moving_base = ((uint32_t)pci_moving_config8(dev, PCI_IO_BASE)) << 8;
337 moving_base |= ((uint32_t)pci_moving_config16(dev, PCI_IO_BASE_UPPER16)) << 16;
339 moving_limit = ((uint32_t)pci_moving_config8(dev, PCI_IO_LIMIT)) << 8;
340 moving_limit |= ((uint32_t)pci_moving_config16(dev, PCI_IO_LIMIT_UPPER16)) << 16;
342 moving = moving_base & moving_limit;
344 /* Initialize the io space constraints on the current bus */
345 pci_record_bridge_resource(dev, moving, PCI_IO_BASE,
346 IORESOURCE_IO, IORESOURCE_IO);
348 /* See if the bridge prefmem resources are implemented */
349 moving_base = ((resource_t)pci_moving_config16(dev, PCI_PREF_MEMORY_BASE)) << 16;
350 moving_base |= ((resource_t)pci_moving_config32(dev, PCI_PREF_BASE_UPPER32)) << 32;
352 moving_limit = ((resource_t)pci_moving_config16(dev, PCI_PREF_MEMORY_LIMIT)) << 16;
353 moving_limit |= ((resource_t)pci_moving_config32(dev, PCI_PREF_LIMIT_UPPER32)) << 32;
355 moving = moving_base & moving_limit;
356 /* Initiliaze the prefetchable memory constraints on the current bus */
357 pci_record_bridge_resource(dev, moving, PCI_PREF_MEMORY_BASE,
358 IORESOURCE_MEM | IORESOURCE_PREFETCH,
359 IORESOURCE_MEM | IORESOURCE_PREFETCH);
361 /* See if the bridge mem resources are implemented */
362 moving_base = ((uint32_t)pci_moving_config16(dev, PCI_MEMORY_BASE)) << 16;
363 moving_limit = ((uint32_t)pci_moving_config16(dev, PCI_MEMORY_LIMIT)) << 16;
365 moving = moving_base & moving_limit;
367 /* Initialize the memory resources on the current bus */
368 pci_record_bridge_resource(dev, moving, PCI_MEMORY_BASE,
369 IORESOURCE_MEM | IORESOURCE_PREFETCH,
372 compact_resources(dev);
375 void pci_dev_read_resources(struct device *dev)
379 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
382 void pci_bus_read_resources(struct device *dev)
386 pci_bridge_read_bases(dev);
387 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
390 static void pci_set_resource(struct device *dev, struct resource *resource)
392 resource_t base, end;
394 /* Make certain the resource has actually been set */
395 if (!(resource->flags & IORESOURCE_ASSIGNED)) {
396 printk_err("ERROR: %s %02x not allocated\n",
397 dev_path(dev), resource->index);
401 /* If I have already stored this resource don't worry about it */
402 if (resource->flags & IORESOURCE_STORED) {
406 /* If the resources is substractive don't worry about it */
407 if (resource->flags & IORESOURCE_SUBTRACTIVE) {
411 /* Only handle PCI memory and IO resources for now */
412 if (!(resource->flags & (IORESOURCE_MEM |IORESOURCE_IO)))
415 /* Enable the resources in the command register */
416 if (resource->size) {
417 if (resource->flags & IORESOURCE_MEM) {
418 dev->command |= PCI_COMMAND_MEMORY;
420 if (resource->flags & IORESOURCE_IO) {
421 dev->command |= PCI_COMMAND_IO;
423 if (resource->flags & IORESOURCE_PCI_BRIDGE) {
424 dev->command |= PCI_COMMAND_MASTER;
427 /* Get the base address */
428 base = resource->base;
431 end = resource_end(resource);
433 /* Now store the resource */
434 resource->flags |= IORESOURCE_STORED;
435 if (!(resource->flags & IORESOURCE_PCI_BRIDGE)) {
436 unsigned long base_lo, base_hi;
438 * some chipsets allow us to set/clear the IO bit.
439 * (e.g. VIA 82c686a.) So set it to be safe)
441 base_lo = base & 0xffffffff;
442 base_hi = (base >> 32) & 0xffffffff;
443 if (resource->flags & IORESOURCE_IO) {
444 base_lo |= PCI_BASE_ADDRESS_SPACE_IO;
446 pci_write_config32(dev, resource->index, base_lo);
447 if (resource->flags & IORESOURCE_PCI64) {
448 pci_write_config32(dev, resource->index + 4, base_hi);
451 else if (resource->index == PCI_IO_BASE) {
452 /* set the IO ranges */
453 compute_allocate_resource(&dev->link[0], resource,
454 IORESOURCE_IO, IORESOURCE_IO);
455 pci_write_config8(dev, PCI_IO_BASE, base >> 8);
456 pci_write_config16(dev, PCI_IO_BASE_UPPER16, base >> 16);
457 pci_write_config8(dev, PCI_IO_LIMIT, end >> 8);
458 pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, end >> 16);
460 else if (resource->index == PCI_MEMORY_BASE) {
461 /* set the memory range */
462 compute_allocate_resource(&dev->link[0], resource,
463 IORESOURCE_MEM | IORESOURCE_PREFETCH,
465 pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);
466 pci_write_config16(dev, PCI_MEMORY_LIMIT, end >> 16);
468 else if (resource->index == PCI_PREF_MEMORY_BASE) {
469 /* set the prefetchable memory range */
470 compute_allocate_resource(&dev->link[0], resource,
471 IORESOURCE_MEM | IORESOURCE_PREFETCH,
472 IORESOURCE_MEM | IORESOURCE_PREFETCH);
473 pci_write_config16(dev, PCI_PREF_MEMORY_BASE, base >> 16);
474 pci_write_config32(dev, PCI_PREF_BASE_UPPER32, base >> 32);
475 pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, end >> 16);
476 pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, end >> 32);
479 /* Don't let me think I stored the resource */
480 resource->flags &= ~IORESOURCE_STORED;
481 printk_err("ERROR: invalid resource->index %x\n",
484 report_resource_stored(dev, resource, "");
488 void pci_dev_set_resources(struct device *dev)
490 struct resource *resource, *last;
494 last = &dev->resource[dev->resources];
496 for (resource = &dev->resource[0]; resource < last; resource++) {
497 pci_set_resource(dev, resource);
499 for (link = 0; link < dev->links; link++) {
501 bus = &dev->link[link];
503 assign_resources(bus);
507 /* set a default latency timer */
508 pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
510 /* set a default secondary latency timer */
511 if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
512 pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
515 /* zero the irq settings */
516 line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
518 pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
520 /* set the cache line size, so far 64 bytes is good for everyone */
521 pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
524 void pci_dev_enable_resources(struct device *dev)
526 const struct pci_operations *ops;
529 /* Set the subsystem vendor and device id for mainboard devices */
531 if (dev->on_mainboard && ops && ops->set_subsystem) {
532 printk_debug("%s subsystem <- %02x/%02x\n",
534 MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
535 MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
536 ops->set_subsystem(dev,
537 MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
538 MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
540 command = pci_read_config16(dev, PCI_COMMAND);
541 command |= dev->command;
542 command |= (PCI_COMMAND_PARITY + PCI_COMMAND_SERR); /* error check */
543 printk_debug("%s cmd <- %02x\n", dev_path(dev), command);
544 pci_write_config16(dev, PCI_COMMAND, command);
547 void pci_bus_enable_resources(struct device *dev)
551 /* enable IO in command register if there is VGA card
552 * connected with (even it does not claim IO resource) */
553 if (dev->link[0].bridge_ctrl & PCI_BRIDGE_CTL_VGA)
554 dev->command |= PCI_COMMAND_IO;
556 ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
557 ctrl |= dev->link[0].bridge_ctrl;
558 ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error check */
559 printk_debug("%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
560 pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
562 pci_dev_enable_resources(dev);
564 enable_childrens_resources(dev);
567 void pci_dev_set_subsystem(device_t dev, unsigned vendor, unsigned device)
569 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
570 ((device & 0xffff) << 16) | (vendor & 0xffff));
573 void pci_dev_init(struct device *dev)
575 struct rom_header *rom, *ram;
577 rom = pci_rom_probe(dev);
580 ram = pci_rom_load(dev, rom);
585 /** Default device operation for PCI devices */
586 static struct pci_operations pci_dev_ops_pci = {
587 .set_subsystem = pci_dev_set_subsystem,
590 struct device_operations default_pci_ops_dev = {
591 .read_resources = pci_dev_read_resources,
592 .set_resources = pci_dev_set_resources,
593 .enable_resources = pci_dev_enable_resources,
594 .init = pci_dev_init,
597 .ops_pci = &pci_dev_ops_pci,
600 /** Default device operations for PCI bridges */
601 static struct pci_operations pci_bus_ops_pci = {
605 struct device_operations default_pci_ops_bus = {
606 .read_resources = pci_bus_read_resources,
607 .set_resources = pci_dev_set_resources,
608 .enable_resources = pci_bus_enable_resources,
610 .scan_bus = pci_scan_bridge,
612 .ops_pci = &pci_bus_ops_pci,
616 * @brief Set up PCI device operation
623 static void set_pci_ops(struct device *dev)
625 struct pci_driver *driver;
630 /* Look through the list of setup drivers and find one for
633 for (driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) {
634 if ((driver->vendor == dev->vendor) &&
635 (driver->device == dev->device))
637 dev->ops = driver->ops;
638 printk_debug("%s [%04x/%04x] %sops\n",
640 driver->vendor, driver->device,
641 (driver->ops->scan_bus?"bus ":""));
646 /* If I don't have a specific driver use the default operations */
647 switch(dev->hdr_type & 0x7f) { /* header type */
648 case PCI_HEADER_TYPE_NORMAL: /* standard header */
649 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
651 dev->ops = &default_pci_ops_dev;
653 case PCI_HEADER_TYPE_BRIDGE:
654 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
656 dev->ops = &default_pci_ops_bus;
661 printk_err("%s [%04x/%04x/%06x] has unknown header "
662 "type %02x, ignoring.\n",
664 dev->vendor, dev->device,
665 dev->class >> 8, dev->hdr_type);
672 * @brief See if we have already allocated a device structure for a given devfn.
674 * Given a linked list of PCI device structures and a devfn number, find the
675 * device structure correspond to the devfn, if present. This function also
676 * removes the device structure from the linked list.
678 * @param list the device structure list
679 * @param devfn a device/function number
681 * @return pointer to the device structure found or null of we have not
682 * allocated a device for this devfn yet.
684 static struct device *pci_scan_get_dev(struct device **list, unsigned int devfn)
688 for(; *list; list = &(*list)->sibling) {
689 if ((*list)->path.type != DEVICE_PATH_PCI) {
690 printk_err("child %s not a pci device\n",
694 if ((*list)->path.u.pci.devfn == devfn) {
695 /* Unlink from the list */
697 *list = (*list)->sibling;
702 /* Just like alloc_dev add the device to the list of device on the bus.
703 * When the list of devices was formed we removed all of the parents
704 * children, and now we are interleaving static and dynamic devices in
709 /* Find the last child of our parent */
710 for (child = dev->bus->children; child && child->sibling; ) {
711 child = child->sibling;
713 /* Place the device on the list of children of it's parent. */
715 child->sibling = dev;
717 dev->bus->children = dev;
725 * @brief Scan a PCI bus.
727 * Determine the existence of devices and bridges on a PCI bus. If there are
728 * bridges on the bus, recursively scan the buses behind the bridges.
730 * @param bus pointer to the bus structure
731 * @param min_devfn minimum devfn to look at in the scan usually 0x00
732 * @param max_devfn maximum devfn to look at in the scan usually 0xff
733 * @param max current bus number
735 * @return The maximum bus number found, after scanning all subordinate busses
737 unsigned int pci_scan_bus(struct bus *bus, unsigned min_devfn, unsigned max_devfn,
742 device_t old_devices;
745 printk_debug("PCI: pci_scan_bus for bus %d\n", bus->secondary);
747 old_devices = bus->children;
752 /* probe all devices/functions on this bus with some optimization for
753 * non-existence and single funcion devices
755 for (devfn = min_devfn; devfn <= max_devfn; devfn++) {
759 /* First thing setup the device structure */
760 dev = pci_scan_get_dev(&old_devices, devfn);
762 /* Detect if a device is present */
766 dummy.path.type = DEVICE_PATH_PCI;
767 dummy.path.u.pci.devfn = devfn;
768 id = pci_read_config32(&dummy, PCI_VENDOR_ID);
769 /* some broken boards return 0 if a slot is empty: */
770 if ((id == 0xffffffff) || (id == 0x00000000) ||
771 (id == 0x0000ffff) || (id == 0xffff0000))
773 printk_spew("PCI: devfn 0x%x, bad id 0x%x\n", devfn, id);
774 if (PCI_FUNC(devfn) == 0x00) {
775 /* if this is a function 0 device and
777 * skip to next device
781 /* This function in a multi function device is
782 * not present, skip to the next function.
786 dev = alloc_dev(bus, &dummy.path);
789 /* Enable/disable the device. Once we have
790 * found the device specific operations this
791 * operations we will disable the device with
794 * This is geared toward devices that have subfunctions
795 * that do not show up by default.
797 * If a device is a stuff option on the motherboard
798 * it may be absent and enable_dev must cope.
801 if (dev->chip_ops && dev->chip_ops->enable_dev)
803 dev->chip_ops->enable_dev(dev);
805 /* Now read the vendor and device id */
806 id = pci_read_config32(dev, PCI_VENDOR_ID);
808 /* If the device does not have a pci id disable it.
809 * Possibly this is because we have already disabled
810 * the device. But this also handles optional devices
811 * that may not always show up.
813 if (id == 0xffffffff || id == 0x00000000 ||
814 id == 0x0000ffff || id == 0xffff0000)
817 printk_info("Disabling static device: %s\n",
823 /* Read the rest of the pci configuration information */
824 hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
825 class = pci_read_config32(dev, PCI_CLASS_REVISION);
827 /* Store the interesting information in the device structure */
828 dev->vendor = id & 0xffff;
829 dev->device = (id >> 16) & 0xffff;
830 dev->hdr_type = hdr_type;
831 /* class code, the upper 3 bytes of PCI_CLASS_REVISION */
832 dev->class = class >> 8;
834 /* Architectural/System devices always need to
837 if ((dev->class >> 16) == PCI_BASE_CLASS_SYSTEM) {
838 dev->command |= PCI_COMMAND_MASTER;
841 /* Look at the vendor and device id, or at least the
842 * header type and class and figure out which set of
843 * configuration methods to use. Unless we already
847 /* Error if we don't have some pci operations for it */
849 printk_err("%s No device operations\n",
854 /* Now run the magic enable/disable sequence for the device */
855 if (dev->ops && dev->ops->enable) {
856 dev->ops->enable(dev);
859 printk_debug("%s [%04x/%04x] %s\n",
861 dev->vendor, dev->device,
862 dev->enabled?"enabled": "disabled");
864 if (PCI_FUNC(devfn) == 0x00 && (hdr_type & 0x80) != 0x80) {
865 /* if this is not a multi function device,
866 * don't waste time probing another function.
867 * Skip to next device.
874 /* For all children that implement scan_bus (i.e. bridges)
875 * scan the bus behind that child.
877 for (child = bus->children; child; child = child->sibling) {
878 if (!child->enabled ||
880 !child->ops->scan_bus)
884 max = child->ops->scan_bus(child, max);
888 * We've scanned the bus and so we know all about what's on
889 * the other side of any bridges that may be on this bus plus
892 * Return how far we've got finding sub-buses.
894 printk_debug("PCI: pci_scan_bus returning with max=%02x\n", max);
900 * @brief Scan a PCI bridge and the buses behind the bridge.
902 * Determine the existence of buses behind the bridge. Set up the bridge
903 * according to the result of the scan.
905 * This function is the default scan_bus() method for PCI bridge devices.
907 * @param dev pointer to the bridge device
908 * @param max the highest bus number assgined up to now
910 * @return The maximum bus number found, after scanning all subordinate busses
912 unsigned int pci_scan_bridge(struct device *dev, unsigned int max)
918 printk_spew("%s for %s\n", __func__, dev_path(dev));
924 /* Set up the primary, secondary and subordinate bus numbers. We have
925 * no idea how many buses are behind this bridge yet, so we set the
926 * subordinate bus number to 0xff for the moment.
928 bus->secondary = ++max;
929 bus->subordinate = 0xff;
931 /* Clear all status bits and turn off memory, I/O and master enables. */
932 cr = pci_read_config16(dev, PCI_COMMAND);
933 pci_write_config16(dev, PCI_COMMAND, 0x0000);
934 pci_write_config16(dev, PCI_STATUS, 0xffff);
937 * Read the existing primary/secondary/subordinate bus
938 * number configuration.
940 buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
942 /* Configure the bus numbers for this bridge: the configuration
943 * transactions will not be propagated by the bridge if it is not
944 * correctly configured.
947 buses |= (((unsigned int) (dev->bus->secondary) << 0) |
948 ((unsigned int) (bus->secondary) << 8) |
949 ((unsigned int) (bus->subordinate) << 16));
950 pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
952 /* Now we can scan all subordinate buses
953 * i.e. the bus behind the bridge.
955 max = pci_scan_bus(bus, 0x00, 0xff, max);
957 /* We know the number of buses behind this bridge. Set the subordinate
958 * bus number to its real value.
960 bus->subordinate = max;
961 buses = (buses & 0xff00ffff) |
962 ((unsigned int) (bus->subordinate) << 16);
963 pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
964 pci_write_config16(dev, PCI_COMMAND, cr);
966 printk_spew("%s returns max %d\n", __func__, max);
971 Tell the EISA int controller this int must be level triggered
972 THIS IS A KLUDGE -- sorry, this needs to get cleaned up.
974 static void pci_level_irq(unsigned char intNum)
976 unsigned short intBits = inb(0x4d0) | (((unsigned) inb(0x4d1)) << 8);
978 printk_spew("%s: current ints are 0x%x\n", __func__, intBits);
979 intBits |= (1 << intNum);
981 printk_spew("%s: try to set ints 0x%x\n", __func__, intBits);
984 outb((unsigned char) intBits, 0x4d0);
985 outb((unsigned char) (intBits >> 8), 0x4d1);
987 /* this seems like an error but is not ... */
989 if (inb(0x4d0) != (intBits & 0xf)) {
990 printk_err("%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
991 __func__, intBits &0xf, inb(0x4d0));
993 if (inb(0x4d1) != ((intBits >> 8) & 0xf)) {
994 printk_err("%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
995 __func__, (intBits>>8) &0xf, inb(0x4d1));
1001 This function assigns IRQs for all functions contained within
1002 the indicated device address. If the device does not exist or does
1003 not require interrupts then this function has no effect.
1005 This function should be called for each PCI slot in your system.
1007 pIntAtoD is an array of IRQ #s that are assigned to PINTA through PINTD of
1009 The particular irq #s that are passed in depend on the routing inside
1010 your southbridge and on your motherboard.
1014 void pci_assign_irqs(unsigned bus, unsigned slot, const unsigned char pIntAtoD[4])
1020 unsigned char readback;
1022 /* Each slot may contain up to eight functions */
1023 for (functNum = 0; functNum < 8; functNum++) {
1024 pdev = dev_find_slot(bus, (slot << 3) + functNum);
1027 line = pci_read_config8(pdev, PCI_INTERRUPT_PIN);
1029 // PCI spec says all other values are reserved
1030 if ((line >= 1) && (line <= 4)) {
1031 irq = pIntAtoD[line - 1];
1033 printk_debug("Assigning IRQ %d to %d:%x.%d\n", \
1034 irq, bus, slot, functNum);
1036 pci_write_config8(pdev, PCI_INTERRUPT_LINE,\
1037 pIntAtoD[line - 1]);
1039 readback = pci_read_config8(pdev, PCI_INTERRUPT_LINE);
1040 printk_debug(" Readback = %d\n", readback);
1042 // Change to level triggered
1043 pci_level_irq(pIntAtoD[line - 1]);