2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
9 * Copyright 2003 -- Eric Biederman <ebiederman@lnxi.com>
12 #include <console/console.h>
18 #include <device/device.h>
19 #include <device/pci.h>
20 #include <device/pci_ids.h>
21 #include <part/hard_reset.h>
22 #include <part/fallback_boot.h>
25 static uint8_t pci_moving_config8(struct device *dev, unsigned reg)
27 uint8_t value, ones, zeroes;
28 value = pci_read_config8(dev, reg);
30 pci_write_config8(dev, reg, 0xff);
31 ones = pci_read_config8(dev, reg);
33 pci_write_config8(dev, reg, 0x00);
34 zeroes = pci_read_config8(dev, reg);
36 pci_write_config8(dev, reg, value);
40 static uint16_t pci_moving_config16(struct device *dev, unsigned reg)
42 uint16_t value, ones, zeroes;
43 value = pci_read_config16(dev, reg);
45 pci_write_config16(dev, reg, 0xffff);
46 ones = pci_read_config16(dev, reg);
48 pci_write_config16(dev, reg, 0x0000);
49 zeroes = pci_read_config16(dev, reg);
51 pci_write_config16(dev, reg, value);
55 static uint32_t pci_moving_config32(struct device *dev, unsigned reg)
57 uint32_t value, ones, zeroes;
58 value = pci_read_config32(dev, reg);
60 pci_write_config32(dev, reg, 0xffffffff);
61 ones = pci_read_config32(dev, reg);
63 pci_write_config32(dev, reg, 0x00000000);
64 zeroes = pci_read_config32(dev, reg);
66 pci_write_config32(dev, reg, value);
71 unsigned pci_find_capability(device_t dev, unsigned cap)
75 switch(dev->hdr_type & 0x7f) {
76 case PCI_HEADER_TYPE_NORMAL:
77 case PCI_HEADER_TYPE_BRIDGE:
78 pos = PCI_CAPABILITY_LIST;
81 if (pos > PCI_CAP_LIST_NEXT) {
82 pos = pci_read_config8(dev, pos);
84 while(pos != 0) { /* loop through the linked list */
86 this_cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID);
87 if (this_cap == cap) {
95 /** Given a device and register, read the size of the BAR for that register.
96 * @param dev Pointer to the device structure
97 * @param resource Pointer to the resource structure
98 * @param index Address of the pci configuration register
100 struct resource *pci_get_resource(struct device *dev, unsigned long index)
102 struct resource *resource;
103 unsigned long value, attr;
104 resource_t moving, limit;
106 /* Initialize the resources to nothing */
107 resource = new_resource(dev, index);
109 /* Get the initial value */
110 value = pci_read_config32(dev, index);
112 /* See which bits move */
113 moving = pci_moving_config32(dev, index);
115 /* Initialize attr to the bits that do not move */
116 attr = value & ~moving;
118 /* If it is a 64bit resource look at the high half as well */
119 if (((attr & PCI_BASE_ADDRESS_SPACE_IO) == 0) &&
120 ((attr & PCI_BASE_ADDRESS_MEM_LIMIT_MASK) == PCI_BASE_ADDRESS_MEM_LIMIT_64))
122 /* Find the high bits that move */
123 moving |= ((resource_t)pci_moving_config32(dev, index + 4)) << 32;
125 /* Find the resource constraints.
127 * Start by finding the bits that move. From there:
128 * - Size is the least significant bit of the bits that move.
129 * - Limit is all of the bits that move plus all of the lower bits.
130 * See PCI Spec 6.2.5.1 ...
135 resource->align = resource->gran = 0;
136 while(!(moving & resource->size)) {
137 resource->size <<= 1;
138 resource->align += 1;
141 resource->limit = limit = moving | (resource->size - 1);
144 * some broken hardware has read-only registers that do not
145 * really size correctly.
146 * Example: the acer m7229 has BARs 1-4 normally read-only.
147 * so BAR1 at offset 0x10 reads 0x1f1. If you size that register
148 * by writing 0xffffffff to it, it will read back as 0x1f1 -- a
149 * violation of the spec.
150 * We catch this case and ignore it by observing which bits move,
151 * This also catches the common case unimplemented registers
152 * that always read back as 0.
157 "%s register %02x(%08x), read-only ignoring it\n",
158 dev_path(dev), index, value);
162 else if (attr & PCI_BASE_ADDRESS_SPACE_IO) {
163 /* An I/O mapped base address */
164 attr &= PCI_BASE_ADDRESS_IO_ATTR_MASK;
165 resource->flags |= IORESOURCE_IO;
166 /* I don't want to deal with 32bit I/O resources */
167 resource->limit = 0xffff;
170 /* A Memory mapped base address */
171 attr &= PCI_BASE_ADDRESS_MEM_ATTR_MASK;
172 resource->flags |= IORESOURCE_MEM;
173 if (attr & PCI_BASE_ADDRESS_MEM_PREFETCH) {
174 resource->flags |= IORESOURCE_PREFETCH;
176 attr &= PCI_BASE_ADDRESS_MEM_LIMIT_MASK;
177 if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_32) {
179 resource->limit = 0xffffffffUL;
181 else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_1M) {
183 resource->limit = 0x000fffffUL;
185 else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_64) {
187 resource->limit = 0xffffffffffffffffULL;
188 resource->flags |= IORESOURCE_PCI64;
195 /* Don't let the limit exceed which bits can move */
196 if (resource->limit > limit) {
197 resource->limit = limit;
200 if (resource->flags) {
201 printk_debug("%s %02x ->",
202 dev_path(dev), resource->index);
203 printk_debug(" value: 0x%08Lx zeroes: 0x%08Lx ones: 0x%08Lx attr: %08lx\n",
204 value, zeroes, ones, attr);
206 "%s %02x -> size: 0x%08Lx max: 0x%08Lx %s%s\n ",
209 resource->size, resource->limit,
210 (resource->flags == 0) ? "unused":
211 (resource->flags & IORESOURCE_IO)? "io":
212 (resource->flags & IORESOURCE_PREFETCH)? "prefmem": "mem",
213 (resource->flags & IORESOURCE_PCI64)?"64":"");
220 /** Read the base address registers for a given device.
221 * @param dev Pointer to the dev structure
222 * @param howmany How many registers to read (6 for device, 2 for bridge)
224 static void pci_read_bases(struct device *dev, unsigned int howmany)
228 for(index = PCI_BASE_ADDRESS_0; (index < PCI_BASE_ADDRESS_0 + (howmany << 2)); ) {
229 struct resource *resource;
230 resource = pci_get_resource(dev, index);
231 index += (resource->flags & IORESOURCE_PCI64)?8:4;
233 compact_resources(dev);
236 static void pci_set_resource(struct device *dev, struct resource *resource);
238 static void pci_record_bridge_resource(
239 struct device *dev, resource_t moving,
240 unsigned index, unsigned long mask, unsigned long type)
242 /* Initiliaze the constraints on the current bus */
243 struct resource *resource;
248 resource = new_resource(dev, index);
252 while((moving & step) == 0) {
256 resource->gran = gran;
257 resource->align = gran;
258 resource->limit = moving | (step - 1);
259 resource->flags = type | IORESOURCE_PCI_BRIDGE;
260 compute_allocate_resource(&dev->link[0], resource, mask, type);
261 /* If there is nothing behind the resource,
262 * clear it and forget it.
264 if (resource->size == 0) {
265 resource->base = moving;
266 resource->flags |= IORESOURCE_ASSIGNED;
267 resource->flags &= ~IORESOURCE_STORED;
268 pci_set_resource(dev, resource);
276 static void pci_bridge_read_bases(struct device *dev)
278 resource_t moving_base, moving_limit, moving;
281 /* See if the bridge I/O resources are implemented */
282 moving_base = ((uint32_t)pci_moving_config8(dev, PCI_IO_BASE)) << 8;
283 moving_base |= ((uint32_t)pci_moving_config16(dev, PCI_IO_BASE_UPPER16)) << 16;
285 moving_limit = ((uint32_t)pci_moving_config8(dev, PCI_IO_LIMIT)) << 8;
286 moving_limit |= ((uint32_t)pci_moving_config16(dev, PCI_IO_LIMIT_UPPER16)) << 16;
288 moving = moving_base & moving_limit;
290 /* Initialize the io space constraints on the current bus */
291 pci_record_bridge_resource(
292 dev, moving, PCI_IO_BASE,
293 IORESOURCE_IO, IORESOURCE_IO);
296 /* See if the bridge prefmem resources are implemented */
297 moving_base = ((resource_t)pci_moving_config16(dev, PCI_PREF_MEMORY_BASE)) << 16;
298 moving_base |= ((resource_t)pci_moving_config32(dev, PCI_PREF_BASE_UPPER32)) << 32;
300 moving_limit = ((resource_t)pci_moving_config16(dev, PCI_PREF_MEMORY_LIMIT)) << 16;
301 moving_limit |= ((resource_t)pci_moving_config32(dev, PCI_PREF_LIMIT_UPPER32)) << 32;
303 moving = moving_base & moving_limit;
304 /* Initiliaze the prefetchable memory constraints on the current bus */
305 pci_record_bridge_resource(
306 dev, moving, PCI_PREF_MEMORY_BASE,
307 IORESOURCE_MEM | IORESOURCE_PREFETCH,
308 IORESOURCE_MEM | IORESOURCE_PREFETCH);
311 /* See if the bridge mem resources are implemented */
312 moving_base = ((uint32_t)pci_moving_config16(dev, PCI_MEMORY_BASE)) << 16;
313 moving_limit = ((uint32_t)pci_moving_config16(dev, PCI_MEMORY_LIMIT)) << 16;
315 moving = moving_base & moving_limit;
317 /* Initialize the memory resources on the current bus */
318 pci_record_bridge_resource(
319 dev, moving, PCI_MEMORY_BASE,
320 IORESOURCE_MEM | IORESOURCE_PREFETCH,
323 compact_resources(dev);
326 void pci_dev_read_resources(struct device *dev)
330 pci_read_bases(dev, 6);
332 addr = pci_read_config32(dev, PCI_ROM_ADDRESS);
333 dev->rom_address = (addr == 0xffffffff)? 0 : addr;
336 void pci_bus_read_resources(struct device *dev)
340 pci_bridge_read_bases(dev);
341 pci_read_bases(dev, 2);
343 addr = pci_read_config32(dev, PCI_ROM_ADDRESS1);
344 dev->rom_address = (addr == 0xffffffff)? 0 : addr;
347 static void pci_set_resource(struct device *dev, struct resource *resource)
349 resource_t base, end;
351 /* Make certain the resource has actually been set */
352 if (!(resource->flags & IORESOURCE_ASSIGNED)) {
353 printk_err("ERROR: %s %02x not allocated\n",
354 dev_path(dev), resource->index);
358 /* If I have already stored this resource don't worry about it */
359 if (resource->flags & IORESOURCE_STORED) {
363 /* If the resources is substractive don't worry about it */
364 if (resource->flags & IORESOURCE_SUBTRACTIVE) {
368 /* Only handle PCI memory and IO resources for now */
369 if (!(resource->flags & (IORESOURCE_MEM |IORESOURCE_IO)))
372 /* Enable the resources in the command register */
373 if (resource->size) {
374 if (resource->flags & IORESOURCE_MEM) {
375 dev->command |= PCI_COMMAND_MEMORY;
377 if (resource->flags & IORESOURCE_IO) {
378 dev->command |= PCI_COMMAND_IO;
380 if (resource->flags & IORESOURCE_PCI_BRIDGE) {
381 dev->command |= PCI_COMMAND_MASTER;
384 /* Get the base address */
385 base = resource->base;
388 end = resource_end(resource);
390 /* Now store the resource */
391 resource->flags |= IORESOURCE_STORED;
392 if (!(resource->flags & IORESOURCE_PCI_BRIDGE)) {
393 unsigned long base_lo, base_hi;
395 * some chipsets allow us to set/clear the IO bit.
396 * (e.g. VIA 82c686a.) So set it to be safe)
398 base_lo = base & 0xffffffff;
399 base_hi = (base >> 32) & 0xffffffff;
400 if (resource->flags & IORESOURCE_IO) {
401 base_lo |= PCI_BASE_ADDRESS_SPACE_IO;
403 pci_write_config32(dev, resource->index, base_lo);
404 if (resource->flags & IORESOURCE_PCI64) {
405 pci_write_config32(dev, resource->index + 4, base_hi);
408 else if (resource->index == PCI_IO_BASE) {
409 /* set the IO ranges */
410 compute_allocate_resource(&dev->link[0], resource,
411 IORESOURCE_IO, IORESOURCE_IO);
412 pci_write_config8(dev, PCI_IO_BASE, base >> 8);
413 pci_write_config16(dev, PCI_IO_BASE_UPPER16, base >> 16);
414 pci_write_config8(dev, PCI_IO_LIMIT, end >> 8);
415 pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, end >> 16);
417 else if (resource->index == PCI_MEMORY_BASE) {
418 /* set the memory range */
419 compute_allocate_resource(&dev->link[0], resource,
420 IORESOURCE_MEM | IORESOURCE_PREFETCH,
422 pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);
423 pci_write_config16(dev, PCI_MEMORY_LIMIT, end >> 16);
425 else if (resource->index == PCI_PREF_MEMORY_BASE) {
426 /* set the prefetchable memory range */
427 compute_allocate_resource(&dev->link[0], resource,
428 IORESOURCE_MEM | IORESOURCE_PREFETCH,
429 IORESOURCE_MEM | IORESOURCE_PREFETCH);
430 pci_write_config16(dev, PCI_PREF_MEMORY_BASE, base >> 16);
431 pci_write_config32(dev, PCI_PREF_BASE_UPPER32, base >> 32);
432 pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, end >> 16);
433 pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, end >> 32);
436 /* Don't let me think I stored the resource */
437 resource->flags &= ~IORESOURCE_STORED;
438 printk_err("ERROR: invalid resource->index %x\n",
441 report_resource_stored(dev, resource, "");
445 void pci_dev_set_resources(struct device *dev)
447 struct resource *resource, *last;
451 last = &dev->resource[dev->resources];
453 for(resource = &dev->resource[0]; resource < last; resource++) {
454 pci_set_resource(dev, resource);
456 for(link = 0; link < dev->links; link++) {
458 bus = &dev->link[link];
460 assign_resources(bus);
464 /* set a default latency timer */
465 pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
467 /* set a default secondary latency timer */
468 if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
469 pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
472 /* zero the irq settings */
473 line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
475 pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
477 /* set the cache line size, so far 64 bytes is good for everyone */
478 pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
481 void pci_dev_enable_resources(struct device *dev)
483 const struct pci_operations *ops;
486 /* Set the subsystem vendor and device id for mainboard devices */
488 if (dev->on_mainboard && ops && ops->set_subsystem) {
489 printk_debug("%s subsystem <- %02x/%02x\n",
491 MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
492 MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
493 ops->set_subsystem(dev,
494 MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
495 MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
497 command = pci_read_config16(dev, PCI_COMMAND);
498 command |= dev->command;
499 command |= (PCI_COMMAND_PARITY + PCI_COMMAND_SERR); /* error check */
500 printk_debug("%s cmd <- %02x\n", dev_path(dev), command);
501 pci_write_config16(dev, PCI_COMMAND, command);
504 void pci_bus_enable_resources(struct device *dev)
507 ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
508 ctrl |= dev->link[0].bridge_ctrl;
509 ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error check */
510 printk_debug("%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
511 pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
513 pci_dev_enable_resources(dev);
515 enable_childrens_resources(dev);
519 void pci_dev_set_subsystem(device_t dev, unsigned vendor, unsigned device)
521 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
522 ((device & 0xffff) << 16) | (vendor & 0xffff));
525 /** Default device operation for PCI devices */
526 static struct pci_operations pci_dev_ops_pci = {
527 .set_subsystem = pci_dev_set_subsystem,
530 struct device_operations default_pci_ops_dev = {
531 .read_resources = pci_dev_read_resources,
532 .set_resources = pci_dev_set_resources,
533 .enable_resources = pci_dev_enable_resources,
537 .ops_pci = &pci_dev_ops_pci,
540 /** Default device operations for PCI bridges */
541 static struct pci_operations pci_bus_ops_pci = {
544 struct device_operations default_pci_ops_bus = {
545 .read_resources = pci_bus_read_resources,
546 .set_resources = pci_dev_set_resources,
547 .enable_resources = pci_bus_enable_resources,
549 .scan_bus = pci_scan_bridge,
551 .ops_pci = &pci_bus_ops_pci,
555 * @brief Set up PCI device operation
562 static void set_pci_ops(struct device *dev)
564 struct pci_driver *driver;
569 /* Look through the list of setup drivers and find one for
572 for(driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) {
573 if ((driver->vendor == dev->vendor) &&
574 (driver->device == dev->device))
576 dev->ops = driver->ops;
577 printk_debug("%s [%04x/%04x] %sops\n",
579 driver->vendor, driver->device,
580 (driver->ops->scan_bus?"bus ":""));
585 /* If I don't have a specific driver use the default operations */
586 switch(dev->hdr_type & 0x7f) { /* header type */
587 case PCI_HEADER_TYPE_NORMAL: /* standard header */
588 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
590 dev->ops = &default_pci_ops_dev;
592 case PCI_HEADER_TYPE_BRIDGE:
593 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
595 dev->ops = &default_pci_ops_bus;
600 printk_err("%s [%04x/%04x/%06x] has unknown header "
601 "type %02x, ignoring.\n",
603 dev->vendor, dev->device,
604 dev->class >> 8, dev->hdr_type);
611 * @brief See if we have already allocated a device structure for a given devfn.
613 * Given a linked list of PCI device structures and a devfn number, find the
614 * device structure correspond to the devfn, if present.
616 * @param list the device structure list
617 * @param devfn a device/function number
619 * @return pointer to the device structure found or null of we have not allocated
620 * a device for this devfn yet.
622 static struct device *pci_scan_get_dev(struct device **list, unsigned int devfn)
626 for(; *list; list = &(*list)->sibling) {
627 if ((*list)->path.type != DEVICE_PATH_PCI) {
628 printk_err("child %s not a pci device\n",
632 if ((*list)->path.u.pci.devfn == devfn) {
633 /* Unlink from the list */
635 *list = (*list)->sibling;
640 /* Just like alloc_dev add the device to the
641 * list of device on the bus. When the list of devices was formed
642 * we removed all of the parents children, and now we are interleaving
643 * static and dynamic devices in order on the bus.
647 /* Find the last child of our parent */
648 for(child = dev->bus->children; child && child->sibling; ) {
649 child = child->sibling;
651 /* Place the device on the list of children of it's parent. */
653 child->sibling = dev;
655 dev->bus->children = dev;
663 * @brief Scan a PCI bus.
665 * Determine the existence of devices and bridges on a PCI bus. If there are
666 * bridges on the bus, recursively scan the buses behind the bridges.
668 * This function is the default scan_bus() method for the root device
671 * @param bus pointer to the bus structure
672 * @param min_devfn minimum devfn to look at in the scan usually 0x00
673 * @param max_devfn maximum devfn to look at in the scan usually 0xff
674 * @param max current bus number
676 * @return The maximum bus number found, after scanning all subordinate busses
678 unsigned int pci_scan_bus(struct bus *bus,
679 unsigned min_devfn, unsigned max_devfn,
684 device_t old_devices;
687 printk_debug("PCI: pci_scan_bus for bus %d\n", bus->secondary);
689 old_devices = bus->children;
694 /* probe all devices/functions on this bus with some optimization for
695 * non-existence and single funcion devices
697 for (devfn = min_devfn; devfn <= max_devfn; devfn++) {
701 /* First thing setup the device structure */
702 dev = pci_scan_get_dev(&old_devices, devfn);
704 /* Detect if a device is present */
708 dummy.path.type = DEVICE_PATH_PCI;
709 dummy.path.u.pci.devfn = devfn;
710 id = pci_read_config32(&dummy, PCI_VENDOR_ID);
711 /* some broken boards return 0 if a slot is empty: */
712 if ( (id == 0xffffffff) || (id == 0x00000000) ||
713 (id == 0x0000ffff) || (id == 0xffff0000))
715 printk_spew("PCI: devfn 0x%x, bad id 0x%x\n", devfn, id);
716 if (PCI_FUNC(devfn) == 0x00) {
717 /* if this is a function 0 device and
719 * skip to next device
723 /* This function in a multi function device is
724 * not present, skip to the next function.
728 dev = alloc_dev(bus, &dummy.path);
731 /* Enable/disable the device. Once we have
732 * found the device specific operations this
733 * operations we will disable the device with
736 * This is geared toward devices that have subfunctions
737 * that do not show up by default.
739 * If a device is a stuff option on the motherboard
740 * it may be absent and enable_dev must cope.
743 if (dev->chip_ops && dev->chip_ops->enable_dev)
745 dev->chip_ops->enable_dev(dev);
747 /* Now read the vendor and device id */
748 id = pci_read_config32(dev, PCI_VENDOR_ID);
750 /* If the device does not have a pci id disable it.
751 * Possibly this is because we have already disabled
752 * the device. But this also handles optional devices
753 * that may not always show up.
755 if (id == 0xffffffff || id == 0x00000000 ||
756 id == 0x0000ffff || id == 0xffff0000)
759 printk_info("Disabling static device: %s\n",
765 /* Read the rest of the pci configuration information */
766 hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
767 class = pci_read_config32(dev, PCI_CLASS_REVISION);
769 /* Store the interesting information in the device structure */
770 dev->vendor = id & 0xffff;
771 dev->device = (id >> 16) & 0xffff;
772 dev->hdr_type = hdr_type;
773 /* class code, the upper 3 bytes of PCI_CLASS_REVISION */
774 dev->class = class >> 8;
776 /* Architectural/System devices always need to
779 if ((dev->class >> 16) == PCI_BASE_CLASS_SYSTEM) {
780 dev->command |= PCI_COMMAND_MASTER;
783 /* Look at the vendor and device id, or at least the
784 * header type and class and figure out which set of
785 * configuration methods to use. Unless we already
789 /* Error if we don't have some pci operations for it */
791 printk_err("%s No device operations\n",
796 /* Now run the magic enable/disable sequence for the device */
797 if (dev->ops && dev->ops->enable) {
798 dev->ops->enable(dev);
801 printk_debug("%s [%04x/%04x] %s\n",
803 dev->vendor, dev->device,
804 dev->enabled?"enabled": "disabled");
806 if (PCI_FUNC(devfn) == 0x00 && (hdr_type & 0x80) != 0x80) {
807 /* if this is not a multi function device,
808 * don't waste time probing another function.
809 * Skip to next device.
816 /* For all children that implement scan_bus (i.e. bridges)
817 * scan the bus behind that child.
819 for(child = bus->children; child; child = child->sibling) {
820 if (!child->enabled ||
822 !child->ops->scan_bus)
826 max = child->ops->scan_bus(child, max);
830 * We've scanned the bus and so we know all about what's on
831 * the other side of any bridges that may be on this bus plus
834 * Return how far we've got finding sub-buses.
836 printk_debug("PCI: pci_scan_bus returning with max=%02x\n", max);
842 * @brief Scan a PCI bridge and the buses behind the bridge.
844 * Determine the existence of buses behind the bridge. Set up the bridge
845 * according to the result of the scan.
847 * This function is the default scan_bus() method for PCI bridge devices.
849 * @param dev pointer to the bridge device
850 * @param max the highest bus number assgined up to now
852 * @return The maximum bus number found, after scanning all subordinate busses
854 unsigned int pci_scan_bridge(struct device *dev, unsigned int max)
864 /* Set up the primary, secondary and subordinate bus numbers. We have
865 * no idea how many buses are behind this bridge yet, so we set the
866 * subordinate bus number to 0xff for the moment.
868 bus->secondary = ++max;
869 bus->subordinate = 0xff;
871 /* Clear all status bits and turn off memory, I/O and master enables. */
872 cr = pci_read_config16(dev, PCI_COMMAND);
873 pci_write_config16(dev, PCI_COMMAND, 0x0000);
874 pci_write_config16(dev, PCI_STATUS, 0xffff);
877 * Read the existing primary/secondary/subordinate bus
878 * number configuration.
880 buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
882 /* Configure the bus numbers for this bridge: the configuration
883 * transactions will not be propagated by the bridge if it is not
884 * correctly configured.
887 buses |= (((unsigned int) (dev->bus->secondary) << 0) |
888 ((unsigned int) (bus->secondary) << 8) |
889 ((unsigned int) (bus->subordinate) << 16));
890 pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
892 /* Now we can scan all subordinate buses
893 * i.e. the bus behind the bridge.
895 max = pci_scan_bus(bus, 0x00, 0xff, max);
897 /* We know the number of buses behind this bridge. Set the subordinate
898 * bus number to its real value.
900 bus->subordinate = max;
901 buses = (buses & 0xff00ffff) |
902 ((unsigned int) (bus->subordinate) << 16);
903 pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
904 pci_write_config16(dev, PCI_COMMAND, cr);
906 printk_spew("%s returns max %d\n", __func__, max);
911 Tell the EISA int controller this int must be level triggered
912 THIS IS A KLUDGE -- sorry, this needs to get cleaned up.
914 static void pci_level_irq(unsigned char intNum)
916 unsigned short intBits = inb(0x4d0) | (((unsigned) inb(0x4d1)) << 8);
918 printk_spew("%s: current ints are 0x%x\n", __func__, intBits);
919 intBits |= (1 << intNum);
921 printk_spew("%s: try to set ints 0x%x\n", __func__, intBits);
924 outb((unsigned char) intBits, 0x4d0);
925 outb((unsigned char) (intBits >> 8), 0x4d1);
927 /* this seems like an error but is not ... */
929 if (inb(0x4d0) != (intBits & 0xf)) {
930 printk_err("%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
931 __func__, intBits &0xf, inb(0x4d0));
933 if (inb(0x4d1) != ((intBits >> 8) & 0xf)) {
934 printk_err("%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
935 __func__, (intBits>>8) &0xf, inb(0x4d1));
941 This function assigns IRQs for all functions contained within
942 the indicated device address. If the device does not exist or does
943 not require interrupts then this function has no effect.
945 This function should be called for each PCI slot in your system.
947 pIntAtoD is an array of IRQ #s that are assigned to PINTA through PINTD of
949 The particular irq #s that are passed in depend on the routing inside
950 your southbridge and on your motherboard.
954 void pci_assign_irqs(unsigned bus, unsigned slot,
955 const unsigned char pIntAtoD[4])
961 unsigned char readback;
963 /* Each slot may contain up to eight functions */
964 for (functNum = 0; functNum < 8; functNum++) {
965 pdev = dev_find_slot(bus, (slot << 3) + functNum);
968 line = pci_read_config8(pdev, PCI_INTERRUPT_PIN);
970 // PCI spec says all other values are reserved
971 if ((line >= 1) && (line <= 4)) {
972 irq = pIntAtoD[line - 1];
974 printk_debug("Assigning IRQ %d to %d:%x.%d\n", \
975 irq, bus, slot, functNum);
977 pci_write_config8(pdev, PCI_INTERRUPT_LINE,\
980 readback = pci_read_config8(pdev, PCI_INTERRUPT_LINE);
981 printk_debug(" Readback = %d\n", readback);
983 // Change to level triggered
984 pci_level_irq(pIntAtoD[line - 1]);