src/devices/pci_device.c

   1 /*
   2  *      PCI Bus Services, see include/linux/pci.h for further explanation.
   3  *
   4  *      Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
   5  *      David Mosberger-Tang
   6  *
   7  *      Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
   8  *
   9  *      Copyright 2003 -- Eric Biederman <ebiederman@lnxi.com>
  10  */
  11
  12 #include <console/console.h>
  13 #include <stdlib.h>
  14 #include <stdint.h>
  15 #include <bitops.h>
  16 #include <string.h>
  17 #include <device/device.h>
  18 #include <device/pci.h>
  19 #include <device/pci_ids.h>
  20
  21 /** Given a device and register, read the size of the BAR for that register.
  22  * @param dev       Pointer to the device structure
  23  * @param resource  Pointer to the resource structure
  24  * @param index     Address of the pci configuration register
  25  */
  26 static void pci_get_resource(struct device *dev, struct resource *resource, unsigned long index)
  27 {
  28         uint32_t addr, size, base;
  29         unsigned long type;
  30
  31         /* Initialize the resources to nothing */
  32         resource->base = 0;
  33         resource->size = 0;
  34         resource->align = 0;
  35         resource->gran = 0;
  36         resource->limit = 0;
  37         resource->flags = 0;
  38         resource->index = index;
  39
  40         addr = pci_read_config32(dev, index);
  41         if (addr == 0xffffffffUL)
  42                 return;
  43
  44         /* FIXME: more consideration for 64-bit PCI devices,
  45          * we currently detect their size but otherwise
  46          * treat them as 32-bit resources
  47          */
  48         /* get the size */
  49         pci_write_config32(dev, index, ~0);
  50         size = pci_read_config32(dev,  index);
  51
  52         /* get the minimum value the bar can be set to */
  53         pci_write_config32(dev, index, 0);
  54         base = pci_read_config32(dev, index);
  55
  56         /* restore addr */
  57         pci_write_config32(dev, index, addr);
  58
  59         /*
  60          * some broken hardware has read-only registers that do not
  61          * really size correctly. You can tell this if addr == size
  62          * Example: the acer m7229 has BARs 1-4 normally read-only.
  63          * so BAR1 at offset 0x10 reads 0x1f1. If you size that register
  64          * by writing 0xffffffff to it, it will read back as 0x1f1 -- a
  65          * violation of the spec.
  66          * We catch this case and ignore it by settting size and type to 0.
  67          * This incidentally catches the common case where registers
  68          * read back as 0 for both address and size.
  69          */
  70         if ((addr == size) && (addr == base)) {
  71                 if (size != 0) {
  72                         printk_debug(
  73                                 "PCI: %02x:%02x.%01x register %02x(%08x), read-only ignoring it\n",
  74                                 dev->bus->secondary,
  75                                 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
  76                                 index, addr);
  77                 }
  78                 resource->flags = 0;
  79         }
  80         /* Now compute the actual size, See PCI Spec 6.2.5.1 ...  */
  81         else if (size & PCI_BASE_ADDRESS_SPACE_IO) {
  82                 type = size & (~PCI_BASE_ADDRESS_IO_MASK);
  83                 /* BUG! Top 16 bits can be zero (or not)
  84                  * So set them to 0xffff so they go away ...
  85                  */
  86                 resource->size = (~((size | 0xffff0000) & PCI_BASE_ADDRESS_IO_MASK)) +1;
  87                 resource->align = log2(resource->size);
  88                 resource->gran = resource->align;
  89                 resource->flags = IORESOURCE_IO;
  90                 resource->limit = 0xffff;
  91         }
  92         else {
  93                 /* A Memory mapped base address */
  94                 type = size & (~PCI_BASE_ADDRESS_MEM_MASK);
  95                 resource->size = (~(size &PCI_BASE_ADDRESS_MEM_MASK)) +1;
  96                 resource->align = log2(resource->size);
  97                 resource->gran = resource->align;
  98                 resource->flags = IORESOURCE_MEM;
  99                 if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
 100                         resource->flags |= IORESOURCE_PREFETCH;
 101                 }
 102                 type &= PCI_BASE_ADDRESS_MEM_TYPE_MASK;
 103                 if (type == PCI_BASE_ADDRESS_MEM_TYPE_32) {
 104                         /* 32bit limit */
 105                         resource->limit = 0xffffffffUL;
 106                 }
 107                 else if (type == PCI_BASE_ADDRESS_MEM_TYPE_1M) {
 108                         /* 1MB limit */
 109                         resource->limit = 0x000fffffUL;
 110                 }
 111                 else if (type == PCI_BASE_ADDRESS_MEM_TYPE_64) {
 112                         unsigned long index_hi;
 113                         /* 64bit limit
 114                          * For now just treat this as a 32bit limit
 115                          */
 116                         index_hi = index + 4;
 117                         resource->limit = 0xffffffffUL;
 118                         resource->flags |= IORESOURCE_PCI64;
 119                         addr = pci_read_config32( dev, index_hi);
 120                         /* get the extended size */
 121                         pci_write_config32(dev, index_hi, 0xffffffffUL);
 122                         size = pci_read_config32( dev, index_hi);
 123
 124                         /* get the minimum value the bar can be set to */
 125                         pci_write_config32(dev, index_hi, 0);
 126                         base = pci_read_config32(dev,  index_hi);
 127
 128                         /* restore addr */
 129                         pci_write_config32(dev, index_hi, addr);
 130
 131                         if ((size == 0xffffffff) && (base == 0)) {
 132                                 /* Clear the top half of the bar */
 133                                 pci_write_config32(dev, index_hi, 0);
 134                         }
 135                         else {
 136                                 printk_err("PCI: %02x:%02x.%01x Unable to handle 64-bit address\n",
 137                                         dev->bus->secondary,
 138                                         PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
 139                                 resource->flags = IORESOURCE_PCI64;
 140                         }
 141                 }
 142                 else {
 143                         /* Invalid value */
 144                         resource->flags = 0;
 145                 }
 146         }
 147         /* dev->size holds the flags... */
 148         return;
 149 }
 150
 151 /** Read the base address registers for a given device.
 152  * @param dev Pointer to the dev structure
 153  * @param howmany How many registers to read (6 for device, 2 for bridge)
 154  */
 155 static void pci_read_bases(struct device *dev, unsigned int howmany)
 156 {
 157         unsigned int reg;
 158         unsigned long index;
 159
 160         reg = dev->resources;
 161         for(index = PCI_BASE_ADDRESS_0;
 162             (reg < MAX_RESOURCES) && (index < PCI_BASE_ADDRESS_0 + (howmany << 2)); ) {
 163                 struct resource *resource;
 164                 resource = &dev->resource[reg];
 165                 pci_get_resource(dev, resource, index);
 166                 reg += (resource->flags & (IORESOURCE_IO | IORESOURCE_MEM))? 1:0;
 167                 index += (resource->flags & IORESOURCE_PCI64)?8:4;
 168         }
 169         dev->resources = reg;
 170 }
 171
 172
 173 static void pci_bridge_read_bases(struct device *dev)
 174 {
 175         unsigned int reg = dev->resources;
 176
 177         /* FIXME handle bridges without some of the optional resources */
 178
 179         /* Initialize the io space constraints on the current bus */
 180         dev->resource[reg].base  = 0;
 181         dev->resource[reg].size  = 0;
 182         dev->resource[reg].align = log2(PCI_IO_BRIDGE_ALIGN);
 183         dev->resource[reg].gran  = log2(PCI_IO_BRIDGE_ALIGN);
 184         dev->resource[reg].limit = 0xffffUL;
 185         dev->resource[reg].flags = IORESOURCE_IO | IORESOURCE_PCI_BRIDGE;
 186         dev->resource[reg].index = PCI_IO_BASE;
 187         compute_allocate_resource(dev, &dev->resource[reg],
 188                 IORESOURCE_IO, IORESOURCE_IO);
 189         reg++;
 190
 191         /* Initiliaze the prefetchable memory constraints on the current bus */
 192         dev->resource[reg].base = 0;
 193         dev->resource[reg].size = 0;
 194         dev->resource[reg].align = log2(PCI_MEM_BRIDGE_ALIGN);
 195         dev->resource[reg].gran  = log2(PCI_MEM_BRIDGE_ALIGN);
 196         dev->resource[reg].limit = 0xffffffffUL;
 197         dev->resource[reg].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_PCI_BRIDGE;
 198         dev->resource[reg].index = PCI_PREF_MEMORY_BASE;
 199         compute_allocate_resource(dev, &dev->resource[reg],
 200                 IORESOURCE_MEM | IORESOURCE_PREFETCH,
 201                 IORESOURCE_MEM | IORESOURCE_PREFETCH);
 202         reg++;
 203
 204         /* Initialize the memory resources on the current bus */
 205         dev->resource[reg].base = 0;
 206         dev->resource[reg].size = 0;
 207         dev->resource[reg].align = log2(PCI_MEM_BRIDGE_ALIGN);
 208         dev->resource[reg].gran  = log2(PCI_MEM_BRIDGE_ALIGN);
 209         dev->resource[reg].limit = 0xffffffffUL;
 210         dev->resource[reg].flags = IORESOURCE_MEM | IORESOURCE_PCI_BRIDGE;
 211         dev->resource[reg].index = PCI_MEMORY_BASE;
 212         compute_allocate_resource(dev, &dev->resource[reg],
 213                 IORESOURCE_MEM | IORESOURCE_PREFETCH,
 214                 IORESOURCE_MEM);
 215         reg++;
 216
 217         dev->resources = reg;
 218 }
 219
 220
 221 void pci_dev_read_resources(struct device *dev)
 222 {
 223         uint32_t addr;
 224         dev->resources = 0;
 225         memset(&dev->resource[0], 0, sizeof(dev->resource));
 226         pci_read_bases(dev, 6);
 227         addr = pci_read_config32(dev, PCI_ROM_ADDRESS);
 228         dev->rom_address = (addr == 0xffffffff)? 0 : addr;
 229 }
 230
 231 void pci_bus_read_resources(struct device *dev)
 232 {
 233         uint32_t addr;
 234         dev->resources = 0;
 235         memset(&dev->resource[0], 0, sizeof(dev->resource));
 236         pci_bridge_read_bases(dev);
 237         pci_read_bases(dev, 2);
 238
 239         addr = pci_read_config32(dev, PCI_ROM_ADDRESS1);
 240         dev->rom_address = (addr == 0xffffffff)? 0 : addr;
 241
 242 }
 243
 244
 245 static void pci_set_resource(struct device *dev, struct resource *resource)
 246 {
 247         unsigned long base, limit;
 248         unsigned long bridge_align = PCI_MEM_BRIDGE_ALIGN;
 249         unsigned char buf[10];
 250
 251         /* Make certain the resource has actually been set */
 252         if (!(resource->flags & IORESOURCE_SET)) {
 253 #if 1
 254                 printk_err("ERROR: %02x:%02x.%01x %02x not allocated\n",
 255                         dev->bus->secondary,
 256                         PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
 257                         resource->index);
 258 #endif
 259                 return;
 260         }
 261
 262         /* Only handle PCI memory and IO resources for now */
 263         if (!(resource->flags & (IORESOURCE_MEM |IORESOURCE_IO)))
 264                 return;
 265
 266         if (resource->flags & IORESOURCE_MEM) {
 267                 dev->command |= PCI_COMMAND_MEMORY;
 268                 bridge_align = PCI_MEM_BRIDGE_ALIGN;
 269         }
 270         if (resource->flags & IORESOURCE_IO) {
 271                 dev->command |= PCI_COMMAND_IO;
 272                 bridge_align = PCI_IO_BRIDGE_ALIGN;
 273         }
 274         if (resource->flags & IORESOURCE_PCI_BRIDGE) {
 275                 dev->command |= PCI_COMMAND_MASTER;
 276         }
 277         /* Get the base address */
 278         base = resource->base;
 279
 280         /* Get the limit (rounded up) */
 281         limit = base + ((resource->size + bridge_align - 1UL) & ~(bridge_align -1)) -1UL;
 282
 283         if (!(resource->flags & IORESOURCE_PCI_BRIDGE)) {
 284                 /*
 285                  * some chipsets allow us to set/clear the IO bit.
 286                  * (e.g. VIA 82c686a.) So set it to be safe)
 287                  */
 288                 limit = base + resource->size -1;
 289                 if (resource->flags & IORESOURCE_IO) {
 290                         base |= PCI_BASE_ADDRESS_SPACE_IO;
 291                 }
 292                 pci_write_config32(dev, resource->index, base & 0xffffffff);
 293                 if (resource->flags & IORESOURCE_PCI64) {
 294                         /* FIXME handle real 64bit base addresses */
 295                         pci_write_config32(dev, resource->index + 4, 0);
 296                 }
 297         }
 298         else if (resource->index == PCI_IO_BASE) {
 299                 /* set the IO ranges
 300                  * WARNING: we don't really do 32-bit addressing for IO yet!
 301                  */
 302                 compute_allocate_resource(dev, resource,
 303                         IORESOURCE_IO, IORESOURCE_IO);
 304                 pci_write_config8(dev, PCI_IO_BASE,  base >> 8);
 305                 pci_write_config8(dev, PCI_IO_LIMIT, limit >> 8);
 306                 pci_write_config16(dev, PCI_IO_BASE_UPPER16, 0);
 307                 pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, 0);
 308         }
 309         else if (resource->index == PCI_MEMORY_BASE) {
 310                 /* set the memory range
 311                  */
 312                 compute_allocate_resource(dev, resource,
 313                         IORESOURCE_MEM | IORESOURCE_PREFETCH,
 314                         IORESOURCE_MEM);
 315                 pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);
 316                 pci_write_config16(dev, PCI_MEMORY_LIMIT, limit >> 16);
 317         }
 318         else if (resource->index == PCI_PREF_MEMORY_BASE) {
 319                 /* set the prefetchable memory range
 320                  * WARNING: we don't really do 64-bit addressing for prefetchable memory yet!
 321                  */
 322                 compute_allocate_resource(dev, resource,
 323                         IORESOURCE_MEM | IORESOURCE_PREFETCH,
 324                         IORESOURCE_MEM | IORESOURCE_PREFETCH);
 325                 pci_write_config16(dev, PCI_PREF_MEMORY_BASE,  base >> 16);
 326                 pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, limit >> 16);
 327                 pci_write_config32(dev, PCI_PREF_BASE_UPPER32, 0);
 328                 pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, 0);
 329         }
 330         else {
 331                 printk_err("ERROR: invalid resource->index %x\n",
 332                         resource->index);
 333         }
 334         buf[0] = '\0';
 335         if (resource->flags & IORESOURCE_PCI_BRIDGE) {
 336                 sprintf(buf, "bus %d ", dev->secondary);
 337         }
 338
 339         printk_debug(
 340                 "PCI: %02x:%02x.%01x %02x <- [0x%08lx - 0x%08lx] %s%s\n",
 341                 dev->bus->secondary,
 342                 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
 343                 resource->index,
 344                 resource->base, limit,
 345                 buf,
 346                 (resource->flags & IORESOURCE_IO)? "io":
 347                 (resource->flags & IORESOURCE_PREFETCH)? "prefmem": "mem");
 348         return;
 349 }
 350
 351 void pci_dev_set_resources(struct device *dev)
 352 {
 353         struct resource *resource, *last;
 354         uint8_t line;
 355
 356         last = &dev->resource[dev->resources];
 357
 358         for(resource = &dev->resource[0]; resource < last; resource++) {
 359                 pci_set_resource(dev, resource);
 360         }
 361         if (dev->children) {
 362                 assign_resources(dev);
 363         }
 364
 365         /* set a default latency timer */
 366         pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
 367
 368         /* set a default secondary latency timer */
 369         if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
 370                 pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
 371         }
 372
 373         /* zero the irq settings */
 374         line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
 375         if (line) {
 376                 pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
 377         }
 378         /* set the cache line size, so far 64 bytes is good for everyone */
 379         pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
 380 }
 381
 382 struct device_operations default_pci_ops_dev = {
 383         .read_resources = pci_dev_read_resources,
 384         .set_resources = pci_dev_set_resources,
 385         .init = 0,
 386         .scan_bus = 0,
 387 };
 388 struct device_operations default_pci_ops_bus = {
 389         .read_resources = pci_bus_read_resources,
 390         .set_resources = pci_dev_set_resources,
 391         .init = 0,
 392         .scan_bus = pci_scan_bridge,
 393 };
 394 static void set_pci_ops(struct device *dev)
 395 {
 396         struct pci_driver *driver;
 397         if (dev->ops) {
 398                 return;
 399         }
 400         /* Look through the list of setup drivers and find one for
 401          * this pci device
 402          */
 403         for(driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) {
 404                 if ((driver->vendor == dev->vendor) &&
 405                         (driver->device == dev->device)) {
 406                         dev->ops = driver->ops;
 407 #if 1
 408                         printk_debug("PCI: %02x:%02x.%01x [%04x/%04x] ops\n",
 409                                 dev->bus->secondary,
 410                                 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
 411                                 driver->vendor, driver->device
 412                                 );
 413 #endif
 414                         return;
 415                 }
 416         }
 417         /* If I don't have a specific driver use the default operations */
 418         switch(dev->hdr_type & 0x7f) {  /* header type */
 419         case PCI_HEADER_TYPE_NORMAL:    /* standard header */
 420                 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
 421                         goto bad;
 422                 dev->ops = &default_pci_ops_dev;
 423                 break;
 424         case PCI_HEADER_TYPE_BRIDGE:
 425                 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
 426                         goto bad;
 427                 dev->ops = &default_pci_ops_bus;
 428                 break;
 429         default:
 430         bad:
 431                 printk_err("PCI: %02x:%02x.%01x [%04x/%04x/%06x] has unknown header "
 432                         "type %02x, ignoring.\n",
 433                         dev->bus->secondary,
 434                         PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
 435                         dev->vendor, dev->device,
 436                         dev->class >> 8, dev->hdr_type);
 437         }
 438         return;
 439 }
 440
 441 /**
 442  * Given a bus and a devfn number, find the device structure
 443  * @param bus The bus structure
 444  * @param devfn a device/function number
 445  * @return pointer to the device structure
 446  */
 447 static struct device *pci_scan_get_dev(struct device **list, unsigned int devfn)
 448 {
 449         struct device *dev = 0;
 450         for(; *list; list = &(*list)->sibling) {
 451                 if ((*list)->devfn == devfn) {
 452                         /* Unlink from the list */
 453                         dev = *list;
 454                         *list = (*list)->sibling;
 455                         dev->sibling = 0;
 456                         break;
 457                 }
 458         }
 459         return dev;
 460 }
 461
 462
 463 #define HYPERTRANSPORT_SUPPORT 1
 464 /** Scan the pci bus devices and bridges.
 465  * @param pci_bus pointer to the bus structure
 466  * @param max current bus number
 467  * @return The maximum bus number found, after scanning all subordinate busses
 468  */
 469 unsigned int pci_scan_bus(struct device *bus, unsigned int max)
 470 {
 471         unsigned int devfn;
 472         struct device *dev, **bus_last;
 473         struct device *old_devices;
 474         struct device *child;
 475 #if HYPERTRANSPORT_SUPPORT
 476         unsigned next_unitid, last_unitid, previous_unitid;
 477         int reset_needed;
 478 #endif
 479
 480         printk_debug("PCI: pci_scan_bus for bus %d\n", bus->secondary);
 481
 482         old_devices = bus->children;
 483         bus->children = 0;
 484         bus_last = &bus->children;
 485
 486         post_code(0x24);
 487
 488
 489 #if HYPERTRANSPORT_SUPPORT
 490         /* Spin through the devices and collapse any early
 491          * hypertransport enumeration.
 492          */
 493         for(devfn = 0; devfn <= 0xff; devfn += 8) {
 494                 struct device dummy;
 495                 uint32_t id;
 496                 uint8_t hdr_type, pos;
 497                 dummy.bus = bus;
 498                 dummy.devfn = devfn;
 499                 id = pci_read_config32(&dummy, PCI_VENDOR_ID);
 500                 if (id == 0xffffffff || id == 0x00000000 ||
 501                         id == 0x0000ffff || id == 0xffff0000) {
 502                         continue;
 503                 }
 504                 hdr_type = pci_read_config8(&dummy, PCI_HEADER_TYPE);
 505                 pos = 0;
 506                 switch(hdr_type & 0x7f) {
 507                 case PCI_HEADER_TYPE_NORMAL:
 508                 case PCI_HEADER_TYPE_BRIDGE:
 509                         pos = PCI_CAPABILITY_LIST;
 510                         break;
 511                 }
 512                 if (pos > PCI_CAP_LIST_NEXT) {
 513                         pos = pci_read_config8(&dummy, pos);
 514                 }
 515                 while(pos != 0) {
 516                         uint8_t cap;
 517                         cap = pci_read_config8(&dummy, pos + PCI_CAP_LIST_ID);
 518                         printk_debug("Capability: 0x%02x @ 0x%02x\n", cap, pos);
 519                         if (cap == PCI_CAP_ID_HT) {
 520                                 uint16_t flags;
 521                                 flags = pci_read_config16(&dummy, pos + PCI_CAP_FLAGS);
 522                                 printk_debug("flags: 0x%04x\n", (unsigned)flags);
 523                                 if ((flags >> 13) == 0) {
 524                                         /* Clear the unitid */
 525                                         flags &= ~0x1f;
 526                                         pci_write_config16(&dummy, pos + PCI_CAP_FLAGS, flags);
 527                                         break;
 528                                 }
 529                         }
 530                         pos = pci_read_config8(&dummy, pos + PCI_CAP_LIST_NEXT);
 531                 }
 532         }
 533         /* If present assign unitid to a hypertransport chain */
 534         last_unitid = 0;
 535         next_unitid = 1;
 536         do {
 537                 struct device dummy;
 538                 uint32_t id;
 539                 uint8_t hdr_type, pos, previous_pos;
 540
 541                 previous_unitid = last_unitid;
 542                 last_unitid = next_unitid;
 543
 544                 /* Read the next unassigned device off the stack */
 545                 dummy.bus   = bus;
 546                 dummy.devfn = 0;
 547                 id = pci_read_config32(&dummy, PCI_VENDOR_ID);
 548                 /* If the chain is enumerated quit */
 549                 if (id == 0xffffffff || id == 0x00000000 ||
 550                         id == 0x0000ffff || id == 0xffff0000) {
 551                         break;
 552                 }
 553                 hdr_type = pci_read_config8(&dummy, PCI_HEADER_TYPE);
 554                 pos = 0;
 555                 switch(hdr_type & 0x7f) {
 556                 case PCI_HEADER_TYPE_NORMAL:
 557                 case PCI_HEADER_TYPE_BRIDGE:
 558                         pos = PCI_CAPABILITY_LIST;
 559                         break;
 560                 }
 561                 if (pos > PCI_CAP_LIST_NEXT) {
 562                         pos = pci_read_config8(&dummy, pos);
 563                 }
 564                 while(pos != 0) {   /* loop through the linked list */
 565                         uint8_t cap;
 566                         cap = pci_read_config8(&dummy, pos + PCI_CAP_LIST_ID);
 567                         printk_debug("Capability: 0x%02x @ 0x%02x\n", cap, pos);
 568                         if (cap == PCI_CAP_ID_HT) {
 569                                 uint16_t flags;
 570                                 uint16_t links;
 571                                 flags = pci_read_config16(&dummy, pos + PCI_CAP_FLAGS);
 572                                 printk_debug("flags: 0x%04x\n", (unsigned)flags);
 573                                 if ((flags >> 13) == 0) {  /* Entry is a Slave secondary */
 574                                         struct device last, previous;
 575                                         unsigned count;
 576                                         unsigned width;
 577                                         flags &= ~0x1f; /* mask out base unit ID */
 578                                         flags |= next_unitid & 0x1f; /* assign ID */
 579                                         count = (flags >> 5) & 0x1f; /* get unit count */
 580                                         printk_debug("unitid: 0x%02x, count: 0x%02x\n",
 581                                                 next_unitid, count);
 582                                         pci_write_config16(&dummy, pos + PCI_CAP_FLAGS, flags);
 583                                         next_unitid += count;
 584
 585                                         if (previous_unitid == 0) { /* the link is back to the host */
 586                                                 /* calculate the previous pos for the host */
 587                                                 previous_pos = 0x80;
 588                                                 previous.bus = 0;
 589                                                 previous.devfn = 0x18 << 3;
 590 #warning "FIXME we should not hard code this!"
 591                                         } else {
 592                                                 previous.bus = bus;
 593                                                 previous.devfn = previous_unitid << 3;
 594                                         }
 595                                         last.bus = bus;
 596                                         last.devfn = last_unitid << 3;
 597                                         /* Set link width and frequency */
 598                                         flags = pci_read_config16(&last, pos + PCI_HT_CAP_SLAVE_FREQ_CAP0);
 599                                         cap = pci_read_config8(&last, pos + PCI_HT_CAP_SLAVE_WIDTH0);
 600                                         if(previous_unitid == 0) { /* the link is back to the host */
 601                                                 links = pci_read_config16(&previous,
 602                                                                 previous_pos + PCI_HT_CAP_HOST_FREQ_CAP);
 603                                                 width = pci_read_config8(&previous,
 604                                                                 previous_pos + PCI_HT_CAP_HOST_WIDTH);
 605                                         }
 606                                         else { /* The link is back up the chain */
 607                                                 links = pci_read_config16(&previous,
 608                                                                 previous_pos + PCI_HT_CAP_SLAVE_FREQ_CAP1);
 609                                                 width = pci_read_config8(&previous,
 610                                                                 previous_pos + PCI_HT_CAP_SLAVE_WIDTH1);
 611                                         }
 612                                         /* Calculate the highest possible frequency */
 613                                         links &= flags;
 614                                         for(flags = 0x40, count = 6; count; count--, flags >>= 1) {
 615                                                 if(flags & links) break;
 616                                         }
 617                                         /* Calculate the highest width */
 618                                         width &= cap;
 619                                         /* set the present device */
 620                                         if(count != pci_read_config8(&last, pos + PCI_HT_CAP_HOST_FREQ)) {
 621                                                 pci_write_config8(&last, pos + PCI_HT_CAP_HOST_FREQ, count);
 622                                                 reset_needed = 1;
 623                                         }
 624                                         if(width != pci_read_config8(&last, pos + PCI_HT_CAP_SLAVE_WIDTH0 + 1)) {
 625                                                 pci_write_config8(&last,
 626                                                                                 pos + PCI_HT_CAP_SLAVE_WIDTH0 + 1, width);
 627                                                 reset_needed = 1;
 628                                         }
 629
 630                                         /* set the upstream device */
 631                                         if(previous_unitid == 0) { /* the link is back to the host */
 632                                                 cap = pci_read_config8(&previous, previous_pos + PCI_HT_CAP_HOST_FREQ);
 633                                                 cap &= 0x0f;
 634                                                 if(count != cap) {
 635                                                         pci_write_config8(&previous,
 636                                                                         previous_pos + PCI_HT_CAP_HOST_FREQ, count);
 637                                                         reset_needed = 1;
 638                                                 }
 639                                                 cap = pci_read_config8(&previous, previous_pos + PCI_HT_CAP_HOST_WIDTH + 1);
 640                                                 if(width != cap) {
 641                                                         pci_write_config8(&previous,
 642                                                                         previous_pos + PCI_HT_CAP_HOST_WIDTH + 1, width);
 643                                                         reset_needed = 1;
 644                                                 }
 645                                         }
 646                                         else { /* The link is back up the chain */
 647                                                 cap = pci_read_config8(&previous,
 648                                                                         previous_pos + PCI_HT_CAP_SLAVE_FREQ1);
 649                                                 cap &= 0x0f;
 650                                                 if(count != cap) {
 651                                                         pci_write_config8(&previous,
 652                                                                 previous_pos + PCI_HT_CAP_SLAVE_FREQ1, count);
 653                                                         reset_needed = 1;
 654                                                 }
 655                                                 cap = pci_read_config8(&previous,
 656                                                                         previous_pos + PCI_HT_CAP_SLAVE_WIDTH1 + 1);
 657                                                 if(width != cap) {
 658                                                         pci_write_config8(&previous,
 659                                                                 previous_pos + PCI_HT_CAP_SLAVE_WIDTH1, width);
 660                                                         reset_needed = 1;
 661                                                 }
 662                                         }
 663                                         break;
 664                                 }
 665                         }
 666                         pos = pci_read_config8(&dummy, pos + PCI_CAP_LIST_NEXT);
 667                 }
 668                 previous_pos = pos;
 669         } while((last_unitid != next_unitid) && (next_unitid <= 0x1f));
 670 #endif /* HYPERTRANSPORT_SUPPORT */
 671
 672         /* probe all devices on this bus with some optimization for non-existance and
 673            single funcion devices */
 674         for (devfn = 0; devfn <= 0xff; devfn++) {
 675                 struct device dummy;
 676                 uint32_t id, class;
 677                 uint8_t cmd, tmp, hdr_type;
 678
 679                 /* First thing setup the device structure */
 680                 dev = pci_scan_get_dev(&old_devices, devfn);
 681
 682                 dummy.bus = bus;
 683                 dummy.devfn = devfn;
 684                 id = pci_read_config32(&dummy, PCI_VENDOR_ID);
 685                 /* some broken boards return 0 if a slot is empty: */
 686                 if (!dev &&
 687                         (id == 0xffffffff || id == 0x00000000 ||
 688                          id == 0x0000ffff || id == 0xffff0000)) {
 689                         printk_spew("PCI: devfn 0x%x, bad id 0x%x\n", devfn, id);
 690                         if (PCI_FUNC(devfn) == 0x00) {
 691                                 /* if this is a function 0 device and it is not present,
 692                                    skip to next device */
 693                                 devfn += 0x07;
 694                         }
 695                         /* multi function device, skip to next function */
 696                         continue;
 697                 }
 698                 hdr_type = pci_read_config8(&dummy, PCI_HEADER_TYPE);
 699                 class = pci_read_config32(&dummy, PCI_CLASS_REVISION);
 700
 701                 if (!dev) {
 702                         if ((dev = malloc(sizeof(*dev))) == 0) {
 703                                 printk_err("PCI: out of memory.\n");
 704                                 continue;
 705                         }
 706                         memset(dev, 0, sizeof(*dev));
 707                         dev->bus = bus;
 708                         dev->devfn = devfn;
 709                         dev->vendor = id & 0xffff;
 710                         dev->device = (id >> 16) & 0xffff;
 711                         dev->hdr_type = hdr_type;
 712                         /* class code, the upper 3 bytes of PCI_CLASS_REVISION */
 713                         dev->class = class >> 8;
 714
 715                         /* If we don't have prior information about this device enable it */
 716                         dev->enable = 1;
 717                 }
 718
 719                 /* Look at the vendor and device id, or at least the
 720                  * header type and class and figure out which set of configuration
 721                  * methods to use.
 722                  */
 723                 set_pci_ops(dev);
 724                 /* Kill the device if we don't have some pci operations for it */
 725                 if (!dev->ops) {
 726                         free(dev);
 727                         continue;
 728                 }
 729
 730                 /* Now run the magic enable/disable sequence for the device */
 731                 if (dev->ops && dev->ops->enable) {
 732                         dev->ops->enable(dev);
 733                 }
 734
 735                 printk_debug("PCI: %02x:%02x.%01x [%04x/%04x] %s\n",
 736                         bus->secondary, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
 737                         dev->vendor, dev->device,
 738                         dev->enable?"enabled": "disabled");
 739
 740                 /* Put it into the global device chain. */
 741                 append_device(dev);
 742
 743                 /* Now insert it into the list of devices held by the parent bus. */
 744                 *bus_last = dev;
 745                 bus_last = &dev->sibling;
 746
 747                 if (PCI_FUNC(devfn) == 0x00 && (hdr_type & 0x80) != 0x80) {
 748                         /* if this is not a multi function device, don't waste time probe
 749                            another function. Skip to next device. */
 750                         devfn += 0x07;
 751                 }
 752         }
 753         post_code(0x25);
 754
 755         for(child = bus->children; child; child = child->sibling) {
 756                 if (!child->ops->scan_bus)
 757                         continue;
 758                 max = child->ops->scan_bus(child, max);
 759
 760         }
 761         /*
 762          * We've scanned the bus and so we know all about what's on
 763          * the other side of any bridges that may be on this bus plus
 764          * any devices.
 765          *
 766          * Return how far we've got finding sub-buses.
 767          */
 768         printk_debug("PCI: pci_scan_bus returning with max=%02x\n", max);
 769         post_code(0x55);
 770         return max;
 771 }
 772
 773 /** Scan the bus, first for bridges and next for devices.
 774  * @param pci_bus pointer to the bus structure
 775  * @return The maximum bus number found, after scanning all subordinate busses
 776  */
 777 unsigned int pci_scan_bridge(struct device *bus, unsigned int max)
 778 {
 779         uint32_t buses;
 780         uint16_t cr;
 781         /* Set up the primary, secondary and subordinate bus numbers. We have
 782          * no idea how many buses are behind this bridge yet, so we set the
 783          * subordinate bus number to 0xff for the moment
 784          */
 785         bus->secondary = ++max;
 786         bus->subordinate = 0xff;
 787
 788         /* Clear all status bits and turn off memory, I/O and master enables. */
 789         cr = pci_read_config16(bus, PCI_COMMAND);
 790         pci_write_config16(bus, PCI_COMMAND, 0x0000);
 791         pci_write_config16(bus, PCI_STATUS, 0xffff);
 792
 793         /*
 794          * Read the existing primary/secondary/subordinate bus
 795          * number configuration.
 796          */
 797         buses = pci_read_config32(bus, PCI_PRIMARY_BUS);
 798
 799         /* Configure the bus numbers for this bridge: the configuration
 800          * transactions will not be propagated by the bridge if it is not
 801          * correctly configured
 802          */
 803         buses &= 0xff000000;
 804         buses |= (((unsigned int) (bus->bus->secondary) << 0) |
 805                 ((unsigned int) (bus->secondary) << 8) |
 806                 ((unsigned int) (bus->subordinate) << 16));
 807         pci_write_config32(bus, PCI_PRIMARY_BUS, buses);
 808
 809         /* Now we can scan all subordinate buses i.e. the bus hehind the bridge */
 810         max = pci_scan_bus(bus, max);
 811
 812         /* We know the number of buses behind this bridge. Set the subordinate
 813          *  bus number to its real value
 814          */
 815         bus->subordinate = max;
 816         buses = (buses & 0xff00ffff) |
 817                 ((unsigned int) (bus->subordinate) << 16);
 818         pci_write_config32(bus, PCI_PRIMARY_BUS, buses);
 819         pci_write_config16(bus, PCI_COMMAND, cr);
 820
 821         return max;
 822 }
 823
 824
 825 static void pci_root_read_resources(struct device *bus)
 826 {
 827         int res = 0;
 828         /* Initialize the system wide io space constraints */
 829         bus->resource[res].base  = 0x400;
 830         bus->resource[res].size  = 0;
 831         bus->resource[res].align = 0;
 832         bus->resource[res].gran  = 0;
 833         bus->resource[res].limit = 0xffffUL;
 834         bus->resource[res].flags = IORESOURCE_IO;
 835         bus->resource[res].index = PCI_IO_BASE;
 836         compute_allocate_resource(bus, &bus->resource[res],
 837                 IORESOURCE_IO, IORESOURCE_IO);
 838         res++;
 839
 840         /* Initialize the system wide memory resources constraints */
 841         bus->resource[res].base  = 0;
 842         bus->resource[res].size  = 0;
 843         bus->resource[res].align = 0;
 844         bus->resource[res].gran  = 0;
 845         bus->resource[res].limit = 0xffffffffUL;
 846         bus->resource[res].flags = IORESOURCE_MEM;
 847         bus->resource[res].index = PCI_MEMORY_BASE;
 848         compute_allocate_resource(bus, &bus->resource[res],
 849                 IORESOURCE_MEM, IORESOURCE_MEM);
 850         res++;
 851
 852         bus->resources = res;
 853 }
 854 static void pci_root_set_resources(struct device *bus)
 855 {
 856         compute_allocate_resource(bus,
 857                 &bus->resource[0], IORESOURCE_IO, IORESOURCE_IO);
 858         compute_allocate_resource(bus,
 859                 &bus->resource[1], IORESOURCE_MEM, IORESOURCE_MEM);
 860         assign_resources(bus);
 861 }
 862
 863 struct device_operations default_pci_ops_root = {
 864         .read_resources = pci_root_read_resources,
 865         .set_resources = pci_root_set_resources,
 866         .init = 0,
 867         .scan_bus = pci_scan_bus,
 868 };
 869