2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
9 * Copyright 2003 -- Eric Biederman <ebiederman@lnxi.com>
12 #include <console/console.h>
18 #include <device/device.h>
19 #include <device/pci.h>
20 #include <device/pci_ids.h>
21 #include <part/hard_reset.h>
22 #include <part/fallback_boot.h>
25 static uint8_t pci_moving_config8(struct device *dev, unsigned reg)
27 uint8_t value, ones, zeroes;
28 value = pci_read_config8(dev, reg);
30 pci_write_config8(dev, reg, 0xff);
31 ones = pci_read_config8(dev, reg);
33 pci_write_config8(dev, reg, 0x00);
34 zeroes = pci_read_config8(dev, reg);
36 pci_write_config8(dev, reg, value);
41 static uint16_t pci_moving_config16(struct device *dev, unsigned reg)
43 uint16_t value, ones, zeroes;
44 value = pci_read_config16(dev, reg);
46 pci_write_config16(dev, reg, 0xffff);
47 ones = pci_read_config16(dev, reg);
49 pci_write_config16(dev, reg, 0x0000);
50 zeroes = pci_read_config16(dev, reg);
52 pci_write_config16(dev, reg, value);
57 static uint32_t pci_moving_config32(struct device *dev, unsigned reg)
59 uint32_t value, ones, zeroes;
60 value = pci_read_config32(dev, reg);
62 pci_write_config32(dev, reg, 0xffffffff);
63 ones = pci_read_config32(dev, reg);
65 pci_write_config32(dev, reg, 0x00000000);
66 zeroes = pci_read_config32(dev, reg);
68 pci_write_config32(dev, reg, value);
73 unsigned pci_find_capability(device_t dev, unsigned cap)
77 switch(dev->hdr_type & 0x7f) {
78 case PCI_HEADER_TYPE_NORMAL:
79 case PCI_HEADER_TYPE_BRIDGE:
80 pos = PCI_CAPABILITY_LIST;
83 if (pos > PCI_CAP_LIST_NEXT) {
84 pos = pci_read_config8(dev, pos);
86 while (pos != 0) { /* loop through the linked list */
88 this_cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID);
89 if (this_cap == cap) {
96 /** Given a device and register, read the size of the BAR for that register.
97 * @param dev Pointer to the device structure
98 * @param resource Pointer to the resource structure
99 * @param index Address of the pci configuration register
101 struct resource *pci_get_resource(struct device *dev, unsigned long index)
103 struct resource *resource;
104 unsigned long value, attr;
105 resource_t moving, limit;
107 /* Initialize the resources to nothing */
108 resource = new_resource(dev, index);
110 /* Get the initial value */
111 value = pci_read_config32(dev, index);
113 /* See which bits move */
114 moving = pci_moving_config32(dev, index);
116 /* Initialize attr to the bits that do not move */
117 attr = value & ~moving;
119 /* If it is a 64bit resource look at the high half as well */
120 if (((attr & PCI_BASE_ADDRESS_SPACE_IO) == 0) &&
121 ((attr & PCI_BASE_ADDRESS_MEM_LIMIT_MASK) == PCI_BASE_ADDRESS_MEM_LIMIT_64))
123 /* Find the high bits that move */
124 moving |= ((resource_t)pci_moving_config32(dev, index + 4)) << 32;
126 /* Find the resource constraints.
128 * Start by finding the bits that move. From there:
129 * - Size is the least significant bit of the bits that move.
130 * - Limit is all of the bits that move plus all of the lower bits.
131 * See PCI Spec 6.2.5.1 ...
136 resource->align = resource->gran = 0;
137 while (!(moving & resource->size)) {
138 resource->size <<= 1;
139 resource->align += 1;
142 resource->limit = limit = moving | (resource->size - 1);
145 * some broken hardware has read-only registers that do not
146 * really size correctly.
147 * Example: the acer m7229 has BARs 1-4 normally read-only.
148 * so BAR1 at offset 0x10 reads 0x1f1. If you size that register
149 * by writing 0xffffffff to it, it will read back as 0x1f1 -- a
150 * violation of the spec.
151 * We catch this case and ignore it by observing which bits move,
152 * This also catches the common case unimplemented registers
153 * that always read back as 0.
157 printk_debug("%s register %02x(%08x), read-only ignoring it\n",
158 dev_path(dev), index, value);
161 } else if (attr & PCI_BASE_ADDRESS_SPACE_IO) {
162 /* An I/O mapped base address */
163 attr &= PCI_BASE_ADDRESS_IO_ATTR_MASK;
164 resource->flags |= IORESOURCE_IO;
165 /* I don't want to deal with 32bit I/O resources */
166 resource->limit = 0xffff;
168 /* A Memory mapped base address */
169 attr &= PCI_BASE_ADDRESS_MEM_ATTR_MASK;
170 resource->flags |= IORESOURCE_MEM;
171 if (attr & PCI_BASE_ADDRESS_MEM_PREFETCH) {
172 resource->flags |= IORESOURCE_PREFETCH;
174 attr &= PCI_BASE_ADDRESS_MEM_LIMIT_MASK;
175 if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_32) {
177 resource->limit = 0xffffffffUL;
178 } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_1M) {
180 resource->limit = 0x000fffffUL;
181 } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_64) {
183 resource->limit = 0xffffffffffffffffULL;
184 resource->flags |= IORESOURCE_PCI64;
190 /* Don't let the limit exceed which bits can move */
191 if (resource->limit > limit) {
192 resource->limit = limit;
195 if (resource->flags) {
196 printk_debug("%s %02x ->",
197 dev_path(dev), resource->index);
198 printk_debug(" value: 0x%08Lx zeroes: 0x%08Lx ones: 0x%08Lx attr: %08lx\n",
199 value, zeroes, ones, attr);
201 "%s %02x -> size: 0x%08Lx max: 0x%08Lx %s%s\n ",
204 resource->size, resource->limit,
205 (resource->flags == 0) ? "unused":
206 (resource->flags & IORESOURCE_IO)? "io":
207 (resource->flags & IORESOURCE_PREFETCH)? "prefmem": "mem",
208 (resource->flags & IORESOURCE_PCI64)?"64":"");
215 static void pci_get_rom_resource(struct device *dev, unsigned long index)
217 struct resource *resource;
219 resource_t moving, limit;
221 /* Initialize the resources to nothing */
222 resource = new_resource(dev, index);
224 /* Get the initial value */
225 value = pci_read_config32(dev, index);
227 /* See which bits move */
228 moving = pci_moving_config32(dev, index);
229 /* clear the Enable bit */
230 moving = moving & ~PCI_ROM_ADDRESS_ENABLE;
232 /* Find the resource constraints.
234 * Start by finding the bits that move. From there:
235 * - Size is the least significant bit of the bits that move.
236 * - Limit is all of the bits that move plus all of the lower bits.
237 * See PCI Spec 6.2.5.1 ...
243 resource->align = resource->gran = 0;
244 while (!(moving & resource->size)) {
245 resource->size <<= 1;
246 resource->align += 1;
249 resource->limit = limit = moving | (resource->size - 1);
254 printk_debug("%s register %02x(%08x), read-only ignoring it\n",
255 dev_path(dev), index, value);
259 resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY;
263 /** Read the base address registers for a given device.
264 * @param dev Pointer to the dev structure
265 * @param howmany How many registers to read (6 for device, 2 for bridge)
267 static void pci_read_bases(struct device *dev, unsigned int howmany, unsigned long rom)
271 for (index = PCI_BASE_ADDRESS_0; (index < PCI_BASE_ADDRESS_0 + (howmany << 2)); ) {
272 struct resource *resource;
273 resource = pci_get_resource(dev, index);
274 index += (resource->flags & IORESOURCE_PCI64)?8:4;
277 if ((!dev->on_mainboard) || (dev->rom_address == 0))
278 pci_get_rom_resource(dev, rom);
281 compact_resources(dev);
284 static void pci_set_resource(struct device *dev, struct resource *resource);
286 static void pci_record_bridge_resource( struct device *dev, resource_t moving,
287 unsigned index, unsigned long mask,
290 /* Initiliaze the constraints on the current bus */
291 struct resource *resource;
296 resource = new_resource(dev, index);
300 while((moving & step) == 0) {
304 resource->gran = gran;
305 resource->align = gran;
306 resource->limit = moving | (step - 1);
307 resource->flags = type | IORESOURCE_PCI_BRIDGE;
308 compute_allocate_resource(&dev->link[0], resource, mask, type);
309 /* If there is nothing behind the resource,
310 * clear it and forget it.
312 if (resource->size == 0) {
313 resource->base = moving;
314 resource->flags |= IORESOURCE_ASSIGNED;
315 resource->flags &= ~IORESOURCE_STORED;
316 pci_set_resource(dev, resource);
323 static void pci_bridge_read_bases(struct device *dev)
325 resource_t moving_base, moving_limit, moving;
327 /* See if the bridge I/O resources are implemented */
328 moving_base = ((uint32_t)pci_moving_config8(dev, PCI_IO_BASE)) << 8;
329 moving_base |= ((uint32_t)pci_moving_config16(dev, PCI_IO_BASE_UPPER16)) << 16;
331 moving_limit = ((uint32_t)pci_moving_config8(dev, PCI_IO_LIMIT)) << 8;
332 moving_limit |= ((uint32_t)pci_moving_config16(dev, PCI_IO_LIMIT_UPPER16)) << 16;
334 moving = moving_base & moving_limit;
336 /* Initialize the io space constraints on the current bus */
337 pci_record_bridge_resource(dev, moving, PCI_IO_BASE,
338 IORESOURCE_IO, IORESOURCE_IO);
340 /* See if the bridge prefmem resources are implemented */
341 moving_base = ((resource_t)pci_moving_config16(dev, PCI_PREF_MEMORY_BASE)) << 16;
342 moving_base |= ((resource_t)pci_moving_config32(dev, PCI_PREF_BASE_UPPER32)) << 32;
344 moving_limit = ((resource_t)pci_moving_config16(dev, PCI_PREF_MEMORY_LIMIT)) << 16;
345 moving_limit |= ((resource_t)pci_moving_config32(dev, PCI_PREF_LIMIT_UPPER32)) << 32;
347 moving = moving_base & moving_limit;
348 /* Initiliaze the prefetchable memory constraints on the current bus */
349 pci_record_bridge_resource(dev, moving, PCI_PREF_MEMORY_BASE,
350 IORESOURCE_MEM | IORESOURCE_PREFETCH,
351 IORESOURCE_MEM | IORESOURCE_PREFETCH);
353 /* See if the bridge mem resources are implemented */
354 moving_base = ((uint32_t)pci_moving_config16(dev, PCI_MEMORY_BASE)) << 16;
355 moving_limit = ((uint32_t)pci_moving_config16(dev, PCI_MEMORY_LIMIT)) << 16;
357 moving = moving_base & moving_limit;
359 /* Initialize the memory resources on the current bus */
360 pci_record_bridge_resource(dev, moving, PCI_MEMORY_BASE,
361 IORESOURCE_MEM | IORESOURCE_PREFETCH,
364 compact_resources(dev);
367 void pci_dev_read_resources(struct device *dev)
371 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
374 void pci_bus_read_resources(struct device *dev)
378 pci_bridge_read_bases(dev);
379 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
382 static void pci_set_resource(struct device *dev, struct resource *resource)
384 resource_t base, end;
386 /* Make certain the resource has actually been set */
387 if (!(resource->flags & IORESOURCE_ASSIGNED)) {
388 printk_err("ERROR: %s %02x not allocated\n",
389 dev_path(dev), resource->index);
393 /* If I have already stored this resource don't worry about it */
394 if (resource->flags & IORESOURCE_STORED) {
398 /* If the resources is substractive don't worry about it */
399 if (resource->flags & IORESOURCE_SUBTRACTIVE) {
403 /* Only handle PCI memory and IO resources for now */
404 if (!(resource->flags & (IORESOURCE_MEM |IORESOURCE_IO)))
407 /* Enable the resources in the command register */
408 if (resource->size) {
409 if (resource->flags & IORESOURCE_MEM) {
410 dev->command |= PCI_COMMAND_MEMORY;
412 if (resource->flags & IORESOURCE_IO) {
413 dev->command |= PCI_COMMAND_IO;
415 if (resource->flags & IORESOURCE_PCI_BRIDGE) {
416 dev->command |= PCI_COMMAND_MASTER;
419 /* Get the base address */
420 base = resource->base;
423 end = resource_end(resource);
425 /* Now store the resource */
426 resource->flags |= IORESOURCE_STORED;
427 if (!(resource->flags & IORESOURCE_PCI_BRIDGE)) {
428 unsigned long base_lo, base_hi;
430 * some chipsets allow us to set/clear the IO bit.
431 * (e.g. VIA 82c686a.) So set it to be safe)
433 base_lo = base & 0xffffffff;
434 base_hi = (base >> 32) & 0xffffffff;
435 if (resource->flags & IORESOURCE_IO) {
436 base_lo |= PCI_BASE_ADDRESS_SPACE_IO;
438 pci_write_config32(dev, resource->index, base_lo);
439 if (resource->flags & IORESOURCE_PCI64) {
440 pci_write_config32(dev, resource->index + 4, base_hi);
443 else if (resource->index == PCI_IO_BASE) {
444 /* set the IO ranges */
445 compute_allocate_resource(&dev->link[0], resource,
446 IORESOURCE_IO, IORESOURCE_IO);
447 pci_write_config8(dev, PCI_IO_BASE, base >> 8);
448 pci_write_config16(dev, PCI_IO_BASE_UPPER16, base >> 16);
449 pci_write_config8(dev, PCI_IO_LIMIT, end >> 8);
450 pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, end >> 16);
452 else if (resource->index == PCI_MEMORY_BASE) {
453 /* set the memory range */
454 compute_allocate_resource(&dev->link[0], resource,
455 IORESOURCE_MEM | IORESOURCE_PREFETCH,
457 pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);
458 pci_write_config16(dev, PCI_MEMORY_LIMIT, end >> 16);
460 else if (resource->index == PCI_PREF_MEMORY_BASE) {
461 /* set the prefetchable memory range */
462 compute_allocate_resource(&dev->link[0], resource,
463 IORESOURCE_MEM | IORESOURCE_PREFETCH,
464 IORESOURCE_MEM | IORESOURCE_PREFETCH);
465 pci_write_config16(dev, PCI_PREF_MEMORY_BASE, base >> 16);
466 pci_write_config32(dev, PCI_PREF_BASE_UPPER32, base >> 32);
467 pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, end >> 16);
468 pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, end >> 32);
471 /* Don't let me think I stored the resource */
472 resource->flags &= ~IORESOURCE_STORED;
473 printk_err("ERROR: invalid resource->index %x\n",
476 report_resource_stored(dev, resource, "");
480 void pci_dev_set_resources(struct device *dev)
482 struct resource *resource, *last;
486 last = &dev->resource[dev->resources];
488 for (resource = &dev->resource[0]; resource < last; resource++) {
489 pci_set_resource(dev, resource);
491 for (link = 0; link < dev->links; link++) {
493 bus = &dev->link[link];
495 assign_resources(bus);
499 /* set a default latency timer */
500 pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
502 /* set a default secondary latency timer */
503 if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
504 pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
507 /* zero the irq settings */
508 line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
510 pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
512 /* set the cache line size, so far 64 bytes is good for everyone */
513 pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
516 void pci_dev_enable_resources(struct device *dev)
518 const struct pci_operations *ops;
521 /* Set the subsystem vendor and device id for mainboard devices */
523 if (dev->on_mainboard && ops && ops->set_subsystem) {
524 printk_debug("%s subsystem <- %02x/%02x\n",
526 MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
527 MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
528 ops->set_subsystem(dev,
529 MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
530 MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
532 command = pci_read_config16(dev, PCI_COMMAND);
533 command |= dev->command;
534 command |= (PCI_COMMAND_PARITY + PCI_COMMAND_SERR); /* error check */
535 printk_debug("%s cmd <- %02x\n", dev_path(dev), command);
536 pci_write_config16(dev, PCI_COMMAND, command);
539 void pci_bus_enable_resources(struct device *dev)
543 /* enable IO in command register if there is VGA card
544 * connected with (even it does not claim IO resource) */
545 if (dev->link[0].bridge_ctrl & PCI_BRIDGE_CTL_VGA)
546 dev->command |= PCI_COMMAND_IO;
548 ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
549 ctrl |= dev->link[0].bridge_ctrl;
550 ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error check */
551 printk_debug("%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
552 pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
554 pci_dev_enable_resources(dev);
556 enable_childrens_resources(dev);
559 void pci_dev_set_subsystem(device_t dev, unsigned vendor, unsigned device)
561 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
562 ((device & 0xffff) << 16) | (vendor & 0xffff));
565 void pci_dev_init(struct device *dev)
567 struct rom_header *rom, *ram;
569 rom = pci_rom_probe(dev);
572 ram = pci_rom_load(dev, rom);
577 /** Default device operation for PCI devices */
578 static struct pci_operations pci_dev_ops_pci = {
579 .set_subsystem = pci_dev_set_subsystem,
582 struct device_operations default_pci_ops_dev = {
583 .read_resources = pci_dev_read_resources,
584 .set_resources = pci_dev_set_resources,
585 .enable_resources = pci_dev_enable_resources,
586 .init = pci_dev_init,
589 .ops_pci = &pci_dev_ops_pci,
592 /** Default device operations for PCI bridges */
593 static struct pci_operations pci_bus_ops_pci = {
597 struct device_operations default_pci_ops_bus = {
598 .read_resources = pci_bus_read_resources,
599 .set_resources = pci_dev_set_resources,
600 .enable_resources = pci_bus_enable_resources,
602 .scan_bus = pci_scan_bridge,
604 .ops_pci = &pci_bus_ops_pci,
608 * @brief Set up PCI device operation
615 static void set_pci_ops(struct device *dev)
617 struct pci_driver *driver;
622 /* Look through the list of setup drivers and find one for
625 for (driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) {
626 if ((driver->vendor == dev->vendor) &&
627 (driver->device == dev->device))
629 dev->ops = driver->ops;
630 printk_debug("%s [%04x/%04x] %sops\n",
632 driver->vendor, driver->device,
633 (driver->ops->scan_bus?"bus ":""));
638 /* If I don't have a specific driver use the default operations */
639 switch(dev->hdr_type & 0x7f) { /* header type */
640 case PCI_HEADER_TYPE_NORMAL: /* standard header */
641 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
643 dev->ops = &default_pci_ops_dev;
645 case PCI_HEADER_TYPE_BRIDGE:
646 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
648 dev->ops = &default_pci_ops_bus;
653 printk_err("%s [%04x/%04x/%06x] has unknown header "
654 "type %02x, ignoring.\n",
656 dev->vendor, dev->device,
657 dev->class >> 8, dev->hdr_type);
664 * @brief See if we have already allocated a device structure for a given devfn.
666 * Given a linked list of PCI device structures and a devfn number, find the
667 * device structure correspond to the devfn, if present. This function also
668 * removes the device structure from the linked list.
670 * @param list the device structure list
671 * @param devfn a device/function number
673 * @return pointer to the device structure found or null of we have not
674 * allocated a device for this devfn yet.
676 static struct device *pci_scan_get_dev(struct device **list, unsigned int devfn)
680 for(; *list; list = &(*list)->sibling) {
681 if ((*list)->path.type != DEVICE_PATH_PCI) {
682 printk_err("child %s not a pci device\n",
686 if ((*list)->path.u.pci.devfn == devfn) {
687 /* Unlink from the list */
689 *list = (*list)->sibling;
694 /* Just like alloc_dev add the device to the list of device on the bus.
695 * When the list of devices was formed we removed all of the parents
696 * children, and now we are interleaving static and dynamic devices in
701 /* Find the last child of our parent */
702 for (child = dev->bus->children; child && child->sibling; ) {
703 child = child->sibling;
705 /* Place the device on the list of children of it's parent. */
707 child->sibling = dev;
709 dev->bus->children = dev;
717 * @brief Scan a PCI bus.
719 * Determine the existence of devices and bridges on a PCI bus. If there are
720 * bridges on the bus, recursively scan the buses behind the bridges.
722 * @param bus pointer to the bus structure
723 * @param min_devfn minimum devfn to look at in the scan usually 0x00
724 * @param max_devfn maximum devfn to look at in the scan usually 0xff
725 * @param max current bus number
727 * @return The maximum bus number found, after scanning all subordinate busses
729 unsigned int pci_scan_bus(struct bus *bus, unsigned min_devfn, unsigned max_devfn,
734 device_t old_devices;
737 printk_debug("PCI: pci_scan_bus for bus %d\n", bus->secondary);
739 old_devices = bus->children;
744 /* probe all devices/functions on this bus with some optimization for
745 * non-existence and single funcion devices
747 for (devfn = min_devfn; devfn <= max_devfn; devfn++) {
751 /* First thing setup the device structure */
752 dev = pci_scan_get_dev(&old_devices, devfn);
754 /* Detect if a device is present */
758 dummy.path.type = DEVICE_PATH_PCI;
759 dummy.path.u.pci.devfn = devfn;
760 id = pci_read_config32(&dummy, PCI_VENDOR_ID);
761 /* some broken boards return 0 if a slot is empty: */
762 if ((id == 0xffffffff) || (id == 0x00000000) ||
763 (id == 0x0000ffff) || (id == 0xffff0000))
765 printk_spew("PCI: devfn 0x%x, bad id 0x%x\n", devfn, id);
766 if (PCI_FUNC(devfn) == 0x00) {
767 /* if this is a function 0 device and
769 * skip to next device
773 /* This function in a multi function device is
774 * not present, skip to the next function.
778 dev = alloc_dev(bus, &dummy.path);
781 /* Enable/disable the device. Once we have
782 * found the device specific operations this
783 * operations we will disable the device with
786 * This is geared toward devices that have subfunctions
787 * that do not show up by default.
789 * If a device is a stuff option on the motherboard
790 * it may be absent and enable_dev must cope.
793 if (dev->chip_ops && dev->chip_ops->enable_dev)
795 dev->chip_ops->enable_dev(dev);
797 /* Now read the vendor and device id */
798 id = pci_read_config32(dev, PCI_VENDOR_ID);
800 /* If the device does not have a pci id disable it.
801 * Possibly this is because we have already disabled
802 * the device. But this also handles optional devices
803 * that may not always show up.
805 if (id == 0xffffffff || id == 0x00000000 ||
806 id == 0x0000ffff || id == 0xffff0000)
809 printk_info("Disabling static device: %s\n",
815 /* Read the rest of the pci configuration information */
816 hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
817 class = pci_read_config32(dev, PCI_CLASS_REVISION);
819 /* Store the interesting information in the device structure */
820 dev->vendor = id & 0xffff;
821 dev->device = (id >> 16) & 0xffff;
822 dev->hdr_type = hdr_type;
823 /* class code, the upper 3 bytes of PCI_CLASS_REVISION */
824 dev->class = class >> 8;
826 /* Architectural/System devices always need to
829 if ((dev->class >> 16) == PCI_BASE_CLASS_SYSTEM) {
830 dev->command |= PCI_COMMAND_MASTER;
833 /* Look at the vendor and device id, or at least the
834 * header type and class and figure out which set of
835 * configuration methods to use. Unless we already
839 /* Error if we don't have some pci operations for it */
841 printk_err("%s No device operations\n",
846 /* Now run the magic enable/disable sequence for the device */
847 if (dev->ops && dev->ops->enable) {
848 dev->ops->enable(dev);
851 printk_debug("%s [%04x/%04x] %s\n",
853 dev->vendor, dev->device,
854 dev->enabled?"enabled": "disabled");
856 if (PCI_FUNC(devfn) == 0x00 && (hdr_type & 0x80) != 0x80) {
857 /* if this is not a multi function device,
858 * don't waste time probing another function.
859 * Skip to next device.
866 /* For all children that implement scan_bus (i.e. bridges)
867 * scan the bus behind that child.
869 for (child = bus->children; child; child = child->sibling) {
870 if (!child->enabled ||
872 !child->ops->scan_bus)
876 max = child->ops->scan_bus(child, max);
880 * We've scanned the bus and so we know all about what's on
881 * the other side of any bridges that may be on this bus plus
884 * Return how far we've got finding sub-buses.
886 printk_debug("PCI: pci_scan_bus returning with max=%02x\n", max);
892 * @brief Scan a PCI bridge and the buses behind the bridge.
894 * Determine the existence of buses behind the bridge. Set up the bridge
895 * according to the result of the scan.
897 * This function is the default scan_bus() method for PCI bridge devices.
899 * @param dev pointer to the bridge device
900 * @param max the highest bus number assgined up to now
902 * @return The maximum bus number found, after scanning all subordinate busses
904 unsigned int pci_scan_bridge(struct device *dev, unsigned int max)
910 printk_spew("%s for %s\n", __func__, dev_path(dev));
916 /* Set up the primary, secondary and subordinate bus numbers. We have
917 * no idea how many buses are behind this bridge yet, so we set the
918 * subordinate bus number to 0xff for the moment.
920 bus->secondary = ++max;
921 bus->subordinate = 0xff;
923 /* Clear all status bits and turn off memory, I/O and master enables. */
924 cr = pci_read_config16(dev, PCI_COMMAND);
925 pci_write_config16(dev, PCI_COMMAND, 0x0000);
926 pci_write_config16(dev, PCI_STATUS, 0xffff);
929 * Read the existing primary/secondary/subordinate bus
930 * number configuration.
932 buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
934 /* Configure the bus numbers for this bridge: the configuration
935 * transactions will not be propagated by the bridge if it is not
936 * correctly configured.
939 buses |= (((unsigned int) (dev->bus->secondary) << 0) |
940 ((unsigned int) (bus->secondary) << 8) |
941 ((unsigned int) (bus->subordinate) << 16));
942 pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
944 /* Now we can scan all subordinate buses
945 * i.e. the bus behind the bridge.
947 max = pci_scan_bus(bus, 0x00, 0xff, max);
949 /* We know the number of buses behind this bridge. Set the subordinate
950 * bus number to its real value.
952 bus->subordinate = max;
953 buses = (buses & 0xff00ffff) |
954 ((unsigned int) (bus->subordinate) << 16);
955 pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
956 pci_write_config16(dev, PCI_COMMAND, cr);
958 printk_spew("%s returns max %d\n", __func__, max);
963 Tell the EISA int controller this int must be level triggered
964 THIS IS A KLUDGE -- sorry, this needs to get cleaned up.
966 static void pci_level_irq(unsigned char intNum)
968 unsigned short intBits = inb(0x4d0) | (((unsigned) inb(0x4d1)) << 8);
970 printk_spew("%s: current ints are 0x%x\n", __func__, intBits);
971 intBits |= (1 << intNum);
973 printk_spew("%s: try to set ints 0x%x\n", __func__, intBits);
976 outb((unsigned char) intBits, 0x4d0);
977 outb((unsigned char) (intBits >> 8), 0x4d1);
979 /* this seems like an error but is not ... */
981 if (inb(0x4d0) != (intBits & 0xf)) {
982 printk_err("%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
983 __func__, intBits &0xf, inb(0x4d0));
985 if (inb(0x4d1) != ((intBits >> 8) & 0xf)) {
986 printk_err("%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
987 __func__, (intBits>>8) &0xf, inb(0x4d1));
993 This function assigns IRQs for all functions contained within
994 the indicated device address. If the device does not exist or does
995 not require interrupts then this function has no effect.
997 This function should be called for each PCI slot in your system.
999 pIntAtoD is an array of IRQ #s that are assigned to PINTA through PINTD of
1001 The particular irq #s that are passed in depend on the routing inside
1002 your southbridge and on your motherboard.
1006 void pci_assign_irqs(unsigned bus, unsigned slot, const unsigned char pIntAtoD[4])
1012 unsigned char readback;
1014 /* Each slot may contain up to eight functions */
1015 for (functNum = 0; functNum < 8; functNum++) {
1016 pdev = dev_find_slot(bus, (slot << 3) + functNum);
1019 line = pci_read_config8(pdev, PCI_INTERRUPT_PIN);
1021 // PCI spec says all other values are reserved
1022 if ((line >= 1) && (line <= 4)) {
1023 irq = pIntAtoD[line - 1];
1025 printk_debug("Assigning IRQ %d to %d:%x.%d\n", \
1026 irq, bus, slot, functNum);
1028 pci_write_config8(pdev, PCI_INTERRUPT_LINE,\
1029 pIntAtoD[line - 1]);
1031 readback = pci_read_config8(pdev, PCI_INTERRUPT_LINE);
1032 printk_debug(" Readback = %d\n", readback);
1034 // Change to level triggered
1035 pci_level_irq(pIntAtoD[line - 1]);