2 * This file is part of the coreboot project.
4 * It was originally based on the Linux kernel (drivers/pci/pci.c).
7 * Copyright (C) 2003-2004 Linux Networx
8 * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
9 * Copyright (C) 2003-2006 Ronald G. Minnich <rminnich@gmail.com>
10 * Copyright (C) 2004-2005 Li-Ta Lo <ollie@lanl.gov>
11 * Copyright (C) 2005-2006 Tyan
12 * (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
13 * Copyright (C) 2005-2009 coresystems GmbH
14 * (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
18 * PCI Bus Services, see include/linux/pci.h for further explanation.
20 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
21 * David Mosberger-Tang
23 * Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
26 #include <console/console.h>
32 #include <device/device.h>
33 #include <device/pci.h>
34 #include <device/pci_ids.h>
36 #if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1
37 #include <device/hypertransport.h>
39 #if CONFIG_PCIX_PLUGIN_SUPPORT == 1
40 #include <device/pcix.h>
42 #if CONFIG_PCIEXP_PLUGIN_SUPPORT == 1
43 #include <device/pciexp.h>
45 #if CONFIG_AGP_PLUGIN_SUPPORT == 1
46 #include <device/agp.h>
48 #if CONFIG_CARDBUS_PLUGIN_SUPPORT == 1
49 #include <device/cardbus.h>
51 #if CONFIG_PC80_SYSTEM == 1
52 #include <pc80/i8259.h>
55 u8 pci_moving_config8(struct device *dev, unsigned int reg)
57 u8 value, ones, zeroes;
59 value = pci_read_config8(dev, reg);
61 pci_write_config8(dev, reg, 0xff);
62 ones = pci_read_config8(dev, reg);
64 pci_write_config8(dev, reg, 0x00);
65 zeroes = pci_read_config8(dev, reg);
67 pci_write_config8(dev, reg, value);
72 u16 pci_moving_config16(struct device *dev, unsigned int reg)
74 u16 value, ones, zeroes;
76 value = pci_read_config16(dev, reg);
78 pci_write_config16(dev, reg, 0xffff);
79 ones = pci_read_config16(dev, reg);
81 pci_write_config16(dev, reg, 0x0000);
82 zeroes = pci_read_config16(dev, reg);
84 pci_write_config16(dev, reg, value);
89 u32 pci_moving_config32(struct device *dev, unsigned int reg)
91 u32 value, ones, zeroes;
93 value = pci_read_config32(dev, reg);
95 pci_write_config32(dev, reg, 0xffffffff);
96 ones = pci_read_config32(dev, reg);
98 pci_write_config32(dev, reg, 0x00000000);
99 zeroes = pci_read_config32(dev, reg);
101 pci_write_config32(dev, reg, value);
103 return ones ^ zeroes;
107 * Given a device, a capability type, and a last position, return the next
108 * matching capability. Always start at the head of the list.
110 * @param dev Pointer to the device structure.
111 * @param cap PCI_CAP_LIST_ID of the PCI capability we're looking for.
112 * @param last Location of the PCI capability register to start from.
113 * @return The next matching capability.
115 unsigned pci_find_next_capability(struct device *dev, unsigned cap,
122 status = pci_read_config16(dev, PCI_STATUS);
123 if (!(status & PCI_STATUS_CAP_LIST))
126 switch (dev->hdr_type & 0x7f) {
127 case PCI_HEADER_TYPE_NORMAL:
128 case PCI_HEADER_TYPE_BRIDGE:
129 pos = PCI_CAPABILITY_LIST;
131 case PCI_HEADER_TYPE_CARDBUS:
132 pos = PCI_CB_CAPABILITY_LIST;
138 pos = pci_read_config8(dev, pos);
139 while (reps-- && (pos >= 0x40)) { /* Loop through the linked list. */
143 this_cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID);
144 printk(BIOS_SPEW, "Capability: type 0x%02x @ 0x%02x\n",
146 if (this_cap == 0xff)
149 if (!last && (this_cap == cap))
155 pos = pci_read_config8(dev, pos + PCI_CAP_LIST_NEXT);
161 * Given a device, and a capability type, return the next matching
162 * capability. Always start at the head of the list.
164 * @param dev Pointer to the device structure.
165 * @param cap PCI_CAP_LIST_ID of the PCI capability we're looking for.
166 * @return The next matching capability.
168 unsigned pci_find_capability(device_t dev, unsigned cap)
170 return pci_find_next_capability(dev, cap, 0);
174 * Given a device and register, read the size of the BAR for that register.
176 * @param dev Pointer to the device structure.
177 * @param index Address of the PCI configuration register.
180 struct resource *pci_get_resource(struct device *dev, unsigned long index)
182 struct resource *resource;
183 unsigned long value, attr;
184 resource_t moving, limit;
186 /* Initialize the resources to nothing. */
187 resource = new_resource(dev, index);
189 /* Get the initial value. */
190 value = pci_read_config32(dev, index);
192 /* See which bits move. */
193 moving = pci_moving_config32(dev, index);
195 /* Initialize attr to the bits that do not move. */
196 attr = value & ~moving;
198 /* If it is a 64bit resource look at the high half as well. */
199 if (((attr & PCI_BASE_ADDRESS_SPACE_IO) == 0) &&
200 ((attr & PCI_BASE_ADDRESS_MEM_LIMIT_MASK) ==
201 PCI_BASE_ADDRESS_MEM_LIMIT_64)) {
202 /* Find the high bits that move. */
204 ((resource_t) pci_moving_config32(dev, index + 4)) << 32;
207 /* Find the resource constraints.
208 * Start by finding the bits that move. From there:
209 * - Size is the least significant bit of the bits that move.
210 * - Limit is all of the bits that move plus all of the lower bits.
211 * See PCI Spec 6.2.5.1.
216 resource->align = resource->gran = 0;
217 while (!(moving & resource->size)) {
218 resource->size <<= 1;
219 resource->align += 1;
222 resource->limit = limit = moving | (resource->size - 1);
226 * Some broken hardware has read-only registers that do not
227 * really size correctly.
229 * Example: the Acer M7229 has BARs 1-4 normally read-only,
230 * so BAR1 at offset 0x10 reads 0x1f1. If you size that register
231 * by writing 0xffffffff to it, it will read back as 0x1f1 -- which
232 * is a violation of the spec.
234 * We catch this case and ignore it by observing which bits move.
236 * This also catches the common case of unimplemented registers
237 * that always read back as 0.
241 printk(BIOS_DEBUG, "%s register %02lx(%08lx), "
242 "read-only ignoring it\n",
243 dev_path(dev), index, value);
246 } else if (attr & PCI_BASE_ADDRESS_SPACE_IO) {
247 /* An I/O mapped base address. */
248 attr &= PCI_BASE_ADDRESS_IO_ATTR_MASK;
249 resource->flags |= IORESOURCE_IO;
250 /* I don't want to deal with 32bit I/O resources. */
251 resource->limit = 0xffff;
253 /* A Memory mapped base address. */
254 attr &= PCI_BASE_ADDRESS_MEM_ATTR_MASK;
255 resource->flags |= IORESOURCE_MEM;
256 if (attr & PCI_BASE_ADDRESS_MEM_PREFETCH)
257 resource->flags |= IORESOURCE_PREFETCH;
258 attr &= PCI_BASE_ADDRESS_MEM_LIMIT_MASK;
259 if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_32) {
261 resource->limit = 0xffffffffUL;
262 } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_1M) {
264 resource->limit = 0x000fffffUL;
265 } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_64) {
267 resource->limit = 0xffffffffffffffffULL;
268 resource->flags |= IORESOURCE_PCI64;
271 printk(BIOS_ERR, "Broken BAR with value %lx\n", attr);
272 printk(BIOS_ERR, " on dev %s at index %02lx\n",
273 dev_path(dev), index);
278 /* Don't let the limit exceed which bits can move. */
279 if (resource->limit > limit)
280 resource->limit = limit;
286 * Given a device and an index, read the size of the BAR for that register.
288 * @param dev Pointer to the device structure.
289 * @param index Address of the PCI configuration register.
291 static void pci_get_rom_resource(struct device *dev, unsigned long index)
293 struct resource *resource;
297 /* Initialize the resources to nothing. */
298 resource = new_resource(dev, index);
300 /* Get the initial value. */
301 value = pci_read_config32(dev, index);
303 /* See which bits move. */
304 moving = pci_moving_config32(dev, index);
306 /* Clear the Enable bit. */
307 moving = moving & ~PCI_ROM_ADDRESS_ENABLE;
309 /* Find the resource constraints.
310 * Start by finding the bits that move. From there:
311 * - Size is the least significant bit of the bits that move.
312 * - Limit is all of the bits that move plus all of the lower bits.
313 * See PCI Spec 6.2.5.1.
317 resource->align = resource->gran = 0;
318 while (!(moving & resource->size)) {
319 resource->size <<= 1;
320 resource->align += 1;
323 resource->limit = moving | (resource->size - 1);
324 resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY;
327 printk(BIOS_DEBUG, "%s register %02lx(%08lx), "
328 "read-only ignoring it\n",
329 dev_path(dev), index, value);
333 compact_resources(dev);
337 * Read the base address registers for a given device.
339 * @param dev Pointer to the dev structure.
340 * @param howmany How many registers to read (6 for device, 2 for bridge).
342 static void pci_read_bases(struct device *dev, unsigned int howmany)
346 for (index = PCI_BASE_ADDRESS_0;
347 (index < PCI_BASE_ADDRESS_0 + (howmany << 2));) {
348 struct resource *resource;
349 resource = pci_get_resource(dev, index);
350 index += (resource->flags & IORESOURCE_PCI64) ? 8 : 4;
353 compact_resources(dev);
356 static void pci_record_bridge_resource(struct device *dev, resource_t moving,
357 unsigned index, unsigned long type)
359 struct resource *resource;
368 /* Initialize the constraints on the current bus. */
369 resource = new_resource(dev, index);
373 while ((moving & step) == 0) {
377 resource->gran = gran;
378 resource->align = gran;
379 resource->limit = moving | (step - 1);
380 resource->flags = type | IORESOURCE_PCI_BRIDGE |
384 static void pci_bridge_read_bases(struct device *dev)
386 resource_t moving_base, moving_limit, moving;
388 /* See if the bridge I/O resources are implemented. */
389 moving_base = ((u32) pci_moving_config8(dev, PCI_IO_BASE)) << 8;
391 ((u32) pci_moving_config16(dev, PCI_IO_BASE_UPPER16)) << 16;
393 moving_limit = ((u32) pci_moving_config8(dev, PCI_IO_LIMIT)) << 8;
395 ((u32) pci_moving_config16(dev, PCI_IO_LIMIT_UPPER16)) << 16;
397 moving = moving_base & moving_limit;
399 /* Initialize the I/O space constraints on the current bus. */
400 pci_record_bridge_resource(dev, moving, PCI_IO_BASE, IORESOURCE_IO);
402 /* See if the bridge prefmem resources are implemented. */
404 ((resource_t) pci_moving_config16(dev, PCI_PREF_MEMORY_BASE)) << 16;
406 ((resource_t) pci_moving_config32(dev, PCI_PREF_BASE_UPPER32)) << 32;
409 ((resource_t) pci_moving_config16(dev, PCI_PREF_MEMORY_LIMIT)) << 16;
411 ((resource_t) pci_moving_config32(dev, PCI_PREF_LIMIT_UPPER32)) << 32;
413 moving = moving_base & moving_limit;
414 /* Initialize the prefetchable memory constraints on the current bus. */
415 pci_record_bridge_resource(dev, moving, PCI_PREF_MEMORY_BASE,
416 IORESOURCE_MEM | IORESOURCE_PREFETCH);
418 /* See if the bridge mem resources are implemented. */
419 moving_base = ((u32) pci_moving_config16(dev, PCI_MEMORY_BASE)) << 16;
420 moving_limit = ((u32) pci_moving_config16(dev, PCI_MEMORY_LIMIT)) << 16;
422 moving = moving_base & moving_limit;
424 /* Initialize the memory resources on the current bus. */
425 pci_record_bridge_resource(dev, moving, PCI_MEMORY_BASE,
428 compact_resources(dev);
431 void pci_dev_read_resources(struct device *dev)
433 pci_read_bases(dev, 6);
434 pci_get_rom_resource(dev, PCI_ROM_ADDRESS);
437 void pci_bus_read_resources(struct device *dev)
439 pci_bridge_read_bases(dev);
440 pci_read_bases(dev, 2);
441 pci_get_rom_resource(dev, PCI_ROM_ADDRESS1);
444 void pci_domain_read_resources(struct device *dev)
446 struct resource *res;
448 /* Initialize the system-wide I/O space constraints. */
449 res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
450 res->limit = 0xffffUL;
451 res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
454 /* Initialize the system-wide memory resources constraints. */
455 res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
456 res->limit = 0xffffffffULL;
457 res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
461 static void pci_set_resource(struct device *dev, struct resource *resource)
463 resource_t base, end;
465 /* Make certain the resource has actually been assigned a value. */
466 if (!(resource->flags & IORESOURCE_ASSIGNED)) {
467 printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010llx not "
468 "assigned\n", dev_path(dev), resource->index,
469 resource_type(resource), resource->size);
473 /* If this resource is fixed don't worry about it. */
474 if (resource->flags & IORESOURCE_FIXED)
477 /* If I have already stored this resource don't worry about it. */
478 if (resource->flags & IORESOURCE_STORED)
481 /* If the resource is subtractive don't worry about it. */
482 if (resource->flags & IORESOURCE_SUBTRACTIVE)
485 /* Only handle PCI memory and I/O resources for now. */
486 if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
489 /* Enable the resources in the command register. */
490 if (resource->size) {
491 if (resource->flags & IORESOURCE_MEM)
492 dev->command |= PCI_COMMAND_MEMORY;
493 if (resource->flags & IORESOURCE_IO)
494 dev->command |= PCI_COMMAND_IO;
495 if (resource->flags & IORESOURCE_PCI_BRIDGE)
496 dev->command |= PCI_COMMAND_MASTER;
499 /* Get the base address. */
500 base = resource->base;
503 end = resource_end(resource);
505 /* Now store the resource. */
506 resource->flags |= IORESOURCE_STORED;
509 * PCI bridges have no enable bit. They are disabled if the base of
510 * the range is greater than the limit. If the size is zero, disable
511 * by setting the base = limit and end = limit - 2^gran.
513 if (resource->size == 0 && (resource->flags & IORESOURCE_PCI_BRIDGE)) {
514 base = resource->limit;
515 end = resource->limit - (1 << resource->gran);
516 resource->base = base;
519 if (!(resource->flags & IORESOURCE_PCI_BRIDGE)) {
520 unsigned long base_lo, base_hi;
523 * Some chipsets allow us to set/clear the I/O bit
524 * (e.g. VIA 82C686A). So set it to be safe.
526 base_lo = base & 0xffffffff;
527 base_hi = (base >> 32) & 0xffffffff;
528 if (resource->flags & IORESOURCE_IO)
529 base_lo |= PCI_BASE_ADDRESS_SPACE_IO;
530 pci_write_config32(dev, resource->index, base_lo);
531 if (resource->flags & IORESOURCE_PCI64)
532 pci_write_config32(dev, resource->index + 4, base_hi);
533 } else if (resource->index == PCI_IO_BASE) {
534 /* Set the I/O ranges. */
535 pci_write_config8(dev, PCI_IO_BASE, base >> 8);
536 pci_write_config16(dev, PCI_IO_BASE_UPPER16, base >> 16);
537 pci_write_config8(dev, PCI_IO_LIMIT, end >> 8);
538 pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, end >> 16);
539 } else if (resource->index == PCI_MEMORY_BASE) {
540 /* Set the memory range. */
541 pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);
542 pci_write_config16(dev, PCI_MEMORY_LIMIT, end >> 16);
543 } else if (resource->index == PCI_PREF_MEMORY_BASE) {
544 /* Set the prefetchable memory range. */
545 pci_write_config16(dev, PCI_PREF_MEMORY_BASE, base >> 16);
546 pci_write_config32(dev, PCI_PREF_BASE_UPPER32, base >> 32);
547 pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, end >> 16);
548 pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, end >> 32);
550 /* Don't let me think I stored the resource. */
551 resource->flags &= ~IORESOURCE_STORED;
552 printk(BIOS_ERR, "ERROR: invalid resource->index %lx\n",
556 report_resource_stored(dev, resource, "");
559 void pci_dev_set_resources(struct device *dev)
561 struct resource *res;
565 for (res = dev->resource_list; res; res = res->next)
566 pci_set_resource(dev, res);
568 for (bus = dev->link_list; bus; bus = bus->next) {
570 assign_resources(bus);
573 /* Set a default latency timer. */
574 pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
576 /* Set a default secondary latency timer. */
577 if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE)
578 pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
580 /* Zero the IRQ settings. */
581 line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
583 pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
585 /* Set the cache line size, so far 64 bytes is good for everyone. */
586 pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
589 void pci_dev_enable_resources(struct device *dev)
591 const struct pci_operations *ops;
594 /* Set the subsystem vendor and device ID for mainboard devices. */
596 if (dev->on_mainboard && ops && ops->set_subsystem) {
597 printk(BIOS_DEBUG, "%s subsystem <- %02x/%02x\n", dev_path(dev),
598 CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
599 CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
600 ops->set_subsystem(dev,
601 CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
602 CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
604 command = pci_read_config16(dev, PCI_COMMAND);
605 command |= dev->command;
608 * command |= (PCI_COMMAND_PARITY + PCI_COMMAND_SERR); // Error check.
611 printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command);
612 pci_write_config16(dev, PCI_COMMAND, command);
615 void pci_bus_enable_resources(struct device *dev)
620 * Enable I/O in command register if there is VGA card
621 * connected with (even it does not claim I/O resource).
623 if (dev->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA)
624 dev->command |= PCI_COMMAND_IO;
625 ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
626 ctrl |= dev->link_list->bridge_ctrl;
627 ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* Error check. */
628 printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
629 pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
631 pci_dev_enable_resources(dev);
634 void pci_bus_reset(struct bus *bus)
638 ctl = pci_read_config16(bus->dev, PCI_BRIDGE_CONTROL);
639 ctl |= PCI_BRIDGE_CTL_BUS_RESET;
640 pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, ctl);
643 ctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
644 pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, ctl);
648 void pci_dev_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
650 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
651 ((device & 0xffff) << 16) | (vendor & 0xffff));
654 /** Default handler: only runs the relevant PCI BIOS. */
655 void pci_dev_init(struct device *dev)
657 #if CONFIG_PCI_ROM_RUN == 1 || CONFIG_VGA_ROM_RUN == 1
658 struct rom_header *rom, *ram;
660 if (CONFIG_PCI_ROM_RUN != 1 && /* Only execute VGA ROMs. */
661 ((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA))
664 if (CONFIG_VGA_ROM_RUN != 1 && /* Only execute non-VGA ROMs. */
665 ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA))
668 rom = pci_rom_probe(dev);
672 ram = pci_rom_load(dev, rom);
676 run_bios(dev, (unsigned long)ram);
677 #endif /* CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN */
680 /** Default device operation for PCI devices */
681 static struct pci_operations pci_dev_ops_pci = {
682 .set_subsystem = pci_dev_set_subsystem,
685 struct device_operations default_pci_ops_dev = {
686 .read_resources = pci_dev_read_resources,
687 .set_resources = pci_dev_set_resources,
688 .enable_resources = pci_dev_enable_resources,
689 .init = pci_dev_init,
692 .ops_pci = &pci_dev_ops_pci,
695 /** Default device operations for PCI bridges */
696 static struct pci_operations pci_bus_ops_pci = {
700 struct device_operations default_pci_ops_bus = {
701 .read_resources = pci_bus_read_resources,
702 .set_resources = pci_dev_set_resources,
703 .enable_resources = pci_bus_enable_resources,
705 .scan_bus = pci_scan_bridge,
707 .reset_bus = pci_bus_reset,
708 .ops_pci = &pci_bus_ops_pci,
712 * Detect the type of downstream bridge.
714 * This function is a heuristic to detect which type of bus is downstream
715 * of a PCI-to-PCI bridge. This functions by looking for various capability
716 * blocks to figure out the type of downstream bridge. PCI-X, PCI-E, and
717 * Hypertransport all seem to have appropriate capabilities.
719 * When only a PCI-Express capability is found the type is examined to see
720 * which type of bridge we have.
722 * @param dev Pointer to the device structure of the bridge.
723 * @return Appropriate bridge operations.
725 static struct device_operations *get_pci_bridge_ops(device_t dev)
729 #if CONFIG_PCIX_PLUGIN_SUPPORT == 1
730 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
732 printk(BIOS_DEBUG, "%s subordinate bus PCI-X\n", dev_path(dev));
733 return &default_pcix_ops_bus;
736 #if CONFIG_AGP_PLUGIN_SUPPORT == 1
737 /* How do I detect a PCI to AGP bridge? */
739 #if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1
741 while ((pos = pci_find_next_capability(dev, PCI_CAP_ID_HT, pos))) {
743 flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
744 if ((flags >> 13) == 1) {
745 /* Host or Secondary Interface */
746 printk(BIOS_DEBUG, "%s subordinate bus HT\n",
748 return &default_ht_ops_bus;
752 #if CONFIG_PCIEXP_PLUGIN_SUPPORT == 1
753 pos = pci_find_capability(dev, PCI_CAP_ID_PCIE);
756 flags = pci_read_config16(dev, pos + PCI_EXP_FLAGS);
757 switch ((flags & PCI_EXP_FLAGS_TYPE) >> 4) {
758 case PCI_EXP_TYPE_ROOT_PORT:
759 case PCI_EXP_TYPE_UPSTREAM:
760 case PCI_EXP_TYPE_DOWNSTREAM:
761 printk(BIOS_DEBUG, "%s subordinate bus PCI Express\n",
763 return &default_pciexp_ops_bus;
764 case PCI_EXP_TYPE_PCI_BRIDGE:
765 printk(BIOS_DEBUG, "%s subordinate PCI\n",
767 return &default_pci_ops_bus;
773 return &default_pci_ops_bus;
777 * Set up PCI device operation.
779 * Check if it already has a driver. If not, use find_device_operations(),
780 * or set to a default based on type.
782 * @param dev Pointer to the device whose pci_ops you want to set.
785 static void set_pci_ops(struct device *dev)
787 struct pci_driver *driver;
793 * Look through the list of setup drivers and find one for
796 for (driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) {
797 if ((driver->vendor == dev->vendor) &&
798 (driver->device == dev->device)) {
799 dev->ops = (struct device_operations *)driver->ops;
800 printk(BIOS_SPEW, "%s [%04x/%04x] %sops\n",
801 dev_path(dev), driver->vendor, driver->device,
802 (driver->ops->scan_bus ? "bus " : ""));
807 /* If I don't have a specific driver use the default operations. */
808 switch (dev->hdr_type & 0x7f) { /* Header type */
809 case PCI_HEADER_TYPE_NORMAL:
810 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
812 dev->ops = &default_pci_ops_dev;
814 case PCI_HEADER_TYPE_BRIDGE:
815 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
817 dev->ops = get_pci_bridge_ops(dev);
819 #if CONFIG_CARDBUS_PLUGIN_SUPPORT == 1
820 case PCI_HEADER_TYPE_CARDBUS:
821 dev->ops = &default_cardbus_ops_bus;
827 printk(BIOS_ERR, "%s [%04x/%04x/%06x] has unknown "
828 "header type %02x, ignoring.\n", dev_path(dev),
829 dev->vendor, dev->device,
830 dev->class >> 8, dev->hdr_type);
836 * See if we have already allocated a device structure for a given devfn.
838 * Given a linked list of PCI device structures and a devfn number, find the
839 * device structure correspond to the devfn, if present. This function also
840 * removes the device structure from the linked list.
842 * @param list The device structure list.
843 * @param devfn A device/function number.
844 * @return Pointer to the device structure found or NULL if we have not
845 * allocated a device for this devfn yet.
847 static struct device *pci_scan_get_dev(struct device **list, unsigned int devfn)
852 for (; *list; list = &(*list)->sibling) {
853 if ((*list)->path.type != DEVICE_PATH_PCI) {
854 printk(BIOS_ERR, "child %s not a PCI device\n",
858 if ((*list)->path.pci.devfn == devfn) {
859 /* Unlink from the list. */
861 *list = (*list)->sibling;
868 * Just like alloc_dev() add the device to the list of devices on the
869 * bus. When the list of devices was formed we removed all of the
870 * parents children, and now we are interleaving static and dynamic
871 * devices in order on the bus.
874 struct device *child;
876 /* Find the last child of our parent. */
877 for (child = dev->bus->children; child && child->sibling;)
878 child = child->sibling;
880 /* Place the device on the list of children of its parent. */
882 child->sibling = dev;
884 dev->bus->children = dev;
893 * Determine the existence of a given PCI device. Allocate a new struct device
894 * if dev==NULL was passed in and the device exists in hardware.
896 * @param dev Pointer to the dev structure.
897 * @param bus Pointer to the bus structure.
898 * @param devfn A device/function number to look at.
899 * @return The device structure for the device (if found), NULL otherwise.
901 device_t pci_probe_dev(device_t dev, struct bus *bus, unsigned devfn)
906 /* Detect if a device is present. */
911 dummy.path.type = DEVICE_PATH_PCI;
912 dummy.path.pci.devfn = devfn;
914 id = pci_read_config32(&dummy, PCI_VENDOR_ID);
916 * Have we found something? Some broken boards return 0 if a
917 * slot is empty, but the expected answer is 0xffffffff.
919 if (id == 0xffffffff)
922 if ((id == 0x00000000) || (id == 0x0000ffff) ||
923 (id == 0xffff0000)) {
924 printk(BIOS_SPEW, "%s, bad id 0x%x\n",
925 dev_path(&dummy), id);
928 dev = alloc_dev(bus, &dummy.path);
931 * Enable/disable the device. Once we have found the device-
932 * specific operations this operations we will disable the
933 * device with those as well.
935 * This is geared toward devices that have subfunctions
936 * that do not show up by default.
938 * If a device is a stuff option on the motherboard
939 * it may be absent and enable_dev() must cope.
941 /* Run the magic enable sequence for the device. */
942 if (dev->chip_ops && dev->chip_ops->enable_dev)
943 dev->chip_ops->enable_dev(dev);
945 /* Now read the vendor and device ID. */
946 id = pci_read_config32(dev, PCI_VENDOR_ID);
949 * If the device does not have a PCI ID disable it. Possibly
950 * this is because we have already disabled the device. But
951 * this also handles optional devices that may not always
954 /* If the chain is fully enumerated quit */
955 if ((id == 0xffffffff) || (id == 0x00000000) ||
956 (id == 0x0000ffff) || (id == 0xffff0000)) {
958 printk(BIOS_INFO, "PCI: Static device %s not "
959 "found, disabling it.\n", dev_path(dev));
966 /* Read the rest of the PCI configuration information. */
967 hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
968 class = pci_read_config32(dev, PCI_CLASS_REVISION);
970 /* Store the interesting information in the device structure. */
971 dev->vendor = id & 0xffff;
972 dev->device = (id >> 16) & 0xffff;
973 dev->hdr_type = hdr_type;
975 /* Class code, the upper 3 bytes of PCI_CLASS_REVISION. */
976 dev->class = class >> 8;
978 /* Architectural/System devices always need to be bus masters. */
979 if ((dev->class >> 16) == PCI_BASE_CLASS_SYSTEM)
980 dev->command |= PCI_COMMAND_MASTER;
983 * Look at the vendor and device ID, or at least the header type and
984 * class and figure out which set of configuration methods to use.
985 * Unless we already have some PCI ops.
989 /* Now run the magic enable/disable sequence for the device. */
990 if (dev->ops && dev->ops->enable)
991 dev->ops->enable(dev);
993 /* Display the device. */
994 printk(BIOS_DEBUG, "%s [%04x/%04x] %s%s\n", dev_path(dev),
995 dev->vendor, dev->device, dev->enabled ? "enabled" : "disabled",
996 dev->ops ? "" : " No operations");
1004 * Determine the existence of devices and bridges on a PCI bus. If there are
1005 * bridges on the bus, recursively scan the buses behind the bridges.
1007 * This function is the default scan_bus() method for the root device
1010 * @param bus Pointer to the bus structure.
1011 * @param min_devfn Minimum devfn to look at in the scan, usually 0x00.
1012 * @param max_devfn Maximum devfn to look at in the scan, usually 0xff.
1013 * @param max Current bus number.
1014 * @return The maximum bus number found, after scanning all subordinate busses.
1016 unsigned int pci_scan_bus(struct bus *bus, unsigned min_devfn,
1017 unsigned max_devfn, unsigned int max)
1020 struct device *old_devices;
1021 struct device *child;
1023 #if CONFIG_PCI_BUS_SEGN_BITS
1024 printk(BIOS_DEBUG, "PCI: pci_scan_bus for bus %04x:%02x\n",
1025 bus->secondary >> 8, bus->secondary & 0xff);
1027 printk(BIOS_DEBUG, "PCI: pci_scan_bus for bus %02x\n", bus->secondary);
1030 /* Maximum sane devfn is 0xFF. */
1031 if (max_devfn > 0xff) {
1032 printk(BIOS_ERR, "PCI: pci_scan_bus limits devfn %x - "
1033 "devfn %x\n", min_devfn, max_devfn);
1034 printk(BIOS_ERR, "PCI: pci_scan_bus upper limit too big. "
1039 old_devices = bus->children;
1040 bus->children = NULL;
1045 * Probe all devices/functions on this bus with some optimization for
1046 * non-existence and single function devices.
1048 for (devfn = min_devfn; devfn <= max_devfn; devfn++) {
1051 /* First thing setup the device structure. */
1052 dev = pci_scan_get_dev(&old_devices, devfn);
1054 /* See if a device is present and setup the device structure. */
1055 dev = pci_probe_dev(dev, bus, devfn);
1058 * If this is not a multi function device, or the device is
1059 * not present don't waste time probing another function.
1060 * Skip to next device.
1062 if ((PCI_FUNC(devfn) == 0x00) && (!dev
1063 || (dev->enabled && ((dev->hdr_type & 0x80) != 0x80)))) {
1071 * Warn if any leftover static devices are are found.
1072 * There's probably a problem in devicetree.cb.
1076 printk(BIOS_WARNING, "PCI: Left over static devices:\n");
1077 for (left = old_devices; left; left = left->sibling)
1078 printk(BIOS_WARNING, "%s\n", dev_path(left));
1080 printk(BIOS_WARNING, "PCI: Check your devicetree.cb.\n");
1084 * For all children that implement scan_bus() (i.e. bridges)
1085 * scan the bus behind that child.
1087 for (child = bus->children; child; child = child->sibling)
1088 max = scan_bus(child, max);
1091 * We've scanned the bus and so we know all about what's on the other
1092 * side of any bridges that may be on this bus plus any devices.
1093 * Return how far we've got finding sub-buses.
1095 printk(BIOS_DEBUG, "PCI: pci_scan_bus returning with max=%03x\n", max);
1101 * Scan a PCI bridge and the buses behind the bridge.
1103 * Determine the existence of buses behind the bridge. Set up the bridge
1104 * according to the result of the scan.
1106 * This function is the default scan_bus() method for PCI bridge devices.
1108 * @param dev Pointer to the bridge device.
1109 * @param max The highest bus number assigned up to now.
1110 * @param do_scan_bus TODO
1111 * @return The maximum bus number found, after scanning all subordinate buses.
1113 unsigned int do_pci_scan_bridge(struct device *dev, unsigned int max,
1114 unsigned int (*do_scan_bus) (struct bus * bus,
1123 printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(dev));
1125 if (dev->link_list == NULL) {
1127 link = malloc(sizeof(*link));
1129 die("Couldn't allocate a link!\n");
1130 memset(link, 0, sizeof(*link));
1132 dev->link_list = link;
1135 bus = dev->link_list;
1138 * Set up the primary, secondary and subordinate bus numbers. We have
1139 * no idea how many buses are behind this bridge yet, so we set the
1140 * subordinate bus number to 0xff for the moment.
1142 bus->secondary = ++max;
1143 bus->subordinate = 0xff;
1145 /* Clear all status bits and turn off memory, I/O and master enables. */
1146 cr = pci_read_config16(dev, PCI_COMMAND);
1147 pci_write_config16(dev, PCI_COMMAND, 0x0000);
1148 pci_write_config16(dev, PCI_STATUS, 0xffff);
1151 * Read the existing primary/secondary/subordinate bus
1152 * number configuration.
1154 buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
1157 * Configure the bus numbers for this bridge: the configuration
1158 * transactions will not be propagated by the bridge if it is not
1159 * correctly configured.
1161 buses &= 0xff000000;
1162 buses |= (((unsigned int)(dev->bus->secondary) << 0) |
1163 ((unsigned int)(bus->secondary) << 8) |
1164 ((unsigned int)(bus->subordinate) << 16));
1165 pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
1167 /* Now we can scan all subordinate buses (those behind the bridge). */
1168 max = do_scan_bus(bus, 0x00, 0xff, max);
1171 * We know the number of buses behind this bridge. Set the subordinate
1172 * bus number to its real value.
1174 bus->subordinate = max;
1175 buses = (buses & 0xff00ffff) | ((unsigned int)(bus->subordinate) << 16);
1176 pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
1177 pci_write_config16(dev, PCI_COMMAND, cr);
1179 printk(BIOS_SPEW, "%s returns max %d\n", __func__, max);
1184 * Scan a PCI bridge and the buses behind the bridge.
1186 * Determine the existence of buses behind the bridge. Set up the bridge
1187 * according to the result of the scan.
1189 * This function is the default scan_bus() method for PCI bridge devices.
1191 * @param dev Pointer to the bridge device.
1192 * @param max The highest bus number assigned up to now.
1193 * @return The maximum bus number found, after scanning all subordinate buses.
1195 unsigned int pci_scan_bridge(struct device *dev, unsigned int max)
1197 return do_pci_scan_bridge(dev, max, pci_scan_bus);
1201 * Scan a PCI domain.
1203 * This function is the default scan_bus() method for PCI domains.
1205 * @param dev Pointer to the domain.
1206 * @param max The highest bus number assigned up to now.
1207 * @return The maximum bus number found, after scanning all subordinate busses.
1209 unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
1211 max = pci_scan_bus(dev->link_list, PCI_DEVFN(0, 0), 0xff, max);
1215 #if CONFIG_PC80_SYSTEM == 1
1217 * Assign IRQ numbers.
1219 * This function assigns IRQs for all functions contained within the indicated
1220 * device address. If the device does not exist or does not require interrupts
1221 * then this function has no effect.
1223 * This function should be called for each PCI slot in your system.
1225 * @param bus Pointer to the bus structure.
1227 * @param pIntAtoD An array of IRQ #s that are assigned to PINTA through PINTD
1228 * of this slot. The particular IRQ #s that are passed in depend on the
1229 * routing inside your southbridge and on your board.
1231 void pci_assign_irqs(unsigned bus, unsigned slot,
1232 const unsigned char pIntAtoD[4])
1238 /* Each slot may contain up to eight functions. */
1239 for (funct = 0; funct < 8; funct++) {
1240 pdev = dev_find_slot(bus, (slot << 3) + funct);
1245 line = pci_read_config8(pdev, PCI_INTERRUPT_PIN);
1247 /* PCI spec says all values except 1..4 are reserved. */
1248 if ((line < 1) || (line > 4))
1251 irq = pIntAtoD[line - 1];
1253 printk(BIOS_DEBUG, "Assigning IRQ %d to %d:%x.%d\n",
1254 irq, bus, slot, funct);
1256 pci_write_config8(pdev, PCI_INTERRUPT_LINE,
1257 pIntAtoD[line - 1]);
1259 #ifdef PARANOID_IRQ_ASSIGNMENTS
1260 irq = pci_read_config8(pdev, PCI_INTERRUPT_LINE);
1261 printk(BIOS_DEBUG, " Readback = %d\n", irq);
1264 #if CONFIG_PC80_SYSTEM == 1
1265 /* Change to level triggered. */
1266 i8259_configure_irq_trigger(pIntAtoD[line - 1],
1267 IRQ_LEVEL_TRIGGERED);