2 * This file is part of the coreboot project.
4 * It was originally based on the Linux kernel (drivers/pci/pci.c).
7 * Copyright (C) 2003-2004 Linux Networx
8 * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
9 * Copyright (C) 2003-2006 Ronald G. Minnich <rminnich@gmail.com>
10 * Copyright (C) 2004-2005 Li-Ta Lo <ollie@lanl.gov>
11 * Copyright (C) 2005-2006 Tyan
12 * (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
13 * Copyright (C) 2005-2009 coresystems GmbH
14 * (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
18 * PCI Bus Services, see include/linux/pci.h for further explanation.
20 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
21 * David Mosberger-Tang
23 * Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
26 #include <console/console.h>
32 #include <device/device.h>
33 #include <device/pci.h>
34 #include <device/pci_ids.h>
35 #include <part/hard_reset.h>
36 #include <part/fallback_boot.h>
38 #if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1
39 #include <device/hypertransport.h>
41 #if CONFIG_PCIX_PLUGIN_SUPPORT == 1
42 #include <device/pcix.h>
44 #if CONFIG_PCIEXP_PLUGIN_SUPPORT == 1
45 #include <device/pciexp.h>
47 #if CONFIG_AGP_PLUGIN_SUPPORT == 1
48 #include <device/agp.h>
50 #if CONFIG_CARDBUS_PLUGIN_SUPPORT == 1
51 #include <device/cardbus.h>
53 #define CONFIG_PC80_SYSTEM 1
54 #if CONFIG_PC80_SYSTEM == 1
55 #include <pc80/i8259.h>
58 u8 pci_moving_config8(struct device *dev, unsigned int reg)
60 u8 value, ones, zeroes;
61 value = pci_read_config8(dev, reg);
63 pci_write_config8(dev, reg, 0xff);
64 ones = pci_read_config8(dev, reg);
66 pci_write_config8(dev, reg, 0x00);
67 zeroes = pci_read_config8(dev, reg);
69 pci_write_config8(dev, reg, value);
74 u16 pci_moving_config16(struct device * dev, unsigned int reg)
76 u16 value, ones, zeroes;
77 value = pci_read_config16(dev, reg);
79 pci_write_config16(dev, reg, 0xffff);
80 ones = pci_read_config16(dev, reg);
82 pci_write_config16(dev, reg, 0x0000);
83 zeroes = pci_read_config16(dev, reg);
85 pci_write_config16(dev, reg, value);
90 u32 pci_moving_config32(struct device * dev, unsigned int reg)
92 u32 value, ones, zeroes;
93 value = pci_read_config32(dev, reg);
95 pci_write_config32(dev, reg, 0xffffffff);
96 ones = pci_read_config32(dev, reg);
98 pci_write_config32(dev, reg, 0x00000000);
99 zeroes = pci_read_config32(dev, reg);
101 pci_write_config32(dev, reg, value);
103 return ones ^ zeroes;
107 * Given a device, a capability type, and a last position, return the next
108 * matching capability. Always start at the head of the list.
110 * @param dev Pointer to the device structure.
111 * @param cap_type PCI_CAP_LIST_ID of the PCI capability we're looking for.
112 * @param last Location of the PCI capability register to start from.
114 unsigned pci_find_next_capability(struct device *dev, unsigned cap,
121 status = pci_read_config16(dev, PCI_STATUS);
122 if (!(status & PCI_STATUS_CAP_LIST)) {
125 switch (dev->hdr_type & 0x7f) {
126 case PCI_HEADER_TYPE_NORMAL:
127 case PCI_HEADER_TYPE_BRIDGE:
128 pos = PCI_CAPABILITY_LIST;
130 case PCI_HEADER_TYPE_CARDBUS:
131 pos = PCI_CB_CAPABILITY_LIST;
136 pos = pci_read_config8(dev, pos);
137 while (reps-- && (pos >= 0x40)) { /* Loop through the linked list. */
140 this_cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID);
141 printk_spew("Capability: type 0x%02x @ 0x%02x\n", this_cap,
143 if (this_cap == 0xff) {
146 if (!last && (this_cap == cap)) {
152 pos = pci_read_config8(dev, pos + PCI_CAP_LIST_NEXT);
158 * Given a device, and a capability type, return the next matching
159 * capability. Always start at the head of the list.
161 * @param dev Pointer to the device structure.
162 * @param cap_type PCI_CAP_LIST_ID of the PCI capability we're looking for.
164 unsigned pci_find_capability(device_t dev, unsigned cap)
166 return pci_find_next_capability(dev, cap, 0);
170 * Given a device and register, read the size of the BAR for that register.
172 * @param dev Pointer to the device structure.
173 * @param index Address of the PCI configuration register.
175 struct resource *pci_get_resource(struct device *dev, unsigned long index)
177 struct resource *resource;
178 unsigned long value, attr;
179 resource_t moving, limit;
181 /* Initialize the resources to nothing. */
182 resource = new_resource(dev, index);
184 /* Get the initial value. */
185 value = pci_read_config32(dev, index);
187 /* See which bits move. */
188 moving = pci_moving_config32(dev, index);
190 /* Initialize attr to the bits that do not move. */
191 attr = value & ~moving;
193 /* If it is a 64bit resource look at the high half as well. */
194 if (((attr & PCI_BASE_ADDRESS_SPACE_IO) == 0) &&
195 ((attr & PCI_BASE_ADDRESS_MEM_LIMIT_MASK) ==
196 PCI_BASE_ADDRESS_MEM_LIMIT_64)) {
197 /* Find the high bits that move. */
199 ((resource_t) pci_moving_config32(dev, index + 4)) << 32;
201 /* Find the resource constraints.
202 * Start by finding the bits that move. From there:
203 * - Size is the least significant bit of the bits that move.
204 * - Limit is all of the bits that move plus all of the lower bits.
205 * See PCI Spec 6.2.5.1.
210 resource->align = resource->gran = 0;
211 while (!(moving & resource->size)) {
212 resource->size <<= 1;
213 resource->align += 1;
216 resource->limit = limit = moving | (resource->size - 1);
219 /* Some broken hardware has read-only registers that do not
220 * really size correctly.
221 * Example: the Acer M7229 has BARs 1-4 normally read-only.
222 * so BAR1 at offset 0x10 reads 0x1f1. If you size that register
223 * by writing 0xffffffff to it, it will read back as 0x1f1 -- a
224 * violation of the spec.
225 * We catch this case and ignore it by observing which bits move,
226 * This also catches the common case unimplemented registers
227 * that always read back as 0.
232 ("%s register %02lx(%08lx), read-only ignoring it\n",
233 dev_path(dev), index, value);
236 } else if (attr & PCI_BASE_ADDRESS_SPACE_IO) {
237 /* An I/O mapped base address. */
238 attr &= PCI_BASE_ADDRESS_IO_ATTR_MASK;
239 resource->flags |= IORESOURCE_IO;
240 /* I don't want to deal with 32bit I/O resources. */
241 resource->limit = 0xffff;
243 /* A Memory mapped base address. */
244 attr &= PCI_BASE_ADDRESS_MEM_ATTR_MASK;
245 resource->flags |= IORESOURCE_MEM;
246 if (attr & PCI_BASE_ADDRESS_MEM_PREFETCH) {
247 resource->flags |= IORESOURCE_PREFETCH;
249 attr &= PCI_BASE_ADDRESS_MEM_LIMIT_MASK;
250 if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_32) {
252 resource->limit = 0xffffffffUL;
253 } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_1M) {
255 resource->limit = 0x000fffffUL;
256 } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_64) {
258 resource->limit = 0xffffffffffffffffULL;
259 resource->flags |= IORESOURCE_PCI64;
262 printk_err("Broken BAR with value %lx\n", attr);
263 printk_err(" on dev %s at index %02lx\n",
264 dev_path(dev), index);
268 /* Don't let the limit exceed which bits can move. */
269 if (resource->limit > limit) {
270 resource->limit = limit;
277 * Given a device and an index, read the size of the BAR for that register.
279 * @param dev Pointer to the device structure.
280 * @param index Address of the PCI configuration register.
282 static void pci_get_rom_resource(struct device *dev, unsigned long index)
284 struct resource *resource;
288 if ((dev->on_mainboard) && (dev->rom_address == 0)) {
289 /* Skip it if rom_address is not set in the MB Config.lb. */
293 /* Initialize the resources to nothing. */
294 resource = new_resource(dev, index);
296 /* Get the initial value. */
297 value = pci_read_config32(dev, index);
299 /* See which bits move. */
300 moving = pci_moving_config32(dev, index);
302 /* Clear the Enable bit. */
303 moving = moving & ~PCI_ROM_ADDRESS_ENABLE;
305 /* Find the resource constraints.
306 * Start by finding the bits that move. From there:
307 * - Size is the least significant bit of the bits that move.
308 * - Limit is all of the bits that move plus all of the lower bits.
309 * See PCI Spec 6.2.5.1.
313 resource->align = resource->gran = 0;
314 while (!(moving & resource->size)) {
315 resource->size <<= 1;
316 resource->align += 1;
319 resource->limit = moving | (resource->size - 1);
320 resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY;
324 ("%s register %02lx(%08lx), read-only ignoring it\n",
325 dev_path(dev), index, value);
330 /* For on board device with embedded ROM image, the ROM image is at
331 * fixed address specified in the Config.lb, the dev->rom_address is
332 * inited by driver_pci_onboard_ops::enable_dev() */
333 if ((dev->on_mainboard) && (dev->rom_address != 0)) {
334 resource->base = dev->rom_address;
335 resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY |
336 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
339 compact_resources(dev);
343 * Read the base address registers for a given device.
345 * @param dev Pointer to the dev structure.
346 * @param howmany How many registers to read (6 for device, 2 for bridge).
348 static void pci_read_bases(struct device *dev, unsigned int howmany)
352 for (index = PCI_BASE_ADDRESS_0;
353 (index < PCI_BASE_ADDRESS_0 + (howmany << 2));) {
354 struct resource *resource;
355 resource = pci_get_resource(dev, index);
356 index += (resource->flags & IORESOURCE_PCI64) ? 8 : 4;
359 compact_resources(dev);
362 static void pci_record_bridge_resource(struct device *dev, resource_t moving,
363 unsigned index, unsigned long type)
365 /* Initialize the constraints on the current bus. */
366 struct resource *resource;
371 resource = new_resource(dev, index);
375 while ((moving & step) == 0) {
379 resource->gran = gran;
380 resource->align = gran;
381 resource->limit = moving | (step - 1);
382 resource->flags = type | IORESOURCE_PCI_BRIDGE |
388 static void pci_bridge_read_bases(struct device *dev)
390 resource_t moving_base, moving_limit, moving;
392 /* See if the bridge I/O resources are implemented. */
393 moving_base = ((u32) pci_moving_config8(dev, PCI_IO_BASE)) << 8;
395 ((u32) pci_moving_config16(dev, PCI_IO_BASE_UPPER16)) << 16;
397 moving_limit = ((u32) pci_moving_config8(dev, PCI_IO_LIMIT)) << 8;
399 ((u32) pci_moving_config16(dev, PCI_IO_LIMIT_UPPER16)) << 16;
401 moving = moving_base & moving_limit;
403 /* Initialize the I/O space constraints on the current bus. */
404 pci_record_bridge_resource(dev, moving, PCI_IO_BASE, IORESOURCE_IO);
406 /* See if the bridge prefmem resources are implemented. */
408 ((resource_t) pci_moving_config16(dev, PCI_PREF_MEMORY_BASE)) << 16;
410 ((resource_t) pci_moving_config32(dev, PCI_PREF_BASE_UPPER32)) <<
414 ((resource_t) pci_moving_config16(dev, PCI_PREF_MEMORY_LIMIT)) <<
417 ((resource_t) pci_moving_config32(dev, PCI_PREF_LIMIT_UPPER32)) <<
420 moving = moving_base & moving_limit;
421 /* Initialize the prefetchable memory constraints on the current bus. */
422 pci_record_bridge_resource(dev, moving, PCI_PREF_MEMORY_BASE,
423 IORESOURCE_MEM | IORESOURCE_PREFETCH);
425 /* See if the bridge mem resources are implemented. */
426 moving_base = ((u32) pci_moving_config16(dev, PCI_MEMORY_BASE)) << 16;
427 moving_limit = ((u32) pci_moving_config16(dev, PCI_MEMORY_LIMIT)) << 16;
429 moving = moving_base & moving_limit;
431 /* Initialize the memory resources on the current bus. */
432 pci_record_bridge_resource(dev, moving, PCI_MEMORY_BASE,
435 compact_resources(dev);
438 void pci_dev_read_resources(struct device *dev)
440 pci_read_bases(dev, 6);
441 pci_get_rom_resource(dev, PCI_ROM_ADDRESS);
444 void pci_bus_read_resources(struct device *dev)
446 pci_bridge_read_bases(dev);
447 pci_read_bases(dev, 2);
448 pci_get_rom_resource(dev, PCI_ROM_ADDRESS1);
451 void pci_domain_read_resources(struct device *dev)
453 struct resource *res;
455 /* Initialize the system-wide I/O space constraints. */
456 res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
457 res->limit = 0xffffUL;
458 res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
461 /* Initialize the system-wide memory resources constraints. */
462 res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
463 res->limit = 0xffffffffULL;
464 res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
468 static void pci_set_resource(struct device *dev, struct resource *resource)
470 resource_t base, end;
472 /* Make certain the resource has actually been assigned a value. */
473 if (!(resource->flags & IORESOURCE_ASSIGNED)) {
474 printk_err("ERROR: %s %02lx %s size: 0x%010llx not assigned\n",
475 dev_path(dev), resource->index,
476 resource_type(resource), resource->size);
480 /* If I have already stored this resource don't worry about it. */
481 if (resource->flags & IORESOURCE_STORED) {
485 /* If the resource is subtractive don't worry about it. */
486 if (resource->flags & IORESOURCE_SUBTRACTIVE) {
490 /* Only handle PCI memory and I/O resources for now. */
491 if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
494 /* Enable the resources in the command register. */
495 if (resource->size) {
496 if (resource->flags & IORESOURCE_MEM) {
497 dev->command |= PCI_COMMAND_MEMORY;
499 if (resource->flags & IORESOURCE_IO) {
500 dev->command |= PCI_COMMAND_IO;
502 if (resource->flags & IORESOURCE_PCI_BRIDGE) {
503 dev->command |= PCI_COMMAND_MASTER;
506 /* Get the base address. */
507 base = resource->base;
510 end = resource_end(resource);
512 /* Now store the resource. */
513 resource->flags |= IORESOURCE_STORED;
515 /* PCI Bridges have no enable bit. They are disabled if the base of
516 * the range is greater than the limit. If the size is zero, disable
517 * by setting the base = limit and end = limit - 2^gran.
519 if (resource->size == 0 && (resource->flags & IORESOURCE_PCI_BRIDGE)) {
520 base = resource->limit;
521 end = resource->limit - (1 << resource->gran);
522 resource->base = base;
525 if (!(resource->flags & IORESOURCE_PCI_BRIDGE)) {
526 unsigned long base_lo, base_hi;
527 /* Some chipsets allow us to set/clear the I/O bit
528 * (e.g. VIA 82c686a). So set it to be safe.
530 base_lo = base & 0xffffffff;
531 base_hi = (base >> 32) & 0xffffffff;
532 if (resource->flags & IORESOURCE_IO) {
533 base_lo |= PCI_BASE_ADDRESS_SPACE_IO;
535 pci_write_config32(dev, resource->index, base_lo);
536 if (resource->flags & IORESOURCE_PCI64) {
537 pci_write_config32(dev, resource->index + 4, base_hi);
539 } else if (resource->index == PCI_IO_BASE) {
540 /* Set the I/O ranges. */
541 pci_write_config8(dev, PCI_IO_BASE, base >> 8);
542 pci_write_config16(dev, PCI_IO_BASE_UPPER16, base >> 16);
543 pci_write_config8(dev, PCI_IO_LIMIT, end >> 8);
544 pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, end >> 16);
545 } else if (resource->index == PCI_MEMORY_BASE) {
546 /* Set the memory range. */
547 pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);
548 pci_write_config16(dev, PCI_MEMORY_LIMIT, end >> 16);
549 } else if (resource->index == PCI_PREF_MEMORY_BASE) {
550 /* Set the prefetchable memory range. */
551 pci_write_config16(dev, PCI_PREF_MEMORY_BASE, base >> 16);
552 pci_write_config32(dev, PCI_PREF_BASE_UPPER32, base >> 32);
553 pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, end >> 16);
554 pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, end >> 32);
556 /* Don't let me think I stored the resource. */
557 resource->flags &= ~IORESOURCE_STORED;
558 printk_err("ERROR: invalid resource->index %lx\n",
561 report_resource_stored(dev, resource, "");
565 void pci_dev_set_resources(struct device *dev)
567 struct resource *resource, *last;
571 last = &dev->resource[dev->resources];
573 for (resource = &dev->resource[0]; resource < last; resource++) {
574 pci_set_resource(dev, resource);
576 for (link = 0; link < dev->links; link++) {
578 bus = &dev->link[link];
580 assign_resources(bus);
584 /* Set a default latency timer. */
585 pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
587 /* Set a default secondary latency timer. */
588 if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
589 pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
592 /* Zero the IRQ settings. */
593 line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
595 pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
597 /* Set the cache line size, so far 64 bytes is good for everyone. */
598 pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
601 void pci_dev_enable_resources(struct device *dev)
603 const struct pci_operations *ops;
606 /* Set the subsystem vendor and device id for mainboard devices. */
608 if (dev->on_mainboard && ops && ops->set_subsystem) {
609 printk_debug("%s subsystem <- %02x/%02x\n",
611 CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
612 CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
613 ops->set_subsystem(dev,
614 CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
615 CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
617 command = pci_read_config16(dev, PCI_COMMAND);
618 command |= dev->command;
620 * command |= (PCI_COMMAND_PARITY + PCI_COMMAND_SERR); // Error check.
622 printk_debug("%s cmd <- %02x\n", dev_path(dev), command);
623 pci_write_config16(dev, PCI_COMMAND, command);
626 void pci_bus_enable_resources(struct device *dev)
630 /* Enable I/O in command register if there is VGA card
631 * connected with (even it does not claim I/O resource).
633 if (dev->link[0].bridge_ctrl & PCI_BRIDGE_CTL_VGA)
634 dev->command |= PCI_COMMAND_IO;
635 ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
636 ctrl |= dev->link[0].bridge_ctrl;
637 ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* Error check. */
638 printk_debug("%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
639 pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
641 pci_dev_enable_resources(dev);
642 enable_childrens_resources(dev);
645 void pci_bus_reset(struct bus *bus)
648 ctl = pci_read_config16(bus->dev, PCI_BRIDGE_CONTROL);
649 ctl |= PCI_BRIDGE_CTL_BUS_RESET;
650 pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, ctl);
652 ctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
653 pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, ctl);
657 void pci_dev_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
659 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
660 ((device & 0xffff) << 16) | (vendor & 0xffff));
663 /** default handler: only runs the relevant pci bios. */
664 void pci_dev_init(struct device *dev)
666 #if CONFIG_PCI_ROM_RUN == 1 || CONFIG_VGA_ROM_RUN == 1
667 void run_bios(struct device *dev, unsigned long addr);
668 struct rom_header *rom, *ram;
670 #if CONFIG_PCI_ROM_RUN != 1
671 /* We want to execute VGA option ROMs when CONFIG_VGA_ROM_RUN
672 * is set but CONFIG_PCI_ROM_RUN is not. In this case we skip
673 * all other option ROM types.
675 if ((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA)
679 rom = pci_rom_probe(dev);
683 ram = pci_rom_load(dev, rom);
687 run_bios(dev, (unsigned long)ram);
689 #if CONFIG_CONSOLE_VGA == 1
690 if ((dev->class>>8) == PCI_CLASS_DISPLAY_VGA)
692 #endif /* CONFIG_CONSOLE_VGA */
693 #endif /* CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN */
696 /** Default device operation for PCI devices */
697 static struct pci_operations pci_dev_ops_pci = {
698 .set_subsystem = pci_dev_set_subsystem,
701 struct device_operations default_pci_ops_dev = {
702 .read_resources = pci_dev_read_resources,
703 .set_resources = pci_dev_set_resources,
704 .enable_resources = pci_dev_enable_resources,
705 .init = pci_dev_init,
708 .ops_pci = &pci_dev_ops_pci,
711 /** Default device operations for PCI bridges */
712 static struct pci_operations pci_bus_ops_pci = {
716 struct device_operations default_pci_ops_bus = {
717 .read_resources = pci_bus_read_resources,
718 .set_resources = pci_dev_set_resources,
719 .enable_resources = pci_bus_enable_resources,
721 .scan_bus = pci_scan_bridge,
723 .reset_bus = pci_bus_reset,
724 .ops_pci = &pci_bus_ops_pci,
728 * @brief Detect the type of downstream bridge
730 * This function is a heuristic to detect which type of bus is downstream
731 * of a PCI-to-PCI bridge. This functions by looking for various capability
732 * blocks to figure out the type of downstream bridge. PCI-X, PCI-E, and
733 * Hypertransport all seem to have appropriate capabilities.
735 * When only a PCI-Express capability is found the type
736 * is examined to see which type of bridge we have.
738 * @param dev Pointer to the device structure of the bridge.
739 * @return Appropriate bridge operations.
741 static struct device_operations *get_pci_bridge_ops(device_t dev)
745 #if CONFIG_PCIX_PLUGIN_SUPPORT == 1
746 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
748 printk_debug("%s subbordinate bus PCI-X\n", dev_path(dev));
749 return &default_pcix_ops_bus;
752 #if CONFIG_AGP_PLUGIN_SUPPORT == 1
753 /* How do I detect an PCI to AGP bridge? */
755 #if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1
757 while ((pos = pci_find_next_capability(dev, PCI_CAP_ID_HT, pos))) {
759 flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
760 if ((flags >> 13) == 1) {
761 /* Host or Secondary Interface */
762 printk_debug("%s subbordinate bus Hypertransport\n",
764 return &default_ht_ops_bus;
768 #if CONFIG_PCIEXP_PLUGIN_SUPPORT == 1
769 pos = pci_find_capability(dev, PCI_CAP_ID_PCIE);
772 flags = pci_read_config16(dev, pos + PCI_EXP_FLAGS);
773 switch ((flags & PCI_EXP_FLAGS_TYPE) >> 4) {
774 case PCI_EXP_TYPE_ROOT_PORT:
775 case PCI_EXP_TYPE_UPSTREAM:
776 case PCI_EXP_TYPE_DOWNSTREAM:
777 printk_debug("%s subbordinate bus PCI Express\n",
779 return &default_pciexp_ops_bus;
780 case PCI_EXP_TYPE_PCI_BRIDGE:
781 printk_debug("%s subbordinate PCI\n", dev_path(dev));
782 return &default_pci_ops_bus;
788 return &default_pci_ops_bus;
792 * Set up PCI device operation. Check if it already has a driver. If not, use
793 * find_device_operations, or set to a default based on type.
795 * @param dev Pointer to the device whose pci_ops you want to set.
798 static void set_pci_ops(struct device *dev)
800 struct pci_driver *driver;
805 /* Look through the list of setup drivers and find one for
808 for (driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) {
809 if ((driver->vendor == dev->vendor) &&
810 (driver->device == dev->device)) {
811 dev->ops = driver->ops;
812 printk_spew("%s [%04x/%04x] %sops\n",
814 driver->vendor, driver->device,
815 (driver->ops->scan_bus ? "bus " : ""));
820 /* If I don't have a specific driver use the default operations */
821 switch (dev->hdr_type & 0x7f) { /* header type */
822 case PCI_HEADER_TYPE_NORMAL: /* standard header */
823 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
825 dev->ops = &default_pci_ops_dev;
827 case PCI_HEADER_TYPE_BRIDGE:
828 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
830 dev->ops = get_pci_bridge_ops(dev);
832 #if CONFIG_CARDBUS_PLUGIN_SUPPORT == 1
833 case PCI_HEADER_TYPE_CARDBUS:
834 dev->ops = &default_cardbus_ops_bus;
840 printk_err("%s [%04x/%04x/%06x] has unknown header "
841 "type %02x, ignoring.\n",
843 dev->vendor, dev->device,
844 dev->class >> 8, dev->hdr_type);
851 * @brief See if we have already allocated a device structure for a given devfn.
853 * Given a linked list of PCI device structures and a devfn number, find the
854 * device structure correspond to the devfn, if present. This function also
855 * removes the device structure from the linked list.
857 * @param list The device structure list.
858 * @param devfn A device/function number.
860 * @return Pointer to the device structure found or NULL if we have not
861 * allocated a device for this devfn yet.
863 static struct device *pci_scan_get_dev(struct device **list, unsigned int devfn)
867 for (; *list; list = &(*list)->sibling) {
868 if ((*list)->path.type != DEVICE_PATH_PCI) {
869 printk_err("child %s not a pci device\n",
873 if ((*list)->path.pci.devfn == devfn) {
874 /* Unlink from the list. */
876 *list = (*list)->sibling;
882 /* Just like alloc_dev() add the device to the list of devices on the
883 * bus. When the list of devices was formed we removed all of the
884 * parents children, and now we are interleaving static and dynamic
885 * devices in order on the bus.
888 struct device *child;
889 /* Find the last child of our parent. */
890 for (child = dev->bus->children; child && child->sibling;) {
891 child = child->sibling;
893 /* Place the device on the list of children of its parent. */
895 child->sibling = dev;
897 dev->bus->children = dev;
905 * @brief Scan a PCI bus.
907 * Determine the existence of a given PCI device. Allocate a new struct device
908 * if dev==NULL was passed in and the device exists in hardware.
910 * @param bus pointer to the bus structure
911 * @param devfn to look at
913 * @return The device structure for hte device (if found)
914 * or the NULL if no device is found.
916 device_t pci_probe_dev(device_t dev, struct bus * bus, unsigned devfn)
921 /* Detect if a device is present. */
925 dummy.path.type = DEVICE_PATH_PCI;
926 dummy.path.pci.devfn = devfn;
927 id = pci_read_config32(&dummy, PCI_VENDOR_ID);
928 /* Have we found something?
929 * Some broken boards return 0 if a slot is empty.
931 if ((id == 0xffffffff) || (id == 0x00000000) ||
932 (id == 0x0000ffff) || (id == 0xffff0000)) {
933 printk_spew("%s, bad id 0x%x\n", dev_path(&dummy), id);
936 dev = alloc_dev(bus, &dummy.path);
938 /* Enable/disable the device. Once we have found the device-
939 * specific operations this operations we will disable the
940 * device with those as well.
942 * This is geared toward devices that have subfunctions
943 * that do not show up by default.
945 * If a device is a stuff option on the motherboard
946 * it may be absent and enable_dev() must cope.
948 /* Run the magic enable sequence for the device. */
949 if (dev->chip_ops && dev->chip_ops->enable_dev) {
950 dev->chip_ops->enable_dev(dev);
952 /* Now read the vendor and device ID. */
953 id = pci_read_config32(dev, PCI_VENDOR_ID);
955 /* If the device does not have a PCI ID disable it. Possibly
956 * this is because we have already disabled the device. But
957 * this also handles optional devices that may not always
960 /* If the chain is fully enumerated quit */
961 if ((id == 0xffffffff) || (id == 0x00000000) ||
962 (id == 0x0000ffff) || (id == 0xffff0000)) {
964 printk_info("Disabling static device: %s\n",
971 /* Read the rest of the PCI configuration information. */
972 hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
973 class = pci_read_config32(dev, PCI_CLASS_REVISION);
975 /* Store the interesting information in the device structure. */
976 dev->vendor = id & 0xffff;
977 dev->device = (id >> 16) & 0xffff;
978 dev->hdr_type = hdr_type;
980 /* Class code, the upper 3 bytes of PCI_CLASS_REVISION. */
981 dev->class = class >> 8;
983 /* Architectural/System devices always need to be bus masters. */
984 if ((dev->class >> 16) == PCI_BASE_CLASS_SYSTEM) {
985 dev->command |= PCI_COMMAND_MASTER;
987 /* Look at the vendor and device ID, or at least the header type and
988 * class and figure out which set of configuration methods to use.
989 * Unless we already have some PCI ops.
993 /* Now run the magic enable/disable sequence for the device. */
994 if (dev->ops && dev->ops->enable) {
995 dev->ops->enable(dev);
998 /* Display the device. */
999 printk_debug("%s [%04x/%04x] %s%s\n",
1001 dev->vendor, dev->device,
1002 dev->enabled ? "enabled" : "disabled",
1003 dev->ops ? "" : " No operations");
1009 * @brief Scan a PCI bus.
1011 * Determine the existence of devices and bridges on a PCI bus. If there are
1012 * bridges on the bus, recursively scan the buses behind the bridges.
1014 * This function is the default scan_bus() method for the root device
1017 * @param bus pointer to the bus structure
1018 * @param min_devfn minimum devfn to look at in the scan usually 0x00
1019 * @param max_devfn maximum devfn to look at in the scan usually 0xff
1020 * @param max current bus number
1022 * @return The maximum bus number found, after scanning all subordinate busses
1024 unsigned int pci_scan_bus(struct bus *bus,
1025 unsigned min_devfn, unsigned max_devfn,
1029 struct device *old_devices;
1030 struct device *child;
1032 #if CONFIG_PCI_BUS_SEGN_BITS
1033 printk_debug("PCI: pci_scan_bus for bus %04x:%02x\n",
1034 bus->secondary >> 8, bus->secondary & 0xff);
1036 printk_debug("PCI: pci_scan_bus for bus %02x\n", bus->secondary);
1039 old_devices = bus->children;
1040 bus->children = NULL;
1043 /* Probe all devices/functions on this bus with some optimization for
1044 * non-existence and single function devices.
1046 for (devfn = min_devfn; devfn <= max_devfn; devfn++) {
1049 /* First thing setup the device structure */
1050 dev = pci_scan_get_dev(&old_devices, devfn);
1052 /* See if a device is present and setup the device structure. */
1053 dev = pci_probe_dev(dev, bus, devfn);
1055 /* If this is not a multi function device, or the device is
1056 * not present don't waste time probing another function.
1057 * Skip to next device.
1059 if ((PCI_FUNC(devfn) == 0x00) &&
1061 || (dev->enabled && ((dev->hdr_type & 0x80) != 0x80)))) {
1067 /* Warn if any leftover static devices are are found.
1068 * There's probably a problem in the Config.lb.
1072 printk_warning("PCI: Left over static devices:\n");
1073 for (left = old_devices; left; left = left->sibling) {
1074 printk_warning("%s\n", dev_path(left));
1076 printk_warning("PCI: Check your mainboard Config.lb.\n");
1079 /* For all children that implement scan_bus() (i.e. bridges)
1080 * scan the bus behind that child.
1082 for (child = bus->children; child; child = child->sibling) {
1083 max = scan_bus(child, max);
1086 /* We've scanned the bus and so we know all about what's on the other
1087 * side of any bridges that may be on this bus plus any devices.
1088 * Return how far we've got finding sub-buses.
1090 printk_debug("PCI: pci_scan_bus returning with max=%03x\n", max);
1096 * @brief Scan a PCI bridge and the buses behind the bridge.
1098 * Determine the existence of buses behind the bridge. Set up the bridge
1099 * according to the result of the scan.
1101 * This function is the default scan_bus() method for PCI bridge devices.
1103 * @param dev Pointer to the bridge device.
1104 * @param max The highest bus number assigned up to now.
1105 * @return The maximum bus number found, after scanning all subordinate buses.
1107 unsigned int do_pci_scan_bridge(struct device *dev, unsigned int max,
1108 unsigned int (*do_scan_bus) (struct bus * bus,
1117 printk_spew("%s for %s\n", __func__, dev_path(dev));
1119 bus = &dev->link[0];
1123 /* Set up the primary, secondary and subordinate bus numbers. We have
1124 * no idea how many buses are behind this bridge yet, so we set the
1125 * subordinate bus number to 0xff for the moment.
1127 bus->secondary = ++max;
1128 bus->subordinate = 0xff;
1130 /* Clear all status bits and turn off memory, I/O and master enables. */
1131 cr = pci_read_config16(dev, PCI_COMMAND);
1132 pci_write_config16(dev, PCI_COMMAND, 0x0000);
1133 pci_write_config16(dev, PCI_STATUS, 0xffff);
1135 /* Read the existing primary/secondary/subordinate bus
1136 * number configuration.
1138 buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
1140 /* Configure the bus numbers for this bridge: the configuration
1141 * transactions will not be propagated by the bridge if it is not
1142 * correctly configured.
1144 buses &= 0xff000000;
1145 buses |= (((unsigned int)(dev->bus->secondary) << 0) |
1146 ((unsigned int)(bus->secondary) << 8) |
1147 ((unsigned int)(bus->subordinate) << 16));
1148 pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
1150 /* Now we can scan all subordinate buses
1151 * i.e. the bus behind the bridge.
1153 max = do_scan_bus(bus, 0x00, 0xff, max);
1155 /* We know the number of buses behind this bridge. Set the subordinate
1156 * bus number to its real value.
1158 bus->subordinate = max;
1159 buses = (buses & 0xff00ffff) | ((unsigned int)(bus->subordinate) << 16);
1160 pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
1161 pci_write_config16(dev, PCI_COMMAND, cr);
1163 printk_spew("%s returns max %d\n", __func__, max);
1168 * @brief Scan a PCI bridge and the buses behind the bridge.
1170 * Determine the existence of buses behind the bridge. Set up the bridge
1171 * according to the result of the scan.
1173 * This function is the default scan_bus() method for PCI bridge devices.
1175 * @param dev Pointer to the bridge device.
1176 * @param max The highest bus number assigned up to now.
1177 * @return The maximum bus number found, after scanning all subordinate buses.
1179 unsigned int pci_scan_bridge(struct device *dev, unsigned int max)
1181 return do_pci_scan_bridge(dev, max, pci_scan_bus);
1185 * @brief Scan a PCI domain.
1187 * This function is the default scan_bus() method for PCI domains.
1189 * @param dev pointer to the domain
1190 * @param max the highest bus number assgined up to now
1192 * @return The maximum bus number found, after scanning all subordinate busses
1194 unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
1196 max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
1200 #if CONFIG_PC80_SYSTEM == 1
1203 * @brief Assign IRQ numbers
1205 * This function assigns IRQs for all functions contained within the indicated
1206 * device address. If the device does not exist or does not require interrupts
1207 * then this function has no effect.
1209 * This function should be called for each PCI slot in your system.
1213 * @param pIntAtoD is an array of IRQ #s that are assigned to PINTA through
1214 * PINTD of this slot. The particular irq #s that are passed in
1215 * depend on the routing inside your southbridge and on your
1218 void pci_assign_irqs(unsigned bus, unsigned slot,
1219 const unsigned char pIntAtoD[4])
1227 /* Each slot may contain up to eight functions */
1228 for (funct = 0; funct < 8; funct++) {
1229 pdev = dev_find_slot(bus, (slot << 3) + funct);
1234 line = pci_read_config8(pdev, PCI_INTERRUPT_PIN);
1236 // PCI spec says all values except 1..4 are reserved.
1237 if ((line < 1) || (line > 4))
1240 irq = pIntAtoD[line - 1];
1242 printk_debug("Assigning IRQ %d to %d:%x.%d\n",
1243 irq, bus, slot, funct);
1245 pci_write_config8(pdev, PCI_INTERRUPT_LINE,
1246 pIntAtoD[line - 1]);
1248 #ifdef PARANOID_IRQ_ASSIGNMENTS
1249 readback = pci_read_config8(pdev, PCI_INTERRUPT_LINE);
1250 printk_debug(" Readback = %d\n", readback);
1253 // Change to level triggered
1254 i8259_configure_irq_trigger(pIntAtoD[line - 1], IRQ_LEVEL_TRIGGERED);