2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
9 * Copyright 2003 -- Eric Biederman <ebiederman@lnxi.com>
12 #include <console/console.h>
18 #include <device/device.h>
19 #include <device/pci.h>
20 #include <device/pci_ids.h>
21 #include <device/chip.h>
22 #include <part/hard_reset.h>
23 #include <part/fallback_boot.h>
25 /** Given a device and register, read the size of the BAR for that register.
26 * @param dev Pointer to the device structure
27 * @param resource Pointer to the resource structure
28 * @param index Address of the pci configuration register
30 static struct resource *pci_get_resource(struct device *dev, unsigned long index)
32 struct resource *resource;
33 uint32_t addr, size, base;
36 /* Initialize the resources to nothing */
37 resource = get_resource(dev, index);
39 addr = pci_read_config32(dev, index);
41 /* FIXME: more consideration for 64-bit PCI devices,
42 * we currently detect their size but otherwise
43 * treat them as 32-bit resources
46 pci_write_config32(dev, index, ~0);
47 size = pci_read_config32(dev, index);
49 /* get the minimum value the bar can be set to */
50 pci_write_config32(dev, index, 0);
51 base = pci_read_config32(dev, index);
54 pci_write_config32(dev, index, addr);
57 * some broken hardware has read-only registers that do not
58 * really size correctly. You can tell this if addr == size
59 * Example: the acer m7229 has BARs 1-4 normally read-only.
60 * so BAR1 at offset 0x10 reads 0x1f1. If you size that register
61 * by writing 0xffffffff to it, it will read back as 0x1f1 -- a
62 * violation of the spec.
63 * We catch this case and ignore it by settting size and type to 0.
64 * This incidentally catches the common case where registers
65 * read back as 0 for both address and size.
67 if ((addr == size) && (addr == base)) {
70 "%s register %02x(%08x), read-only ignoring it\n",
76 /* Now compute the actual size, See PCI Spec 6.2.5.1 ... */
77 else if (size & PCI_BASE_ADDRESS_SPACE_IO) {
78 type = size & (~PCI_BASE_ADDRESS_IO_MASK);
79 /* BUG! Top 16 bits can be zero (or not)
80 * So set them to 0xffff so they go away ...
82 resource->size = (~((size | 0xffff0000) & PCI_BASE_ADDRESS_IO_MASK)) +1;
83 resource->align = log2(resource->size);
84 resource->gran = resource->align;
85 resource->flags |= IORESOURCE_IO;
86 resource->limit = 0xffff;
89 /* A Memory mapped base address */
90 type = size & (~PCI_BASE_ADDRESS_MEM_MASK);
91 resource->size = (~(size &PCI_BASE_ADDRESS_MEM_MASK)) +1;
92 resource->align = log2(resource->size);
93 resource->gran = resource->align;
94 resource->flags |= IORESOURCE_MEM;
95 if (type & PCI_BASE_ADDRESS_MEM_PREFETCH) {
96 resource->flags |= IORESOURCE_PREFETCH;
98 type &= PCI_BASE_ADDRESS_MEM_TYPE_MASK;
99 if (type == PCI_BASE_ADDRESS_MEM_TYPE_32) {
101 resource->limit = 0xffffffffUL;
103 else if (type == PCI_BASE_ADDRESS_MEM_TYPE_1M) {
105 resource->limit = 0x000fffffUL;
107 else if (type == PCI_BASE_ADDRESS_MEM_TYPE_64) {
108 unsigned long index_hi;
110 * For now just treat this as a 32bit limit
112 index_hi = index + 4;
113 resource->limit = 0xffffffffUL;
114 resource->flags |= IORESOURCE_PCI64;
115 addr = pci_read_config32( dev, index_hi);
116 /* get the extended size */
117 pci_write_config32(dev, index_hi, 0xffffffffUL);
118 size = pci_read_config32( dev, index_hi);
120 /* get the minimum value the bar can be set to */
121 pci_write_config32(dev, index_hi, 0);
122 base = pci_read_config32(dev, index_hi);
125 pci_write_config32(dev, index_hi, addr);
127 if ((size == 0xffffffff) && (base == 0)) {
128 /* Clear the top half of the bar */
129 pci_write_config32(dev, index_hi, 0);
132 printk_err("%s Unable to handle 64-bit address\n",
134 resource->flags = IORESOURCE_PCI64;
142 /* dev->size holds the flags... */
146 /** Read the base address registers for a given device.
147 * @param dev Pointer to the dev structure
148 * @param howmany How many registers to read (6 for device, 2 for bridge)
150 static void pci_read_bases(struct device *dev, unsigned int howmany)
154 for(index = PCI_BASE_ADDRESS_0; (index < PCI_BASE_ADDRESS_0 + (howmany << 2)); ) {
155 struct resource *resource;
156 resource = pci_get_resource(dev, index);
157 index += (resource->flags & IORESOURCE_PCI64)?8:4;
159 compact_resources(dev);
162 static void pci_bridge_read_bases(struct device *dev)
164 struct resource *resource;
166 /* FIXME handle bridges without some of the optional resources */
168 /* Initialize the io space constraints on the current bus */
169 resource = get_resource(dev, PCI_IO_BASE);
171 resource->align = log2(PCI_IO_BRIDGE_ALIGN);
172 resource->gran = log2(PCI_IO_BRIDGE_ALIGN);
173 resource->limit = 0xffffUL;
174 resource->flags |= IORESOURCE_IO | IORESOURCE_PCI_BRIDGE;
175 compute_allocate_resource(&dev->link[0], resource,
176 IORESOURCE_IO, IORESOURCE_IO);
178 /* Initiliaze the prefetchable memory constraints on the current bus */
179 resource = get_resource(dev, PCI_PREF_MEMORY_BASE);
181 resource->align = log2(PCI_MEM_BRIDGE_ALIGN);
182 resource->gran = log2(PCI_MEM_BRIDGE_ALIGN);
183 resource->limit = 0xffffffffUL;
184 resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_PCI_BRIDGE;
185 resource->index = PCI_PREF_MEMORY_BASE;
186 compute_allocate_resource(&dev->link[0], resource,
187 IORESOURCE_MEM | IORESOURCE_PREFETCH,
188 IORESOURCE_MEM | IORESOURCE_PREFETCH);
190 /* Initialize the memory resources on the current bus */
191 resource = get_resource(dev, PCI_MEMORY_BASE);
193 resource->align = log2(PCI_MEM_BRIDGE_ALIGN);
194 resource->gran = log2(PCI_MEM_BRIDGE_ALIGN);
195 resource->limit = 0xffffffffUL;
196 resource->flags = IORESOURCE_MEM | IORESOURCE_PCI_BRIDGE;
197 compute_allocate_resource(&dev->link[0], resource,
198 IORESOURCE_MEM | IORESOURCE_PREFETCH,
201 compact_resources(dev);
204 void pci_dev_read_resources(struct device *dev)
208 pci_read_bases(dev, 6);
210 addr = pci_read_config32(dev, PCI_ROM_ADDRESS);
211 dev->rom_address = (addr == 0xffffffff)? 0 : addr;
214 void pci_bus_read_resources(struct device *dev)
218 pci_bridge_read_bases(dev);
219 pci_read_bases(dev, 2);
221 addr = pci_read_config32(dev, PCI_ROM_ADDRESS1);
222 dev->rom_address = (addr == 0xffffffff)? 0 : addr;
226 * @brief round a number up to the next multiple of gran
227 * @param val the starting value
228 * @param gran granularity we are aligning the number to.
229 * @returns aligned value
231 static unsigned long align(unsigned long val, unsigned long gran)
233 /* GRAN MUST BE A POWER OF TWO. */
241 static void pci_set_resource(struct device *dev, struct resource *resource)
243 unsigned long base, limit;
244 unsigned char buf[10];
247 /* Make certain the resource has actually been set */
248 if (!(resource->flags & IORESOURCE_ASSIGNED)) {
249 printk_err("ERROR: %s %02x not allocated\n",
250 dev_path(dev), resource->index);
254 /* If I have already stored this resource don't worry about it */
255 if (resource->flags & IORESOURCE_STORED) {
259 /* Only handle PCI memory and IO resources for now */
260 if (!(resource->flags & (IORESOURCE_MEM |IORESOURCE_IO)))
263 if (resource->flags & IORESOURCE_MEM) {
264 dev->command |= PCI_COMMAND_MEMORY;
266 if (resource->flags & IORESOURCE_IO) {
267 dev->command |= PCI_COMMAND_IO;
269 if (resource->flags & IORESOURCE_PCI_BRIDGE) {
270 dev->command |= PCI_COMMAND_MASTER;
272 /* Get the base address */
273 base = resource->base;
274 /* Get the resource granularity */
275 gran = 1UL << resource->gran;
277 /* For a non bridge resource granularity and alignment are the same.
278 * For a bridge resource align is the largest needed alignment below
279 * the bridge. While the granularity is simply how many low bits of the
280 * address cannot be set.
283 /* Get the limit (rounded up) */
284 limit = base + align(resource->size, gran) - 1UL;
286 /* Now store the resource */
287 resource->flags |= IORESOURCE_STORED;
288 if (!(resource->flags & IORESOURCE_PCI_BRIDGE)) {
290 * some chipsets allow us to set/clear the IO bit.
291 * (e.g. VIA 82c686a.) So set it to be safe)
293 limit = base + resource->size -1;
294 if (resource->flags & IORESOURCE_IO) {
295 base |= PCI_BASE_ADDRESS_SPACE_IO;
297 pci_write_config32(dev, resource->index, base & 0xffffffff);
298 if (resource->flags & IORESOURCE_PCI64) {
299 /* FIXME handle real 64bit base addresses */
300 pci_write_config32(dev, resource->index + 4, 0);
303 else if (resource->index == PCI_IO_BASE) {
305 * WARNING: we don't really do 32-bit addressing for IO yet!
307 compute_allocate_resource(&dev->link[0], resource,
308 IORESOURCE_IO, IORESOURCE_IO);
309 pci_write_config8(dev, PCI_IO_BASE, base >> 8);
310 pci_write_config8(dev, PCI_IO_LIMIT, limit >> 8);
311 pci_write_config16(dev, PCI_IO_BASE_UPPER16, 0);
312 pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, 0);
314 else if (resource->index == PCI_MEMORY_BASE) {
315 /* set the memory range
317 compute_allocate_resource(&dev->link[0], resource,
318 IORESOURCE_MEM | IORESOURCE_PREFETCH,
320 pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);
321 pci_write_config16(dev, PCI_MEMORY_LIMIT, limit >> 16);
323 else if (resource->index == PCI_PREF_MEMORY_BASE) {
324 /* set the prefetchable memory range
325 * WARNING: we don't really do 64-bit addressing
326 * for prefetchable memory yet!
328 compute_allocate_resource(&dev->link[0], resource,
329 IORESOURCE_MEM | IORESOURCE_PREFETCH,
330 IORESOURCE_MEM | IORESOURCE_PREFETCH);
331 pci_write_config16(dev, PCI_PREF_MEMORY_BASE, base >> 16);
332 pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, limit >> 16);
333 pci_write_config32(dev, PCI_PREF_BASE_UPPER32, 0);
334 pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, 0);
337 /* Don't let me think I stored the resource */
338 resource->flags &= ~IORESOURCE_STORED;
339 printk_err("ERROR: invalid resource->index %x\n",
343 if (resource->flags & IORESOURCE_PCI_BRIDGE) {
344 sprintf(buf, "bus %d ", dev->link[0].secondary);
347 "%s %02x <- [0x%08lx - 0x%08lx] %s%s\n",
350 (unsigned long)(resource->base), limit,
352 (resource->flags & IORESOURCE_IO)? "io":
353 (resource->flags & IORESOURCE_PREFETCH)? "prefmem": "mem");
357 void pci_dev_set_resources(struct device *dev)
359 struct resource *resource, *last;
363 last = &dev->resource[dev->resources];
365 for(resource = &dev->resource[0]; resource < last; resource++) {
366 pci_set_resource(dev, resource);
368 for(link = 0; link < dev->links; link++) {
370 bus = &dev->link[link];
372 assign_resources(bus);
376 /* set a default latency timer */
377 pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
379 /* set a default secondary latency timer */
380 if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
381 pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
384 /* zero the irq settings */
385 line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
387 pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
389 /* set the cache line size, so far 64 bytes is good for everyone */
390 pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
393 void pci_dev_enable_resources(struct device *dev)
396 command = pci_read_config16(dev, PCI_COMMAND);
397 command |= dev->command;
398 command |= (PCI_COMMAND_PARITY + PCI_COMMAND_SERR); /* error check */
399 printk_debug("%s cmd <- %02x\n", dev_path(dev), command);
400 pci_write_config16(dev, PCI_COMMAND, command);
402 enable_childrens_resources(dev);
405 void pci_bus_enable_resources(struct device *dev)
408 ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
409 ctrl |= dev->link[0].bridge_ctrl;
410 ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error check */
411 printk_debug("%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
412 pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
414 pci_dev_enable_resources(dev);
417 /** Default device operation for PCI devices */
418 struct device_operations default_pci_ops_dev = {
419 .read_resources = pci_dev_read_resources,
420 .set_resources = pci_dev_set_resources,
421 .enable_resources = pci_dev_enable_resources,
426 /** Default device operations for PCI bridges */
427 struct device_operations default_pci_ops_bus = {
428 .read_resources = pci_bus_read_resources,
429 .set_resources = pci_dev_set_resources,
430 .enable_resources = pci_bus_enable_resources,
432 .scan_bus = pci_scan_bridge,
436 * @brief Set up PCI device operation
443 static void set_pci_ops(struct device *dev)
445 struct pci_driver *driver;
451 /* Look through the list of setup drivers and find one for
454 for(driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) {
455 if ((driver->vendor == dev->vendor) &&
456 (driver->device == dev->device))
458 dev->ops = driver->ops;
459 printk_debug("%s [%04x/%04x] %sops\n",
461 driver->vendor, driver->device,
462 (driver->ops->scan_bus?"bus ":""));
468 extern struct pci_driver generic_vga_driver;
469 /* TODO: Install generic VGA driver for VGA devices, base on the
471 if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) {
472 printk_debug("setting up generic VGA driver\n");
473 dev->ops = generic_vga_driver.ops;
478 /* If I don't have a specific driver use the default operations */
479 switch(dev->hdr_type & 0x7f) { /* header type */
480 case PCI_HEADER_TYPE_NORMAL: /* standard header */
481 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
483 dev->ops = &default_pci_ops_dev;
485 case PCI_HEADER_TYPE_BRIDGE:
486 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
488 dev->ops = &default_pci_ops_bus;
493 printk_err("%s [%04x/%04x/%06x] has unknown header "
494 "type %02x, ignoring.\n",
496 dev->vendor, dev->device,
497 dev->class >> 8, dev->hdr_type);
504 * @brief Find a specific device structure on a list of device structures
506 * Given a linked list of PCI device structures and a devfn number, find the
507 * device structure correspond to the devfn, if present.
509 * @param list the device structure list
510 * @param devfn a device/function number
512 * @return pointer to the device structure found or null of we have not allocated
513 * a device for this devfn yet.
515 static struct device *pci_scan_get_dev(struct device **list, unsigned int devfn)
519 printk_spew("%s, looking for devfn: %02x.%01x\n", __FUNCTION__,
520 devfn >> 3, devfn & 7);
522 for(; *list; list = &(*list)->sibling) {
523 if ((*list)->path.type != DEVICE_PATH_PCI) {
524 printk_err("child %s not a pci device\n",
528 if ((*list)->path.u.pci.devfn == devfn) {
529 /* Unlink from the list */
531 *list = (*list)->sibling;
536 /* Just like alloc_dev add the device to the
537 * list of device on the bus. When the list of devices was formed
538 * we removed all of the parents children, and now we are interleaving
539 * static and dynamic devices in order on the bus.
541 printk_spew("%s, found dev %08x\n", __FUNCTION__, dev);
544 /* Find the last child of our parent */
545 for(child = dev->bus->children; child && child->sibling; ) {
546 child = child->sibling;
548 /* Place the device on the list of children of it's parent. */
550 child->sibling = dev;
552 dev->bus->children = dev;
560 * @brief Scan a PCI bus.
562 * Determine the existence of devices and bridges on a PCI bus. If there are
563 * bridges on the bus, recursively scan the buses behind the bridges.
565 * This function is the default scan_bus() method for the root device
568 * @param bus pointer to the bus structure
569 * @param min_devfn minimum devfn to look at in the scan usually 0x00
570 * @param max_devfn maximum devfn to look at in the scan usually 0xff
571 * @param max current bus number
573 * @return The maximum bus number found, after scanning all subordinate busses
575 unsigned int pci_scan_bus(struct bus *bus,
576 unsigned min_devfn, unsigned max_devfn,
581 device_t old_devices;
584 printk_debug("PCI: pci_scan_bus for bus %d\n", bus->secondary);
586 old_devices = bus->children;
591 /* probe all devices/functions on this bus with some optimization for
592 * non-existence and single funcion devices
594 for (devfn = min_devfn; devfn <= max_devfn; devfn++) {
598 /* device structures for PCI devices associated with static
599 * devices are already created during the static device
600 * enumeration, find out if it is the case for this devfn */
601 dev = pci_scan_get_dev(&old_devices, devfn);
604 /* it's not associated with a static device, detect if
605 * this device is present */
608 dummy.path.type = DEVICE_PATH_PCI;
609 dummy.path.u.pci.devfn = devfn;
610 id = pci_read_config32(&dummy, PCI_VENDOR_ID);
611 /* some broken boards return 0 if a slot is empty: */
612 if ( (id == 0xffffffff) || (id == 0x00000000) ||
613 (id == 0x0000ffff) || (id == 0xffff0000))
615 printk_spew("PCI: devfn 0x%x, bad id 0x%x\n", devfn, id);
616 if (PCI_FUNC(devfn) == 0x00) {
617 /* if this is a function 0 device and
619 * skip to next device
623 /* This function in a multi function device is
624 * not present, skip to the next function.
628 dev = alloc_dev(bus, &dummy.path);
631 /* If at all possible enable the device, if desired
632 * we will disable the device later, once we have
633 * found it's device specific operations.
635 * This is geared toward devices that have subfunctions
636 * that do not show up by default.
638 * If a device is a stuff option on the motherboard
639 * it may be absent and enable_dev must cope.
642 if ( dev->chip && dev->chip->control &&
643 dev->chip->control->enable_dev)
645 int enabled = dev->enabled;
647 dev->chip->control->enable_dev(dev);
648 dev->enabled = enabled;
650 /* Now read the vendor and device id */
651 id = pci_read_config32(dev, PCI_VENDOR_ID);
653 /* Read the rest of the pci configuration information */
654 hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
655 class = pci_read_config32(dev, PCI_CLASS_REVISION);
657 /* Store the interesting information in the device structure */
658 dev->vendor = id & 0xffff;
659 dev->device = (id >> 16) & 0xffff;
660 dev->hdr_type = hdr_type;
661 /* class code, the upper 3 bytes of PCI_CLASS_REVISION */
662 dev->class = class >> 8;
664 /* Look at the vendor and device id, or at least the
665 * header type and class and figure out which set of
666 * configuration methods to use. Unless we already
670 /* Error if we don't have some pci operations for it */
672 printk_err("%s No device operations\n",
677 /* Now run the magic enable/disable sequence for the device */
678 if (dev->ops && dev->ops->enable) {
679 dev->ops->enable(dev);
681 else if (dev->chip && dev->chip->control &&
682 dev->chip->control->enable_dev)
684 dev->chip->control->enable_dev(dev);
687 printk_debug("%s [%04x/%04x] %s\n",
689 dev->vendor, dev->device,
690 dev->enabled?"enabled": "disabled");
692 if (PCI_FUNC(devfn) == 0x00 && (hdr_type & 0x80) != 0x80) {
693 /* if this is not a multi function device,
694 * don't waste time probing another function.
695 * Skip to next device.
702 /* For all children that implement scan_bus (i.e. bridges)
703 * scan the bus behind that child.
705 for(child = bus->children; child; child = child->sibling) {
706 if (!child->enabled ||
708 !child->ops->scan_bus)
712 max = child->ops->scan_bus(child, max);
716 * We've scanned the bus and so we know all about what's on
717 * the other side of any bridges that may be on this bus plus
720 * Return how far we've got finding sub-buses.
722 printk_debug("PCI: pci_scan_bus returning with max=%02x\n", max);
728 * @brief Scan a PCI bridge and the buses behind the bridge.
730 * Determine the existence of buses behind the bridge. Set up the bridge
731 * according to the result of the scan.
733 * This function is the default scan_bus() method for PCI bridge devices.
735 * @param dev pointer to the bridge device
736 * @param max the highest bus number assgined up to now
738 * @return The maximum bus number found, after scanning all subordinate busses
740 unsigned int pci_scan_bridge(struct device *dev, unsigned int max)
749 /* Set up the primary, secondary and subordinate bus numbers. We have
750 * no idea how many buses are behind this bridge yet, so we set the
751 * subordinate bus number to 0xff for the moment.
753 bus->secondary = ++max;
754 bus->subordinate = 0xff;
756 /* Clear all status bits and turn off memory, I/O and master enables. */
757 cr = pci_read_config16(dev, PCI_COMMAND);
758 pci_write_config16(dev, PCI_COMMAND, 0x0000);
759 pci_write_config16(dev, PCI_STATUS, 0xffff);
762 * Read the existing primary/secondary/subordinate bus
763 * number configuration.
765 buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
767 /* Configure the bus numbers for this bridge: the configuration
768 * transactions will not be propagated by the bridge if it is not
769 * correctly configured.
772 buses |= (((unsigned int) (dev->bus->secondary) << 0) |
773 ((unsigned int) (bus->secondary) << 8) |
774 ((unsigned int) (bus->subordinate) << 16));
775 pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
777 /* Now we can scan all subordinate buses
778 * i.e. the bus behind the bridge.
780 max = pci_scan_bus(bus, 0x00, 0xff, max);
782 /* We know the number of buses behind this bridge. Set the subordinate
783 * bus number to its real value.
785 bus->subordinate = max;
786 buses = (buses & 0xff00ffff) |
787 ((unsigned int) (bus->subordinate) << 16);
788 pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
789 pci_write_config16(dev, PCI_COMMAND, cr);
791 printk_spew("%s returns max %d\n", __func__, max);
796 Tell the EISA int controller this int must be level triggered
797 THIS IS A KLUDGE -- sorry, this needs to get cleaned up.
799 static void pci_level_irq(unsigned char intNum)
801 unsigned short intBits = inb(0x4d0) | (((unsigned) inb(0x4d1)) << 8);
804 printk_spew("%s: current ints are 0x%x\n", __func__, intBits);
806 printk_debug("%s: current ints are 0x%x\n", __FUNCTION__, intBits);
808 intBits |= (1 << intNum);
811 printk_spew("%s: try to set ints 0x%x\n", __func__, intBits);
813 printk_debug("%s: try to set ints 0x%x\n", __FUNCTION__, intBits);
817 outb((unsigned char) intBits, 0x4d0);
818 outb((unsigned char) (intBits >> 8), 0x4d1);
820 /* this seems like an error but is not ... */
822 if (inb(0x4d0) != (intBits & 0xf)) {
823 printk_err("%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
824 __func__, intBits &0xf, inb(0x4d0));
826 if (inb(0x4d1) != ((intBits >> 8) & 0xf)) {
827 printk_err("%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
828 __func__, (intBits>>8) &0xf, inb(0x4d1));
834 This function assigns IRQs for all functions contained within
835 the indicated device address. If the device does not exist or does
836 not require interrupts then this function has no effect.
838 This function should be called for each PCI slot in your system.
840 pIntAtoD is an array of IRQ #s that are assigned to PINTA through PINTD of
842 The particular irq #s that are passed in depend on the routing inside
843 your southbridge and on your motherboard.
847 void pci_assign_irqs(unsigned bus, unsigned slot,
848 const unsigned char pIntAtoD[4])
854 unsigned char readback;
856 /* Each slot may contain up to eight functions */
857 for (functNum = 0; functNum < 8; functNum++) {
858 pdev = dev_find_slot(bus, (slot << 3) + functNum);
861 line = pci_read_config8(pdev, PCI_INTERRUPT_PIN);
863 // PCI spec says all other values are reserved
864 if ((line >= 1) && (line <= 4)) {
865 irq = pIntAtoD[line - 1];
867 printk_debug("Assigning IRQ %d to %d:%x.%d\n", \
868 irq, bus, slot, functNum);
870 pci_write_config8(pdev, PCI_INTERRUPT_LINE,\
873 readback = pci_read_config8(pdev, PCI_INTERRUPT_LINE);
874 printk_debug(" Readback = %d\n", readback);
876 // Change to level triggered
877 pci_level_irq(pIntAtoD[line - 1]);