2 * This file is part of the LinuxBIOS project.
4 * It was originally based on the Linux kernel (drivers/pci/pci.c).
7 * Copyright (C) 2003-2004 Linux Networx
8 * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
9 * Copyright (C) 2003-2006 Ronald G. Minnich <rminnich@gmail.com>
10 * Copyright (C) 2004-2005 Li-Ta Lo <ollie@lanl.gov>
11 * Copyright (C) 2005-2006 Tyan
12 * (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
13 * Copyright (C) 2005-2007 Stefan Reinauer <stepan@openbios.org>
17 * PCI Bus Services, see include/linux/pci.h for further explanation.
19 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
20 * David Mosberger-Tang
22 * Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
25 #include <console/console.h>
31 #include <device/device.h>
32 #include <device/pci.h>
33 #include <device/pci_ids.h>
34 #include <part/hard_reset.h>
35 #include <part/fallback_boot.h>
37 #if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1
38 #include <device/hypertransport.h>
40 #if CONFIG_PCIX_PLUGIN_SUPPORT == 1
41 #include <device/pcix.h>
43 #if CONFIG_PCIEXP_PLUGIN_SUPPORT == 1
44 #include <device/pciexp.h>
46 #if CONFGI_AGP_PLUGIN_SUPPORT == 1
47 #include <device/agp.h>
49 #if CONFIG_CARDBUS_PLUGIN_SUPPORT == 1
50 #include <device/cardbus.h>
53 uint8_t pci_moving_config8(struct device *dev, unsigned reg)
55 uint8_t value, ones, zeroes;
56 value = pci_read_config8(dev, reg);
58 pci_write_config8(dev, reg, 0xff);
59 ones = pci_read_config8(dev, reg);
61 pci_write_config8(dev, reg, 0x00);
62 zeroes = pci_read_config8(dev, reg);
64 pci_write_config8(dev, reg, value);
69 uint16_t pci_moving_config16(struct device *dev, unsigned reg)
71 uint16_t value, ones, zeroes;
72 value = pci_read_config16(dev, reg);
74 pci_write_config16(dev, reg, 0xffff);
75 ones = pci_read_config16(dev, reg);
77 pci_write_config16(dev, reg, 0x0000);
78 zeroes = pci_read_config16(dev, reg);
80 pci_write_config16(dev, reg, value);
85 uint32_t pci_moving_config32(struct device *dev, unsigned reg)
87 uint32_t value, ones, zeroes;
88 value = pci_read_config32(dev, reg);
90 pci_write_config32(dev, reg, 0xffffffff);
91 ones = pci_read_config32(dev, reg);
93 pci_write_config32(dev, reg, 0x00000000);
94 zeroes = pci_read_config32(dev, reg);
96 pci_write_config32(dev, reg, value);
101 unsigned pci_find_next_capability(device_t dev, unsigned cap, unsigned last)
107 status = pci_read_config16(dev, PCI_STATUS);
108 if (!(status & PCI_STATUS_CAP_LIST)) {
111 switch(dev->hdr_type & 0x7f) {
112 case PCI_HEADER_TYPE_NORMAL:
113 case PCI_HEADER_TYPE_BRIDGE:
114 pos = PCI_CAPABILITY_LIST;
116 case PCI_HEADER_TYPE_CARDBUS:
117 pos = PCI_CB_CAPABILITY_LIST;
122 pos = pci_read_config8(dev, pos);
123 while(reps-- && (pos >= 0x40)) { /* loop through the linked list */
126 this_cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID);
127 printk_spew("Capability: 0x%02x @ 0x%02x\n", cap, pos);
128 if (this_cap == 0xff) {
131 if (!last && (this_cap == cap)) {
137 pos = pci_read_config8(dev, pos + PCI_CAP_LIST_NEXT);
142 unsigned pci_find_capability(device_t dev, unsigned cap)
144 return pci_find_next_capability(dev, cap, 0);
148 /** Given a device and register, read the size of the BAR for that register.
149 * @param dev Pointer to the device structure
150 * @param resource Pointer to the resource structure
151 * @param index Address of the pci configuration register
153 struct resource *pci_get_resource(struct device *dev, unsigned long index)
155 struct resource *resource;
156 unsigned long value, attr;
157 resource_t moving, limit;
159 /* Initialize the resources to nothing */
160 resource = new_resource(dev, index);
162 /* Get the initial value */
163 value = pci_read_config32(dev, index);
165 /* See which bits move */
166 moving = pci_moving_config32(dev, index);
168 /* Initialize attr to the bits that do not move */
169 attr = value & ~moving;
171 /* If it is a 64bit resource look at the high half as well */
172 if (((attr & PCI_BASE_ADDRESS_SPACE_IO) == 0) &&
173 ((attr & PCI_BASE_ADDRESS_MEM_LIMIT_MASK) == PCI_BASE_ADDRESS_MEM_LIMIT_64))
175 /* Find the high bits that move */
176 moving |= ((resource_t)pci_moving_config32(dev, index + 4)) << 32;
178 /* Find the resource constraints.
180 * Start by finding the bits that move. From there:
181 * - Size is the least significant bit of the bits that move.
182 * - Limit is all of the bits that move plus all of the lower bits.
183 * See PCI Spec 6.2.5.1 ...
188 resource->align = resource->gran = 0;
189 while(!(moving & resource->size)) {
190 resource->size <<= 1;
191 resource->align += 1;
194 resource->limit = limit = moving | (resource->size - 1);
197 * some broken hardware has read-only registers that do not
198 * really size correctly.
199 * Example: the acer m7229 has BARs 1-4 normally read-only.
200 * so BAR1 at offset 0x10 reads 0x1f1. If you size that register
201 * by writing 0xffffffff to it, it will read back as 0x1f1 -- a
202 * violation of the spec.
203 * We catch this case and ignore it by observing which bits move,
204 * This also catches the common case unimplemented registers
205 * that always read back as 0.
210 "%s register %02x(%08x), read-only ignoring it\n",
211 dev_path(dev), index, value);
215 else if (attr & PCI_BASE_ADDRESS_SPACE_IO) {
216 /* An I/O mapped base address */
217 attr &= PCI_BASE_ADDRESS_IO_ATTR_MASK;
218 resource->flags |= IORESOURCE_IO;
219 /* I don't want to deal with 32bit I/O resources */
220 resource->limit = 0xffff;
223 /* A Memory mapped base address */
224 attr &= PCI_BASE_ADDRESS_MEM_ATTR_MASK;
225 resource->flags |= IORESOURCE_MEM;
226 if (attr & PCI_BASE_ADDRESS_MEM_PREFETCH) {
227 resource->flags |= IORESOURCE_PREFETCH;
229 attr &= PCI_BASE_ADDRESS_MEM_LIMIT_MASK;
230 if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_32) {
232 resource->limit = 0xffffffffUL;
234 else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_1M) {
236 resource->limit = 0x000fffffUL;
238 else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_64) {
240 resource->limit = 0xffffffffffffffffULL;
241 resource->flags |= IORESOURCE_PCI64;
248 /* Don't let the limit exceed which bits can move */
249 if (resource->limit > limit) {
250 resource->limit = limit;
253 if (resource->flags) {
254 printk_debug("%s %02x ->",
255 dev_path(dev), resource->index);
256 printk_debug(" value: 0x%08Lx zeroes: 0x%08Lx ones: 0x%08Lx attr: %08lx\n",
257 value, zeroes, ones, attr);
259 "%s %02x -> size: 0x%08Lx max: 0x%08Lx %s\n ",
262 resource->size, resource->limit,
263 resource_type(resource));
270 static void pci_get_rom_resource(struct device *dev, unsigned long index)
272 struct resource *resource;
274 resource_t moving, limit;
276 if ((dev->on_mainboard) && (dev->rom_address == 0)) {
277 //skip it if rom_address is not set in MB Config.lb
281 /* Initialize the resources to nothing */
282 resource = new_resource(dev, index);
284 /* Get the initial value */
285 value = pci_read_config32(dev, index);
287 /* See which bits move */
288 moving = pci_moving_config32(dev, index);
289 /* clear the Enable bit */
290 moving = moving & ~PCI_ROM_ADDRESS_ENABLE;
292 /* Find the resource constraints.
294 * Start by finding the bits that move. From there:
295 * - Size is the least significant bit of the bits that move.
296 * - Limit is all of the bits that move plus all of the lower bits.
297 * See PCI Spec 6.2.5.1 ...
303 resource->align = resource->gran = 0;
304 while (!(moving & resource->size)) {
305 resource->size <<= 1;
306 resource->align += 1;
309 resource->limit = limit = moving | (resource->size - 1);
314 printk_debug("%s register %02x(%08x), read-only ignoring it\n",
315 dev_path(dev), index, value);
319 resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY;
322 /* for on board device with embedded ROM image, the ROM image is at
323 * fixed address specified in the Config.lb, the dev->rom_address is
324 * inited by driver_pci_onboard_ops::enable_dev() */
325 if ((dev->on_mainboard) && (dev->rom_address != 0)) {
326 resource->base = dev->rom_address;
327 resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY |
328 IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
331 compact_resources(dev);
334 /** Read the base address registers for a given device.
335 * @param dev Pointer to the dev structure
336 * @param howmany How many registers to read (6 for device, 2 for bridge)
338 static void pci_read_bases(struct device *dev, unsigned int howmany)
342 for(index = PCI_BASE_ADDRESS_0; (index < PCI_BASE_ADDRESS_0 + (howmany << 2)); ) {
343 struct resource *resource;
344 resource = pci_get_resource(dev, index);
345 index += (resource->flags & IORESOURCE_PCI64)?8:4;
348 compact_resources(dev);
351 static void pci_set_resource(struct device *dev, struct resource *resource);
353 static void pci_record_bridge_resource(
354 struct device *dev, resource_t moving,
355 unsigned index, unsigned long mask, unsigned long type)
357 /* Initiliaze the constraints on the current bus */
358 struct resource *resource;
363 resource = new_resource(dev, index);
367 while((moving & step) == 0) {
371 resource->gran = gran;
372 resource->align = gran;
373 resource->limit = moving | (step - 1);
374 resource->flags = type | IORESOURCE_PCI_BRIDGE;
375 compute_allocate_resource(&dev->link[0], resource, mask, type);
376 /* If there is nothing behind the resource,
377 * clear it and forget it.
379 if (resource->size == 0) {
380 resource->base = moving;
381 resource->flags |= IORESOURCE_ASSIGNED;
382 resource->flags &= ~IORESOURCE_STORED;
383 pci_set_resource(dev, resource);
390 static void pci_bridge_read_bases(struct device *dev)
392 resource_t moving_base, moving_limit, moving;
394 /* See if the bridge I/O resources are implemented */
395 moving_base = ((uint32_t)pci_moving_config8(dev, PCI_IO_BASE)) << 8;
396 moving_base |= ((uint32_t)pci_moving_config16(dev, PCI_IO_BASE_UPPER16)) << 16;
398 moving_limit = ((uint32_t)pci_moving_config8(dev, PCI_IO_LIMIT)) << 8;
399 moving_limit |= ((uint32_t)pci_moving_config16(dev, PCI_IO_LIMIT_UPPER16)) << 16;
401 moving = moving_base & moving_limit;
403 /* Initialize the io space constraints on the current bus */
404 pci_record_bridge_resource(
405 dev, moving, PCI_IO_BASE,
406 IORESOURCE_IO, IORESOURCE_IO);
409 /* See if the bridge prefmem resources are implemented */
410 moving_base = ((resource_t)pci_moving_config16(dev, PCI_PREF_MEMORY_BASE)) << 16;
411 moving_base |= ((resource_t)pci_moving_config32(dev, PCI_PREF_BASE_UPPER32)) << 32;
413 moving_limit = ((resource_t)pci_moving_config16(dev, PCI_PREF_MEMORY_LIMIT)) << 16;
414 moving_limit |= ((resource_t)pci_moving_config32(dev, PCI_PREF_LIMIT_UPPER32)) << 32;
416 moving = moving_base & moving_limit;
417 /* Initiliaze the prefetchable memory constraints on the current bus */
418 pci_record_bridge_resource(
419 dev, moving, PCI_PREF_MEMORY_BASE,
420 IORESOURCE_MEM | IORESOURCE_PREFETCH,
421 IORESOURCE_MEM | IORESOURCE_PREFETCH);
424 /* See if the bridge mem resources are implemented */
425 moving_base = ((uint32_t)pci_moving_config16(dev, PCI_MEMORY_BASE)) << 16;
426 moving_limit = ((uint32_t)pci_moving_config16(dev, PCI_MEMORY_LIMIT)) << 16;
428 moving = moving_base & moving_limit;
430 /* Initialize the memory resources on the current bus */
431 pci_record_bridge_resource(
432 dev, moving, PCI_MEMORY_BASE,
433 IORESOURCE_MEM | IORESOURCE_PREFETCH,
436 compact_resources(dev);
439 void pci_dev_read_resources(struct device *dev)
441 pci_read_bases(dev, 6);
442 pci_get_rom_resource(dev, PCI_ROM_ADDRESS);
445 void pci_bus_read_resources(struct device *dev)
447 pci_bridge_read_bases(dev);
448 pci_read_bases(dev, 2);
449 pci_get_rom_resource(dev, PCI_ROM_ADDRESS1);
452 static void pci_set_resource(struct device *dev, struct resource *resource)
454 resource_t base, end;
456 /* Make certain the resource has actually been set */
457 if (!(resource->flags & IORESOURCE_ASSIGNED)) {
458 printk_err("ERROR: %s %02x %s size: 0x%010Lx not assigned\n",
459 dev_path(dev), resource->index,
460 resource_type(resource),
465 /* If I have already stored this resource don't worry about it */
466 if (resource->flags & IORESOURCE_STORED) {
470 /* If the resources is substractive don't worry about it */
471 if (resource->flags & IORESOURCE_SUBTRACTIVE) {
475 /* Only handle PCI memory and IO resources for now */
476 if (!(resource->flags & (IORESOURCE_MEM |IORESOURCE_IO)))
479 /* Enable the resources in the command register */
480 if (resource->size) {
481 if (resource->flags & IORESOURCE_MEM) {
482 dev->command |= PCI_COMMAND_MEMORY;
484 if (resource->flags & IORESOURCE_IO) {
485 dev->command |= PCI_COMMAND_IO;
487 if (resource->flags & IORESOURCE_PCI_BRIDGE) {
488 dev->command |= PCI_COMMAND_MASTER;
491 /* Get the base address */
492 base = resource->base;
495 end = resource_end(resource);
497 /* Now store the resource */
498 resource->flags |= IORESOURCE_STORED;
499 if (!(resource->flags & IORESOURCE_PCI_BRIDGE)) {
500 unsigned long base_lo, base_hi;
502 * some chipsets allow us to set/clear the IO bit.
503 * (e.g. VIA 82c686a.) So set it to be safe)
505 base_lo = base & 0xffffffff;
506 base_hi = (base >> 32) & 0xffffffff;
507 if (resource->flags & IORESOURCE_IO) {
508 base_lo |= PCI_BASE_ADDRESS_SPACE_IO;
510 pci_write_config32(dev, resource->index, base_lo);
511 if (resource->flags & IORESOURCE_PCI64) {
512 pci_write_config32(dev, resource->index + 4, base_hi);
515 else if (resource->index == PCI_IO_BASE) {
516 /* set the IO ranges */
517 compute_allocate_resource(&dev->link[0], resource,
518 IORESOURCE_IO, IORESOURCE_IO);
519 pci_write_config8(dev, PCI_IO_BASE, base >> 8);
520 pci_write_config16(dev, PCI_IO_BASE_UPPER16, base >> 16);
521 pci_write_config8(dev, PCI_IO_LIMIT, end >> 8);
522 pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, end >> 16);
524 else if (resource->index == PCI_MEMORY_BASE) {
525 /* set the memory range */
526 compute_allocate_resource(&dev->link[0], resource,
527 IORESOURCE_MEM | IORESOURCE_PREFETCH,
529 pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);
530 pci_write_config16(dev, PCI_MEMORY_LIMIT, end >> 16);
532 else if (resource->index == PCI_PREF_MEMORY_BASE) {
533 /* set the prefetchable memory range */
534 compute_allocate_resource(&dev->link[0], resource,
535 IORESOURCE_MEM | IORESOURCE_PREFETCH,
536 IORESOURCE_MEM | IORESOURCE_PREFETCH);
537 pci_write_config16(dev, PCI_PREF_MEMORY_BASE, base >> 16);
538 pci_write_config32(dev, PCI_PREF_BASE_UPPER32, base >> 32);
539 pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, end >> 16);
540 pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, end >> 32);
543 /* Don't let me think I stored the resource */
544 resource->flags &= ~IORESOURCE_STORED;
545 printk_err("ERROR: invalid resource->index %x\n",
548 report_resource_stored(dev, resource, "");
552 void pci_dev_set_resources(struct device *dev)
554 struct resource *resource, *last;
558 last = &dev->resource[dev->resources];
560 for(resource = &dev->resource[0]; resource < last; resource++) {
561 pci_set_resource(dev, resource);
563 for(link = 0; link < dev->links; link++) {
565 bus = &dev->link[link];
567 assign_resources(bus);
571 /* set a default latency timer */
572 pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
574 /* set a default secondary latency timer */
575 if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
576 pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
579 /* zero the irq settings */
580 line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
582 pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
584 /* set the cache line size, so far 64 bytes is good for everyone */
585 pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
588 void pci_dev_enable_resources(struct device *dev)
590 const struct pci_operations *ops;
593 /* Set the subsystem vendor and device id for mainboard devices */
595 if (dev->on_mainboard && ops && ops->set_subsystem) {
596 printk_debug("%s subsystem <- %02x/%02x\n",
598 MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
599 MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
600 ops->set_subsystem(dev,
601 MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
602 MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
604 command = pci_read_config16(dev, PCI_COMMAND);
605 command |= dev->command;
606 printk_debug("%s cmd <- %02x\n", dev_path(dev), command);
607 pci_write_config16(dev, PCI_COMMAND, command);
610 void pci_bus_enable_resources(struct device *dev)
613 /* enable IO in command register if there is VGA card
614 * connected with (even it does not claim IO resource) */
615 if (dev->link[0].bridge_ctrl & PCI_BRIDGE_CTL_VGA)
616 dev->command |= PCI_COMMAND_IO;
617 ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
618 ctrl |= dev->link[0].bridge_ctrl;
619 ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error check */
620 printk_debug("%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
621 pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
623 pci_dev_enable_resources(dev);
625 enable_childrens_resources(dev);
628 void pci_bus_reset(struct bus *bus)
631 ctl = pci_read_config16(bus->dev, PCI_BRIDGE_CONTROL);
632 ctl |= PCI_BRIDGE_CTL_BUS_RESET;
633 pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, ctl);
635 ctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
636 pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, ctl);
640 void pci_dev_set_subsystem(device_t dev, unsigned vendor, unsigned device)
642 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
643 ((device & 0xffff) << 16) | (vendor & 0xffff));
646 /** default handler: only runs the relevant pci bios. */
647 void pci_dev_init(struct device *dev)
649 #if CONFIG_PCI_ROM_RUN == 1 || CONFIG_VGA_ROM_RUN == 1
650 struct rom_header *rom, *ram;
652 #if CONFIG_PCI_ROM_RUN != 1
653 /* We want to execute VGA option ROMs when CONFIG_VGA_ROM_RUN
654 * is set but CONFIG_PCI_ROM_RUN is not. In this case we skip
655 * all other option ROM types.
657 if (dev->class!=PCI_CLASS_DISPLAY_VGA)
661 rom = pci_rom_probe(dev);
665 ram = pci_rom_load(dev, rom);
671 #if CONFIG_CONSOLE_VGA == 1
672 /* vga_inited is a trigger of the VGA console code. */
673 if (dev->class == PCI_CLASS_DISPLAY_VGA) {
674 extern int vga_inited;
677 #endif /* CONFIG_CONSOLE_VGA */
678 #endif /* CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN */
681 /** Default device operation for PCI devices */
682 static struct pci_operations pci_dev_ops_pci = {
683 .set_subsystem = pci_dev_set_subsystem,
686 struct device_operations default_pci_ops_dev = {
687 .read_resources = pci_dev_read_resources,
688 .set_resources = pci_dev_set_resources,
689 .enable_resources = pci_dev_enable_resources,
690 .init = pci_dev_init,
693 .ops_pci = &pci_dev_ops_pci,
696 /** Default device operations for PCI bridges */
697 static struct pci_operations pci_bus_ops_pci = {
701 struct device_operations default_pci_ops_bus = {
702 .read_resources = pci_bus_read_resources,
703 .set_resources = pci_dev_set_resources,
704 .enable_resources = pci_bus_enable_resources,
706 .scan_bus = pci_scan_bridge,
708 .reset_bus = pci_bus_reset,
709 .ops_pci = &pci_bus_ops_pci,
713 * @brief Detect the type of downstream bridge
715 * This function is a heuristic to detect which type
716 * of bus is downstream of a pci to pci bridge. This
717 * functions by looking for various capability blocks
718 * to figure out the type of downstream bridge. PCI-X
719 * PCI-E, and Hypertransport all seem to have appropriate
722 * When only a PCI-Express capability is found the type
723 * is examined to see which type of bridge we have.
727 * @return appropriate bridge operations
729 static struct device_operations *get_pci_bridge_ops(device_t dev)
733 #if CONFIG_PCIX_PLUGIN_SUPPORT == 1
734 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
736 printk_debug("%s subbordinate bus PCI-X\n", dev_path(dev));
737 return &default_pcix_ops_bus;
740 #if CONFIG_AGP_PLUGIN_SUPPORT == 1
741 /* How do I detect an PCI to AGP bridge? */
743 #if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1
745 while((pos = pci_find_next_capability(dev, PCI_CAP_ID_HT, pos))) {
747 flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
748 if ((flags >> 13) == 1) {
749 /* Host or Secondary Interface */
750 printk_debug("%s subbordinate bus Hypertransport\n",
752 return &default_ht_ops_bus;
756 #if CONFIG_PCIEXP_PLUGIN_SUPPORT == 1
757 pos = pci_find_capability(dev, PCI_CAP_ID_PCIE);
760 flags = pci_read_config16(dev, pos + PCI_EXP_FLAGS);
761 switch((flags & PCI_EXP_FLAGS_TYPE) >> 4) {
762 case PCI_EXP_TYPE_ROOT_PORT:
763 case PCI_EXP_TYPE_UPSTREAM:
764 case PCI_EXP_TYPE_DOWNSTREAM:
765 printk_debug("%s subbordinate bus PCI Express\n",
767 return &default_pciexp_ops_bus;
768 case PCI_EXP_TYPE_PCI_BRIDGE:
769 printk_debug("%s subbordinate PCI\n",
771 return &default_pci_ops_bus;
777 return &default_pci_ops_bus;
781 * @brief Set up PCI device operation
788 static void set_pci_ops(struct device *dev)
790 struct pci_driver *driver;
795 /* Look through the list of setup drivers and find one for
798 for(driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) {
799 if ((driver->vendor == dev->vendor) &&
800 (driver->device == dev->device))
802 dev->ops = driver->ops;
803 printk_spew("%s [%04x/%04x] %sops\n",
805 driver->vendor, driver->device,
806 (driver->ops->scan_bus?"bus ":""));
811 /* If I don't have a specific driver use the default operations */
812 switch(dev->hdr_type & 0x7f) { /* header type */
813 case PCI_HEADER_TYPE_NORMAL: /* standard header */
814 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
816 dev->ops = &default_pci_ops_dev;
818 case PCI_HEADER_TYPE_BRIDGE:
819 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
821 dev->ops = get_pci_bridge_ops(dev);
823 #if CONFIG_CARDBUS_PLUGIN_SUPPORT == 1
824 case PCI_HEADER_TYPE_CARDBUS:
825 dev->ops = &default_cardbus_ops_bus;
831 printk_err("%s [%04x/%04x/%06x] has unknown header "
832 "type %02x, ignoring.\n",
834 dev->vendor, dev->device,
835 dev->class >> 8, dev->hdr_type);
844 * @brief See if we have already allocated a device structure for a given devfn.
846 * Given a linked list of PCI device structures and a devfn number, find the
847 * device structure correspond to the devfn, if present. This function also
848 * removes the device structure from the linked list.
850 * @param list the device structure list
851 * @param devfn a device/function number
853 * @return pointer to the device structure found or null of we have not
854 * allocated a device for this devfn yet.
856 static struct device *pci_scan_get_dev(struct device **list, unsigned int devfn)
860 for(; *list; list = &(*list)->sibling) {
861 if ((*list)->path.type != DEVICE_PATH_PCI) {
862 printk_err("child %s not a pci device\n",
866 if ((*list)->path.u.pci.devfn == devfn) {
867 /* Unlink from the list */
869 *list = (*list)->sibling;
874 /* Just like alloc_dev add the device to the list of device on the bus.
875 * When the list of devices was formed we removed all of the parents
876 * children, and now we are interleaving static and dynamic devices in
881 /* Find the last child of our parent */
882 for(child = dev->bus->children; child && child->sibling; ) {
883 child = child->sibling;
885 /* Place the device on the list of children of it's parent. */
887 child->sibling = dev;
889 dev->bus->children = dev;
897 * @brief Scan a PCI bus.
899 * Determine the existence of a given PCI device.
901 * @param bus pointer to the bus structure
902 * @param devfn to look at
904 * @return The device structure for hte device (if found)
905 * or the NULL if no device is found.
907 device_t pci_probe_dev(device_t dev, struct bus *bus, unsigned devfn)
912 /* Detect if a device is present */
916 dummy.path.type = DEVICE_PATH_PCI;
917 dummy.path.u.pci.devfn = devfn;
918 id = pci_read_config32(&dummy, PCI_VENDOR_ID);
919 /* Have we found somthing?
920 * Some broken boards return 0 if a slot is empty.
922 if ( (id == 0xffffffff) || (id == 0x00000000) ||
923 (id == 0x0000ffff) || (id == 0xffff0000))
925 printk_spew("PCI: devfn 0x%x, bad id 0x%x\n", devfn, id);
928 dev = alloc_dev(bus, &dummy.path);
931 /* Enable/disable the device. Once we have
932 * found the device specific operations this
933 * operations we will disable the device with
936 * This is geared toward devices that have subfunctions
937 * that do not show up by default.
939 * If a device is a stuff option on the motherboard
940 * it may be absent and enable_dev must cope.
943 /* Run the magice enable sequence for the device */
944 if (dev->chip_ops && dev->chip_ops->enable_dev) {
945 dev->chip_ops->enable_dev(dev);
947 /* Now read the vendor and device id */
948 id = pci_read_config32(dev, PCI_VENDOR_ID);
951 /* If the device does not have a pci id disable it.
952 * Possibly this is because we have already disabled
953 * the device. But this also handles optional devices
954 * that may not always show up.
956 /* If the chain is fully enumerated quit */
957 if ( (id == 0xffffffff) || (id == 0x00000000) ||
958 (id == 0x0000ffff) || (id == 0xffff0000))
961 printk_info("Disabling static device: %s\n",
968 /* Read the rest of the pci configuration information */
969 hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
970 class = pci_read_config32(dev, PCI_CLASS_REVISION);
972 /* Store the interesting information in the device structure */
973 dev->vendor = id & 0xffff;
974 dev->device = (id >> 16) & 0xffff;
975 dev->hdr_type = hdr_type;
976 /* class code, the upper 3 bytes of PCI_CLASS_REVISION */
977 dev->class = class >> 8;
980 /* Architectural/System devices always need to
983 if ((dev->class >> 16) == PCI_BASE_CLASS_SYSTEM) {
984 dev->command |= PCI_COMMAND_MASTER;
986 /* Look at the vendor and device id, or at least the
987 * header type and class and figure out which set of
988 * configuration methods to use. Unless we already
993 /* Now run the magic enable/disable sequence for the device */
994 if (dev->ops && dev->ops->enable) {
995 dev->ops->enable(dev);
999 /* Display the device and error if we don't have some pci operations
1002 printk_debug("%s [%04x/%04x] %s%s\n",
1004 dev->vendor, dev->device,
1005 dev->enabled?"enabled": "disabled",
1006 dev->ops?"" : " No operations"
1013 * @brief Scan a PCI bus.
1015 * Determine the existence of devices and bridges on a PCI bus. If there are
1016 * bridges on the bus, recursively scan the buses behind the bridges.
1018 * This function is the default scan_bus() method for the root device
1021 * @param bus pointer to the bus structure
1022 * @param min_devfn minimum devfn to look at in the scan usually 0x00
1023 * @param max_devfn maximum devfn to look at in the scan usually 0xff
1024 * @param max current bus number
1026 * @return The maximum bus number found, after scanning all subordinate busses
1028 unsigned int pci_scan_bus(struct bus *bus,
1029 unsigned min_devfn, unsigned max_devfn,
1033 device_t old_devices;
1036 #if PCI_BUS_SEGN_BITS
1037 printk_debug("PCI: pci_scan_bus for bus %04x:%02x\n", bus->secondary >> 8, bus->secondary & 0xff);
1039 printk_debug("PCI: pci_scan_bus for bus %02x\n", bus->secondary);
1042 old_devices = bus->children;
1046 /* probe all devices/functions on this bus with some optimization for
1047 * non-existence and single funcion devices
1049 for (devfn = min_devfn; devfn <= max_devfn; devfn++) {
1052 /* First thing setup the device structure */
1053 dev = pci_scan_get_dev(&old_devices, devfn);
1055 /* See if a device is present and setup the device
1058 dev = pci_probe_dev(dev, bus, devfn);
1060 /* if this is not a multi function device,
1061 * or the device is not present don't waste
1062 * time probing another function.
1063 * Skip to next device.
1065 if ((PCI_FUNC(devfn) == 0x00) &&
1066 (!dev || (dev->enabled && ((dev->hdr_type & 0x80) != 0x80))))
1073 /* Die if any leftover Static devices are are found.
1074 * There's probably a problem in the Config.lb.
1078 for(left = old_devices; left; left = left->sibling) {
1079 printk_err("%s\n", dev_path(left));
1081 die("PCI: Left over static devices. Check your Config.lb\n");
1084 /* For all children that implement scan_bus (i.e. bridges)
1085 * scan the bus behind that child.
1087 for(child = bus->children; child; child = child->sibling) {
1088 max = scan_bus(child, max);
1092 * We've scanned the bus and so we know all about what's on
1093 * the other side of any bridges that may be on this bus plus
1096 * Return how far we've got finding sub-buses.
1098 printk_debug("PCI: pci_scan_bus returning with max=%03x\n", max);
1105 * @brief Scan a PCI bridge and the buses behind the bridge.
1107 * Determine the existence of buses behind the bridge. Set up the bridge
1108 * according to the result of the scan.
1110 * This function is the default scan_bus() method for PCI bridge devices.
1112 * @param dev pointer to the bridge device
1113 * @param max the highest bus number assgined up to now
1115 * @return The maximum bus number found, after scanning all subordinate busses
1117 unsigned int do_pci_scan_bridge(struct device *dev, unsigned int max,
1118 unsigned int (*do_scan_bus)(struct bus *bus,
1119 unsigned min_devfn, unsigned max_devfn, unsigned int max))
1125 printk_spew("%s for %s\n", __func__, dev_path(dev));
1127 bus = &dev->link[0];
1131 /* Set up the primary, secondary and subordinate bus numbers. We have
1132 * no idea how many buses are behind this bridge yet, so we set the
1133 * subordinate bus number to 0xff for the moment.
1135 bus->secondary = ++max;
1136 bus->subordinate = 0xff;
1138 /* Clear all status bits and turn off memory, I/O and master enables. */
1139 cr = pci_read_config16(dev, PCI_COMMAND);
1140 pci_write_config16(dev, PCI_COMMAND, 0x0000);
1141 pci_write_config16(dev, PCI_STATUS, 0xffff);
1144 * Read the existing primary/secondary/subordinate bus
1145 * number configuration.
1147 buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
1149 /* Configure the bus numbers for this bridge: the configuration
1150 * transactions will not be propagated by the bridge if it is not
1151 * correctly configured.
1153 buses &= 0xff000000;
1154 buses |= (((unsigned int) (dev->bus->secondary) << 0) |
1155 ((unsigned int) (bus->secondary) << 8) |
1156 ((unsigned int) (bus->subordinate) << 16));
1157 pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
1159 /* Now we can scan all subordinate buses
1160 * i.e. the bus behind the bridge.
1162 max = do_scan_bus(bus, 0x00, 0xff, max);
1164 /* We know the number of buses behind this bridge. Set the subordinate
1165 * bus number to its real value.
1167 bus->subordinate = max;
1168 buses = (buses & 0xff00ffff) |
1169 ((unsigned int) (bus->subordinate) << 16);
1170 pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
1171 pci_write_config16(dev, PCI_COMMAND, cr);
1173 printk_spew("%s returns max %d\n", __func__, max);
1178 * @brief Scan a PCI bridge and the buses behind the bridge.
1180 * Determine the existence of buses behind the bridge. Set up the bridge
1181 * according to the result of the scan.
1183 * This function is the default scan_bus() method for PCI bridge devices.
1185 * @param dev pointer to the bridge device
1186 * @param max the highest bus number assgined up to now
1188 * @return The maximum bus number found, after scanning all subordinate busses
1190 unsigned int pci_scan_bridge(struct device *dev, unsigned int max)
1192 return do_pci_scan_bridge(dev, max, pci_scan_bus);
1196 Tell the EISA int controller this int must be level triggered
1197 THIS IS A KLUDGE -- sorry, this needs to get cleaned up.
1199 void pci_level_irq(unsigned char intNum)
1201 unsigned short intBits = inb(0x4d0) | (((unsigned) inb(0x4d1)) << 8);
1203 printk_spew("%s: current ints are 0x%x\n", __func__, intBits);
1204 intBits |= (1 << intNum);
1206 printk_spew("%s: try to set ints 0x%x\n", __func__, intBits);
1209 outb((unsigned char) intBits, 0x4d0);
1210 outb((unsigned char) (intBits >> 8), 0x4d1);
1212 /* this seems like an error but is not ... */
1214 if (inb(0x4d0) != (intBits & 0xff)) {
1215 printk_err("%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
1216 __func__, intBits &0xff, inb(0x4d0));
1218 if (inb(0x4d1) != ((intBits >> 8) & 0xff)) {
1219 printk_err("%s: lower order bits are wrong: want 0x%x, got 0x%x\n",
1220 __func__, (intBits>>8) &0xff, inb(0x4d1));
1226 This function assigns IRQs for all functions contained within
1227 the indicated device address. If the device does not exist or does
1228 not require interrupts then this function has no effect.
1230 This function should be called for each PCI slot in your system.
1232 pIntAtoD is an array of IRQ #s that are assigned to PINTA through PINTD of
1234 The particular irq #s that are passed in depend on the routing inside
1235 your southbridge and on your motherboard.
1239 void pci_assign_irqs(unsigned bus, unsigned slot,
1240 const unsigned char pIntAtoD[4])
1246 unsigned char readback;
1248 /* Each slot may contain up to eight functions */
1249 for (functNum = 0; functNum < 8; functNum++) {
1250 pdev = dev_find_slot(bus, (slot << 3) + functNum);
1253 line = pci_read_config8(pdev, PCI_INTERRUPT_PIN);
1255 // PCI spec says all other values are reserved
1256 if ((line >= 1) && (line <= 4)) {
1257 irq = pIntAtoD[line - 1];
1259 printk_debug("Assigning IRQ %d to %d:%x.%d\n", \
1260 irq, bus, slot, functNum);
1262 pci_write_config8(pdev, PCI_INTERRUPT_LINE,\
1263 pIntAtoD[line - 1]);
1265 readback = pci_read_config8(pdev, PCI_INTERRUPT_LINE);
1266 printk_debug(" Readback = %d\n", readback);
1268 // Change to level triggered
1269 pci_level_irq(pIntAtoD[line - 1]);