2 * This file is part of the coreboot project.
4 * It was originally based on the Linux kernel (drivers/pci/pci.c).
7 * Copyright (C) 2003-2004 Linux Networx
8 * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
9 * Copyright (C) 2003-2006 Ronald G. Minnich <rminnich@gmail.com>
10 * Copyright (C) 2004-2005 Li-Ta Lo <ollie@lanl.gov>
11 * Copyright (C) 2005-2006 Tyan
12 * (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
13 * Copyright (C) 2005-2009 coresystems GmbH
14 * (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
18 * PCI Bus Services, see include/linux/pci.h for further explanation.
20 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
21 * David Mosberger-Tang
23 * Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
26 #include <console/console.h>
32 #include <device/device.h>
33 #include <device/pci.h>
34 #include <device/pci_ids.h>
35 #include <part/hard_reset.h>
36 #include <part/fallback_boot.h>
38 #if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1
39 #include <device/hypertransport.h>
41 #if CONFIG_PCIX_PLUGIN_SUPPORT == 1
42 #include <device/pcix.h>
44 #if CONFIG_PCIEXP_PLUGIN_SUPPORT == 1
45 #include <device/pciexp.h>
47 #if CONFIG_AGP_PLUGIN_SUPPORT == 1
48 #include <device/agp.h>
50 #if CONFIG_CARDBUS_PLUGIN_SUPPORT == 1
51 #include <device/cardbus.h>
53 #define CONFIG_PC80_SYSTEM 1
54 #if CONFIG_PC80_SYSTEM == 1
55 #include <pc80/i8259.h>
58 u8 pci_moving_config8(struct device *dev, unsigned int reg)
60 u8 value, ones, zeroes;
61 value = pci_read_config8(dev, reg);
63 pci_write_config8(dev, reg, 0xff);
64 ones = pci_read_config8(dev, reg);
66 pci_write_config8(dev, reg, 0x00);
67 zeroes = pci_read_config8(dev, reg);
69 pci_write_config8(dev, reg, value);
74 u16 pci_moving_config16(struct device * dev, unsigned int reg)
76 u16 value, ones, zeroes;
77 value = pci_read_config16(dev, reg);
79 pci_write_config16(dev, reg, 0xffff);
80 ones = pci_read_config16(dev, reg);
82 pci_write_config16(dev, reg, 0x0000);
83 zeroes = pci_read_config16(dev, reg);
85 pci_write_config16(dev, reg, value);
90 u32 pci_moving_config32(struct device * dev, unsigned int reg)
92 u32 value, ones, zeroes;
93 value = pci_read_config32(dev, reg);
95 pci_write_config32(dev, reg, 0xffffffff);
96 ones = pci_read_config32(dev, reg);
98 pci_write_config32(dev, reg, 0x00000000);
99 zeroes = pci_read_config32(dev, reg);
101 pci_write_config32(dev, reg, value);
103 return ones ^ zeroes;
107 * Given a device, a capability type, and a last position, return the next
108 * matching capability. Always start at the head of the list.
110 * @param dev Pointer to the device structure.
111 * @param cap_type PCI_CAP_LIST_ID of the PCI capability we're looking for.
112 * @param last Location of the PCI capability register to start from.
114 unsigned pci_find_next_capability(struct device *dev, unsigned cap,
121 status = pci_read_config16(dev, PCI_STATUS);
122 if (!(status & PCI_STATUS_CAP_LIST)) {
125 switch (dev->hdr_type & 0x7f) {
126 case PCI_HEADER_TYPE_NORMAL:
127 case PCI_HEADER_TYPE_BRIDGE:
128 pos = PCI_CAPABILITY_LIST;
130 case PCI_HEADER_TYPE_CARDBUS:
131 pos = PCI_CB_CAPABILITY_LIST;
136 pos = pci_read_config8(dev, pos);
137 while (reps-- && (pos >= 0x40)) { /* Loop through the linked list. */
140 this_cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID);
141 printk_spew("Capability: type 0x%02x @ 0x%02x\n", this_cap,
143 if (this_cap == 0xff) {
146 if (!last && (this_cap == cap)) {
152 pos = pci_read_config8(dev, pos + PCI_CAP_LIST_NEXT);
158 * Given a device, and a capability type, return the next matching
159 * capability. Always start at the head of the list.
161 * @param dev Pointer to the device structure.
162 * @param cap_type PCI_CAP_LIST_ID of the PCI capability we're looking for.
164 unsigned pci_find_capability(device_t dev, unsigned cap)
166 return pci_find_next_capability(dev, cap, 0);
170 * Given a device and register, read the size of the BAR for that register.
172 * @param dev Pointer to the device structure.
173 * @param index Address of the PCI configuration register.
175 struct resource *pci_get_resource(struct device *dev, unsigned long index)
177 struct resource *resource;
178 unsigned long value, attr;
179 resource_t moving, limit;
181 /* Initialize the resources to nothing. */
182 resource = new_resource(dev, index);
184 /* Get the initial value. */
185 value = pci_read_config32(dev, index);
187 /* See which bits move. */
188 moving = pci_moving_config32(dev, index);
190 /* Initialize attr to the bits that do not move. */
191 attr = value & ~moving;
193 /* If it is a 64bit resource look at the high half as well. */
194 if (((attr & PCI_BASE_ADDRESS_SPACE_IO) == 0) &&
195 ((attr & PCI_BASE_ADDRESS_MEM_LIMIT_MASK) ==
196 PCI_BASE_ADDRESS_MEM_LIMIT_64)) {
197 /* Find the high bits that move. */
199 ((resource_t) pci_moving_config32(dev, index + 4)) << 32;
201 /* Find the resource constraints.
202 * Start by finding the bits that move. From there:
203 * - Size is the least significant bit of the bits that move.
204 * - Limit is all of the bits that move plus all of the lower bits.
205 * See PCI Spec 6.2.5.1.
210 resource->align = resource->gran = 0;
211 while (!(moving & resource->size)) {
212 resource->size <<= 1;
213 resource->align += 1;
216 resource->limit = limit = moving | (resource->size - 1);
219 /* Some broken hardware has read-only registers that do not
220 * really size correctly.
221 * Example: the Acer M7229 has BARs 1-4 normally read-only.
222 * so BAR1 at offset 0x10 reads 0x1f1. If you size that register
223 * by writing 0xffffffff to it, it will read back as 0x1f1 -- a
224 * violation of the spec.
225 * We catch this case and ignore it by observing which bits move,
226 * This also catches the common case unimplemented registers
227 * that always read back as 0.
232 ("%s register %02lx(%08lx), read-only ignoring it\n",
233 dev_path(dev), index, value);
236 } else if (attr & PCI_BASE_ADDRESS_SPACE_IO) {
237 /* An I/O mapped base address. */
238 attr &= PCI_BASE_ADDRESS_IO_ATTR_MASK;
239 resource->flags |= IORESOURCE_IO;
240 /* I don't want to deal with 32bit I/O resources. */
241 resource->limit = 0xffff;
243 /* A Memory mapped base address. */
244 attr &= PCI_BASE_ADDRESS_MEM_ATTR_MASK;
245 resource->flags |= IORESOURCE_MEM;
246 if (attr & PCI_BASE_ADDRESS_MEM_PREFETCH) {
247 resource->flags |= IORESOURCE_PREFETCH;
249 attr &= PCI_BASE_ADDRESS_MEM_LIMIT_MASK;
250 if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_32) {
252 resource->limit = 0xffffffffUL;
253 } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_1M) {
255 resource->limit = 0x000fffffUL;
256 } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_64) {
258 resource->limit = 0xffffffffffffffffULL;
259 resource->flags |= IORESOURCE_PCI64;
262 printk_err("Broken BAR with value %lx\n", attr);
263 printk_err(" on dev %s at index %02lx\n",
264 dev_path(dev), index);
268 /* Don't let the limit exceed which bits can move. */
269 if (resource->limit > limit) {
270 resource->limit = limit;
277 * Given a device and an index, read the size of the BAR for that register.
279 * @param dev Pointer to the device structure.
280 * @param index Address of the PCI configuration register.
282 static void pci_get_rom_resource(struct device *dev, unsigned long index)
284 struct resource *resource;
288 /* Initialize the resources to nothing. */
289 resource = new_resource(dev, index);
291 /* Get the initial value. */
292 value = pci_read_config32(dev, index);
294 /* See which bits move. */
295 moving = pci_moving_config32(dev, index);
297 /* Clear the Enable bit. */
298 moving = moving & ~PCI_ROM_ADDRESS_ENABLE;
300 /* Find the resource constraints.
301 * Start by finding the bits that move. From there:
302 * - Size is the least significant bit of the bits that move.
303 * - Limit is all of the bits that move plus all of the lower bits.
304 * See PCI Spec 6.2.5.1.
308 resource->align = resource->gran = 0;
309 while (!(moving & resource->size)) {
310 resource->size <<= 1;
311 resource->align += 1;
314 resource->limit = moving | (resource->size - 1);
315 resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY;
319 ("%s register %02lx(%08lx), read-only ignoring it\n",
320 dev_path(dev), index, value);
324 compact_resources(dev);
328 * Read the base address registers for a given device.
330 * @param dev Pointer to the dev structure.
331 * @param howmany How many registers to read (6 for device, 2 for bridge).
333 static void pci_read_bases(struct device *dev, unsigned int howmany)
337 for (index = PCI_BASE_ADDRESS_0;
338 (index < PCI_BASE_ADDRESS_0 + (howmany << 2));) {
339 struct resource *resource;
340 resource = pci_get_resource(dev, index);
341 index += (resource->flags & IORESOURCE_PCI64) ? 8 : 4;
344 compact_resources(dev);
347 static void pci_record_bridge_resource(struct device *dev, resource_t moving,
348 unsigned index, unsigned long type)
350 /* Initialize the constraints on the current bus. */
351 struct resource *resource;
356 resource = new_resource(dev, index);
360 while ((moving & step) == 0) {
364 resource->gran = gran;
365 resource->align = gran;
366 resource->limit = moving | (step - 1);
367 resource->flags = type | IORESOURCE_PCI_BRIDGE |
373 static void pci_bridge_read_bases(struct device *dev)
375 resource_t moving_base, moving_limit, moving;
377 /* See if the bridge I/O resources are implemented. */
378 moving_base = ((u32) pci_moving_config8(dev, PCI_IO_BASE)) << 8;
380 ((u32) pci_moving_config16(dev, PCI_IO_BASE_UPPER16)) << 16;
382 moving_limit = ((u32) pci_moving_config8(dev, PCI_IO_LIMIT)) << 8;
384 ((u32) pci_moving_config16(dev, PCI_IO_LIMIT_UPPER16)) << 16;
386 moving = moving_base & moving_limit;
388 /* Initialize the I/O space constraints on the current bus. */
389 pci_record_bridge_resource(dev, moving, PCI_IO_BASE, IORESOURCE_IO);
391 /* See if the bridge prefmem resources are implemented. */
393 ((resource_t) pci_moving_config16(dev, PCI_PREF_MEMORY_BASE)) << 16;
395 ((resource_t) pci_moving_config32(dev, PCI_PREF_BASE_UPPER32)) <<
399 ((resource_t) pci_moving_config16(dev, PCI_PREF_MEMORY_LIMIT)) <<
402 ((resource_t) pci_moving_config32(dev, PCI_PREF_LIMIT_UPPER32)) <<
405 moving = moving_base & moving_limit;
406 /* Initialize the prefetchable memory constraints on the current bus. */
407 pci_record_bridge_resource(dev, moving, PCI_PREF_MEMORY_BASE,
408 IORESOURCE_MEM | IORESOURCE_PREFETCH);
410 /* See if the bridge mem resources are implemented. */
411 moving_base = ((u32) pci_moving_config16(dev, PCI_MEMORY_BASE)) << 16;
412 moving_limit = ((u32) pci_moving_config16(dev, PCI_MEMORY_LIMIT)) << 16;
414 moving = moving_base & moving_limit;
416 /* Initialize the memory resources on the current bus. */
417 pci_record_bridge_resource(dev, moving, PCI_MEMORY_BASE,
420 compact_resources(dev);
423 void pci_dev_read_resources(struct device *dev)
425 pci_read_bases(dev, 6);
426 pci_get_rom_resource(dev, PCI_ROM_ADDRESS);
429 void pci_bus_read_resources(struct device *dev)
431 pci_bridge_read_bases(dev);
432 pci_read_bases(dev, 2);
433 pci_get_rom_resource(dev, PCI_ROM_ADDRESS1);
436 void pci_domain_read_resources(struct device *dev)
438 struct resource *res;
440 /* Initialize the system-wide I/O space constraints. */
441 res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
442 res->limit = 0xffffUL;
443 res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
446 /* Initialize the system-wide memory resources constraints. */
447 res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
448 res->limit = 0xffffffffULL;
449 res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
453 static void pci_set_resource(struct device *dev, struct resource *resource)
455 resource_t base, end;
457 /* Make certain the resource has actually been assigned a value. */
458 if (!(resource->flags & IORESOURCE_ASSIGNED)) {
459 printk_err("ERROR: %s %02lx %s size: 0x%010llx not assigned\n",
460 dev_path(dev), resource->index,
461 resource_type(resource), resource->size);
465 /* If this resource is fixed don't worry about it. */
466 if (resource->flags & IORESOURCE_FIXED) {
470 /* If I have already stored this resource don't worry about it. */
471 if (resource->flags & IORESOURCE_STORED) {
475 /* If the resource is subtractive don't worry about it. */
476 if (resource->flags & IORESOURCE_SUBTRACTIVE) {
480 /* Only handle PCI memory and I/O resources for now. */
481 if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
484 /* Enable the resources in the command register. */
485 if (resource->size) {
486 if (resource->flags & IORESOURCE_MEM) {
487 dev->command |= PCI_COMMAND_MEMORY;
489 if (resource->flags & IORESOURCE_IO) {
490 dev->command |= PCI_COMMAND_IO;
492 if (resource->flags & IORESOURCE_PCI_BRIDGE) {
493 dev->command |= PCI_COMMAND_MASTER;
496 /* Get the base address. */
497 base = resource->base;
500 end = resource_end(resource);
502 /* Now store the resource. */
503 resource->flags |= IORESOURCE_STORED;
505 /* PCI Bridges have no enable bit. They are disabled if the base of
506 * the range is greater than the limit. If the size is zero, disable
507 * by setting the base = limit and end = limit - 2^gran.
509 if (resource->size == 0 && (resource->flags & IORESOURCE_PCI_BRIDGE)) {
510 base = resource->limit;
511 end = resource->limit - (1 << resource->gran);
512 resource->base = base;
515 if (!(resource->flags & IORESOURCE_PCI_BRIDGE)) {
516 unsigned long base_lo, base_hi;
517 /* Some chipsets allow us to set/clear the I/O bit
518 * (e.g. VIA 82c686a). So set it to be safe.
520 base_lo = base & 0xffffffff;
521 base_hi = (base >> 32) & 0xffffffff;
522 if (resource->flags & IORESOURCE_IO) {
523 base_lo |= PCI_BASE_ADDRESS_SPACE_IO;
525 pci_write_config32(dev, resource->index, base_lo);
526 if (resource->flags & IORESOURCE_PCI64) {
527 pci_write_config32(dev, resource->index + 4, base_hi);
529 } else if (resource->index == PCI_IO_BASE) {
530 /* Set the I/O ranges. */
531 pci_write_config8(dev, PCI_IO_BASE, base >> 8);
532 pci_write_config16(dev, PCI_IO_BASE_UPPER16, base >> 16);
533 pci_write_config8(dev, PCI_IO_LIMIT, end >> 8);
534 pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, end >> 16);
535 } else if (resource->index == PCI_MEMORY_BASE) {
536 /* Set the memory range. */
537 pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);
538 pci_write_config16(dev, PCI_MEMORY_LIMIT, end >> 16);
539 } else if (resource->index == PCI_PREF_MEMORY_BASE) {
540 /* Set the prefetchable memory range. */
541 pci_write_config16(dev, PCI_PREF_MEMORY_BASE, base >> 16);
542 pci_write_config32(dev, PCI_PREF_BASE_UPPER32, base >> 32);
543 pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, end >> 16);
544 pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, end >> 32);
546 /* Don't let me think I stored the resource. */
547 resource->flags &= ~IORESOURCE_STORED;
548 printk_err("ERROR: invalid resource->index %lx\n",
551 report_resource_stored(dev, resource, "");
555 void pci_dev_set_resources(struct device *dev)
557 struct resource *resource, *last;
561 last = &dev->resource[dev->resources];
563 for (resource = &dev->resource[0]; resource < last; resource++) {
564 pci_set_resource(dev, resource);
566 for (link = 0; link < dev->links; link++) {
568 bus = &dev->link[link];
570 assign_resources(bus);
574 /* Set a default latency timer. */
575 pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
577 /* Set a default secondary latency timer. */
578 if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
579 pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
582 /* Zero the IRQ settings. */
583 line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
585 pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
587 /* Set the cache line size, so far 64 bytes is good for everyone. */
588 pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
591 void pci_dev_enable_resources(struct device *dev)
593 const struct pci_operations *ops;
596 /* Set the subsystem vendor and device id for mainboard devices. */
598 if (dev->on_mainboard && ops && ops->set_subsystem) {
599 printk_debug("%s subsystem <- %02x/%02x\n",
601 CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
602 CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
603 ops->set_subsystem(dev,
604 CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
605 CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
607 command = pci_read_config16(dev, PCI_COMMAND);
608 command |= dev->command;
610 * command |= (PCI_COMMAND_PARITY + PCI_COMMAND_SERR); // Error check.
612 printk_debug("%s cmd <- %02x\n", dev_path(dev), command);
613 pci_write_config16(dev, PCI_COMMAND, command);
616 void pci_bus_enable_resources(struct device *dev)
620 /* Enable I/O in command register if there is VGA card
621 * connected with (even it does not claim I/O resource).
623 if (dev->link[0].bridge_ctrl & PCI_BRIDGE_CTL_VGA)
624 dev->command |= PCI_COMMAND_IO;
625 ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
626 ctrl |= dev->link[0].bridge_ctrl;
627 ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* Error check. */
628 printk_debug("%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
629 pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
631 pci_dev_enable_resources(dev);
632 enable_childrens_resources(dev);
635 void pci_bus_reset(struct bus *bus)
638 ctl = pci_read_config16(bus->dev, PCI_BRIDGE_CONTROL);
639 ctl |= PCI_BRIDGE_CTL_BUS_RESET;
640 pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, ctl);
642 ctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
643 pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, ctl);
647 void pci_dev_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
649 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
650 ((device & 0xffff) << 16) | (vendor & 0xffff));
653 /** default handler: only runs the relevant pci bios. */
654 void pci_dev_init(struct device *dev)
656 #if CONFIG_PCI_ROM_RUN == 1 || CONFIG_VGA_ROM_RUN == 1
657 void run_bios(struct device *dev, unsigned long addr);
658 struct rom_header *rom, *ram;
660 if (CONFIG_PCI_ROM_RUN != 1 && /* Only execute VGA ROMs. */
661 ((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA))
664 if (CONFIG_VGA_ROM_RUN != 1 && /* Only execute non-VGA ROMs. */
665 ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA))
668 rom = pci_rom_probe(dev);
672 ram = pci_rom_load(dev, rom);
676 run_bios(dev, (unsigned long)ram);
678 #if CONFIG_CONSOLE_VGA == 1
679 if ((dev->class>>8) == PCI_CLASS_DISPLAY_VGA)
681 #endif /* CONFIG_CONSOLE_VGA */
682 #endif /* CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN */
685 /** Default device operation for PCI devices */
686 static struct pci_operations pci_dev_ops_pci = {
687 .set_subsystem = pci_dev_set_subsystem,
690 struct device_operations default_pci_ops_dev = {
691 .read_resources = pci_dev_read_resources,
692 .set_resources = pci_dev_set_resources,
693 .enable_resources = pci_dev_enable_resources,
694 .init = pci_dev_init,
697 .ops_pci = &pci_dev_ops_pci,
700 /** Default device operations for PCI bridges */
701 static struct pci_operations pci_bus_ops_pci = {
705 struct device_operations default_pci_ops_bus = {
706 .read_resources = pci_bus_read_resources,
707 .set_resources = pci_dev_set_resources,
708 .enable_resources = pci_bus_enable_resources,
710 .scan_bus = pci_scan_bridge,
712 .reset_bus = pci_bus_reset,
713 .ops_pci = &pci_bus_ops_pci,
717 * @brief Detect the type of downstream bridge
719 * This function is a heuristic to detect which type of bus is downstream
720 * of a PCI-to-PCI bridge. This functions by looking for various capability
721 * blocks to figure out the type of downstream bridge. PCI-X, PCI-E, and
722 * Hypertransport all seem to have appropriate capabilities.
724 * When only a PCI-Express capability is found the type
725 * is examined to see which type of bridge we have.
727 * @param dev Pointer to the device structure of the bridge.
728 * @return Appropriate bridge operations.
730 static struct device_operations *get_pci_bridge_ops(device_t dev)
734 #if CONFIG_PCIX_PLUGIN_SUPPORT == 1
735 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
737 printk_debug("%s subordinate bus PCI-X\n", dev_path(dev));
738 return &default_pcix_ops_bus;
741 #if CONFIG_AGP_PLUGIN_SUPPORT == 1
742 /* How do I detect an PCI to AGP bridge? */
744 #if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1
746 while ((pos = pci_find_next_capability(dev, PCI_CAP_ID_HT, pos))) {
748 flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
749 if ((flags >> 13) == 1) {
750 /* Host or Secondary Interface */
751 printk_debug("%s subordinate bus Hypertransport\n",
753 return &default_ht_ops_bus;
757 #if CONFIG_PCIEXP_PLUGIN_SUPPORT == 1
758 pos = pci_find_capability(dev, PCI_CAP_ID_PCIE);
761 flags = pci_read_config16(dev, pos + PCI_EXP_FLAGS);
762 switch ((flags & PCI_EXP_FLAGS_TYPE) >> 4) {
763 case PCI_EXP_TYPE_ROOT_PORT:
764 case PCI_EXP_TYPE_UPSTREAM:
765 case PCI_EXP_TYPE_DOWNSTREAM:
766 printk_debug("%s subordinate bus PCI Express\n",
768 return &default_pciexp_ops_bus;
769 case PCI_EXP_TYPE_PCI_BRIDGE:
770 printk_debug("%s subordinate PCI\n", dev_path(dev));
771 return &default_pci_ops_bus;
777 return &default_pci_ops_bus;
781 * Set up PCI device operation. Check if it already has a driver. If not, use
782 * find_device_operations, or set to a default based on type.
784 * @param dev Pointer to the device whose pci_ops you want to set.
787 static void set_pci_ops(struct device *dev)
789 struct pci_driver *driver;
794 /* Look through the list of setup drivers and find one for
797 for (driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) {
798 if ((driver->vendor == dev->vendor) &&
799 (driver->device == dev->device)) {
800 dev->ops = (struct device_operations *)driver->ops;
801 printk_spew("%s [%04x/%04x] %sops\n",
803 driver->vendor, driver->device,
804 (driver->ops->scan_bus ? "bus " : ""));
809 /* If I don't have a specific driver use the default operations */
810 switch (dev->hdr_type & 0x7f) { /* header type */
811 case PCI_HEADER_TYPE_NORMAL: /* standard header */
812 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
814 dev->ops = &default_pci_ops_dev;
816 case PCI_HEADER_TYPE_BRIDGE:
817 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
819 dev->ops = get_pci_bridge_ops(dev);
821 #if CONFIG_CARDBUS_PLUGIN_SUPPORT == 1
822 case PCI_HEADER_TYPE_CARDBUS:
823 dev->ops = &default_cardbus_ops_bus;
829 printk_err("%s [%04x/%04x/%06x] has unknown header "
830 "type %02x, ignoring.\n",
832 dev->vendor, dev->device,
833 dev->class >> 8, dev->hdr_type);
840 * @brief See if we have already allocated a device structure for a given devfn.
842 * Given a linked list of PCI device structures and a devfn number, find the
843 * device structure correspond to the devfn, if present. This function also
844 * removes the device structure from the linked list.
846 * @param list The device structure list.
847 * @param devfn A device/function number.
849 * @return Pointer to the device structure found or NULL if we have not
850 * allocated a device for this devfn yet.
852 static struct device *pci_scan_get_dev(struct device **list, unsigned int devfn)
856 for (; *list; list = &(*list)->sibling) {
857 if ((*list)->path.type != DEVICE_PATH_PCI) {
858 printk_err("child %s not a pci device\n",
862 if ((*list)->path.pci.devfn == devfn) {
863 /* Unlink from the list. */
865 *list = (*list)->sibling;
871 /* Just like alloc_dev() add the device to the list of devices on the
872 * bus. When the list of devices was formed we removed all of the
873 * parents children, and now we are interleaving static and dynamic
874 * devices in order on the bus.
877 struct device *child;
878 /* Find the last child of our parent. */
879 for (child = dev->bus->children; child && child->sibling;) {
880 child = child->sibling;
882 /* Place the device on the list of children of its parent. */
884 child->sibling = dev;
886 dev->bus->children = dev;
894 * @brief Scan a PCI bus.
896 * Determine the existence of a given PCI device. Allocate a new struct device
897 * if dev==NULL was passed in and the device exists in hardware.
899 * @param bus pointer to the bus structure
900 * @param devfn to look at
902 * @return The device structure for hte device (if found)
903 * or the NULL if no device is found.
905 device_t pci_probe_dev(device_t dev, struct bus * bus, unsigned devfn)
910 /* Detect if a device is present. */
914 dummy.path.type = DEVICE_PATH_PCI;
915 dummy.path.pci.devfn = devfn;
916 id = pci_read_config32(&dummy, PCI_VENDOR_ID);
917 /* Have we found something?
918 * Some broken boards return 0 if a slot is empty.
920 if ((id == 0xffffffff) || (id == 0x00000000) ||
921 (id == 0x0000ffff) || (id == 0xffff0000)) {
922 printk_spew("%s, bad id 0x%x\n", dev_path(&dummy), id);
925 dev = alloc_dev(bus, &dummy.path);
927 /* Enable/disable the device. Once we have found the device-
928 * specific operations this operations we will disable the
929 * device with those as well.
931 * This is geared toward devices that have subfunctions
932 * that do not show up by default.
934 * If a device is a stuff option on the motherboard
935 * it may be absent and enable_dev() must cope.
937 /* Run the magic enable sequence for the device. */
938 if (dev->chip_ops && dev->chip_ops->enable_dev) {
939 dev->chip_ops->enable_dev(dev);
941 /* Now read the vendor and device ID. */
942 id = pci_read_config32(dev, PCI_VENDOR_ID);
944 /* If the device does not have a PCI ID disable it. Possibly
945 * this is because we have already disabled the device. But
946 * this also handles optional devices that may not always
949 /* If the chain is fully enumerated quit */
950 if ((id == 0xffffffff) || (id == 0x00000000) ||
951 (id == 0x0000ffff) || (id == 0xffff0000)) {
953 printk_info("Disabling static device: %s\n",
960 /* Read the rest of the PCI configuration information. */
961 hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
962 class = pci_read_config32(dev, PCI_CLASS_REVISION);
964 /* Store the interesting information in the device structure. */
965 dev->vendor = id & 0xffff;
966 dev->device = (id >> 16) & 0xffff;
967 dev->hdr_type = hdr_type;
969 /* Class code, the upper 3 bytes of PCI_CLASS_REVISION. */
970 dev->class = class >> 8;
972 /* Architectural/System devices always need to be bus masters. */
973 if ((dev->class >> 16) == PCI_BASE_CLASS_SYSTEM) {
974 dev->command |= PCI_COMMAND_MASTER;
976 /* Look at the vendor and device ID, or at least the header type and
977 * class and figure out which set of configuration methods to use.
978 * Unless we already have some PCI ops.
982 /* Now run the magic enable/disable sequence for the device. */
983 if (dev->ops && dev->ops->enable) {
984 dev->ops->enable(dev);
987 /* Display the device. */
988 printk_debug("%s [%04x/%04x] %s%s\n",
990 dev->vendor, dev->device,
991 dev->enabled ? "enabled" : "disabled",
992 dev->ops ? "" : " No operations");
998 * @brief Scan a PCI bus.
1000 * Determine the existence of devices and bridges on a PCI bus. If there are
1001 * bridges on the bus, recursively scan the buses behind the bridges.
1003 * This function is the default scan_bus() method for the root device
1006 * @param bus pointer to the bus structure
1007 * @param min_devfn minimum devfn to look at in the scan usually 0x00
1008 * @param max_devfn maximum devfn to look at in the scan usually 0xff
1009 * @param max current bus number
1011 * @return The maximum bus number found, after scanning all subordinate busses
1013 unsigned int pci_scan_bus(struct bus *bus,
1014 unsigned min_devfn, unsigned max_devfn,
1018 struct device *old_devices;
1019 struct device *child;
1021 #if CONFIG_PCI_BUS_SEGN_BITS
1022 printk_debug("PCI: pci_scan_bus for bus %04x:%02x\n",
1023 bus->secondary >> 8, bus->secondary & 0xff);
1025 printk_debug("PCI: pci_scan_bus for bus %02x\n", bus->secondary);
1028 old_devices = bus->children;
1029 bus->children = NULL;
1032 /* Probe all devices/functions on this bus with some optimization for
1033 * non-existence and single function devices.
1035 for (devfn = min_devfn; devfn <= max_devfn; devfn++) {
1038 /* First thing setup the device structure */
1039 dev = pci_scan_get_dev(&old_devices, devfn);
1041 /* See if a device is present and setup the device structure. */
1042 dev = pci_probe_dev(dev, bus, devfn);
1044 /* If this is not a multi function device, or the device is
1045 * not present don't waste time probing another function.
1046 * Skip to next device.
1048 if ((PCI_FUNC(devfn) == 0x00) &&
1050 || (dev->enabled && ((dev->hdr_type & 0x80) != 0x80)))) {
1056 /* Warn if any leftover static devices are are found.
1057 * There's probably a problem in the Config.lb.
1061 printk_warning("PCI: Left over static devices:\n");
1062 for (left = old_devices; left; left = left->sibling) {
1063 printk_warning("%s\n", dev_path(left));
1065 printk_warning("PCI: Check your mainboard Config.lb.\n");
1068 /* For all children that implement scan_bus() (i.e. bridges)
1069 * scan the bus behind that child.
1071 for (child = bus->children; child; child = child->sibling) {
1072 max = scan_bus(child, max);
1075 /* We've scanned the bus and so we know all about what's on the other
1076 * side of any bridges that may be on this bus plus any devices.
1077 * Return how far we've got finding sub-buses.
1079 printk_debug("PCI: pci_scan_bus returning with max=%03x\n", max);
1085 * @brief Scan a PCI bridge and the buses behind the bridge.
1087 * Determine the existence of buses behind the bridge. Set up the bridge
1088 * according to the result of the scan.
1090 * This function is the default scan_bus() method for PCI bridge devices.
1092 * @param dev Pointer to the bridge device.
1093 * @param max The highest bus number assigned up to now.
1094 * @return The maximum bus number found, after scanning all subordinate buses.
1096 unsigned int do_pci_scan_bridge(struct device *dev, unsigned int max,
1097 unsigned int (*do_scan_bus) (struct bus * bus,
1106 printk_spew("%s for %s\n", __func__, dev_path(dev));
1108 bus = &dev->link[0];
1112 /* Set up the primary, secondary and subordinate bus numbers. We have
1113 * no idea how many buses are behind this bridge yet, so we set the
1114 * subordinate bus number to 0xff for the moment.
1116 bus->secondary = ++max;
1117 bus->subordinate = 0xff;
1119 /* Clear all status bits and turn off memory, I/O and master enables. */
1120 cr = pci_read_config16(dev, PCI_COMMAND);
1121 pci_write_config16(dev, PCI_COMMAND, 0x0000);
1122 pci_write_config16(dev, PCI_STATUS, 0xffff);
1124 /* Read the existing primary/secondary/subordinate bus
1125 * number configuration.
1127 buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
1129 /* Configure the bus numbers for this bridge: the configuration
1130 * transactions will not be propagated by the bridge if it is not
1131 * correctly configured.
1133 buses &= 0xff000000;
1134 buses |= (((unsigned int)(dev->bus->secondary) << 0) |
1135 ((unsigned int)(bus->secondary) << 8) |
1136 ((unsigned int)(bus->subordinate) << 16));
1137 pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
1139 /* Now we can scan all subordinate buses
1140 * i.e. the bus behind the bridge.
1142 max = do_scan_bus(bus, 0x00, 0xff, max);
1144 /* We know the number of buses behind this bridge. Set the subordinate
1145 * bus number to its real value.
1147 bus->subordinate = max;
1148 buses = (buses & 0xff00ffff) | ((unsigned int)(bus->subordinate) << 16);
1149 pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
1150 pci_write_config16(dev, PCI_COMMAND, cr);
1152 printk_spew("%s returns max %d\n", __func__, max);
1157 * @brief Scan a PCI bridge and the buses behind the bridge.
1159 * Determine the existence of buses behind the bridge. Set up the bridge
1160 * according to the result of the scan.
1162 * This function is the default scan_bus() method for PCI bridge devices.
1164 * @param dev Pointer to the bridge device.
1165 * @param max The highest bus number assigned up to now.
1166 * @return The maximum bus number found, after scanning all subordinate buses.
1168 unsigned int pci_scan_bridge(struct device *dev, unsigned int max)
1170 return do_pci_scan_bridge(dev, max, pci_scan_bus);
1174 * @brief Scan a PCI domain.
1176 * This function is the default scan_bus() method for PCI domains.
1178 * @param dev pointer to the domain
1179 * @param max the highest bus number assgined up to now
1181 * @return The maximum bus number found, after scanning all subordinate busses
1183 unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
1185 max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
1189 #if CONFIG_PC80_SYSTEM == 1
1192 * @brief Assign IRQ numbers
1194 * This function assigns IRQs for all functions contained within the indicated
1195 * device address. If the device does not exist or does not require interrupts
1196 * then this function has no effect.
1198 * This function should be called for each PCI slot in your system.
1202 * @param pIntAtoD is an array of IRQ #s that are assigned to PINTA through
1203 * PINTD of this slot. The particular irq #s that are passed in
1204 * depend on the routing inside your southbridge and on your
1207 void pci_assign_irqs(unsigned bus, unsigned slot,
1208 const unsigned char pIntAtoD[4])
1215 /* Each slot may contain up to eight functions */
1216 for (funct = 0; funct < 8; funct++) {
1217 pdev = dev_find_slot(bus, (slot << 3) + funct);
1222 line = pci_read_config8(pdev, PCI_INTERRUPT_PIN);
1224 // PCI spec says all values except 1..4 are reserved.
1225 if ((line < 1) || (line > 4))
1228 irq = pIntAtoD[line - 1];
1230 printk_debug("Assigning IRQ %d to %d:%x.%d\n",
1231 irq, bus, slot, funct);
1233 pci_write_config8(pdev, PCI_INTERRUPT_LINE,
1234 pIntAtoD[line - 1]);
1236 #ifdef PARANOID_IRQ_ASSIGNMENTS
1237 irq = pci_read_config8(pdev, PCI_INTERRUPT_LINE);
1238 printk_debug(" Readback = %d\n", irq);
1241 // Change to level triggered
1242 i8259_configure_irq_trigger(pIntAtoD[line - 1], IRQ_LEVEL_TRIGGERED);