2 * This file is part of the coreboot project.
4 * It was originally based on the Linux kernel (drivers/pci/pci.c).
7 * Copyright (C) 2003-2004 Linux Networx
8 * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
9 * Copyright (C) 2003-2006 Ronald G. Minnich <rminnich@gmail.com>
10 * Copyright (C) 2004-2005 Li-Ta Lo <ollie@lanl.gov>
11 * Copyright (C) 2005-2006 Tyan
12 * (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
13 * Copyright (C) 2005-2009 coresystems GmbH
14 * (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
18 * PCI Bus Services, see include/linux/pci.h for further explanation.
20 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
21 * David Mosberger-Tang
23 * Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
26 #include <console/console.h>
32 #include <device/device.h>
33 #include <device/pci.h>
34 #include <device/pci_ids.h>
36 #if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1
37 #include <device/hypertransport.h>
39 #if CONFIG_PCIX_PLUGIN_SUPPORT == 1
40 #include <device/pcix.h>
42 #if CONFIG_PCIEXP_PLUGIN_SUPPORT == 1
43 #include <device/pciexp.h>
45 #if CONFIG_AGP_PLUGIN_SUPPORT == 1
46 #include <device/agp.h>
48 #if CONFIG_CARDBUS_PLUGIN_SUPPORT == 1
49 #include <device/cardbus.h>
51 #if CONFIG_PC80_SYSTEM == 1
52 #include <pc80/i8259.h>
54 #if CONFIG_HAVE_ACPI_RESUME && !CONFIG_S3_VGA_ROM_RUN
55 #include <arch/acpi.h>
58 u8 pci_moving_config8(struct device *dev, unsigned int reg)
60 u8 value, ones, zeroes;
62 value = pci_read_config8(dev, reg);
64 pci_write_config8(dev, reg, 0xff);
65 ones = pci_read_config8(dev, reg);
67 pci_write_config8(dev, reg, 0x00);
68 zeroes = pci_read_config8(dev, reg);
70 pci_write_config8(dev, reg, value);
75 u16 pci_moving_config16(struct device *dev, unsigned int reg)
77 u16 value, ones, zeroes;
79 value = pci_read_config16(dev, reg);
81 pci_write_config16(dev, reg, 0xffff);
82 ones = pci_read_config16(dev, reg);
84 pci_write_config16(dev, reg, 0x0000);
85 zeroes = pci_read_config16(dev, reg);
87 pci_write_config16(dev, reg, value);
92 u32 pci_moving_config32(struct device *dev, unsigned int reg)
94 u32 value, ones, zeroes;
96 value = pci_read_config32(dev, reg);
98 pci_write_config32(dev, reg, 0xffffffff);
99 ones = pci_read_config32(dev, reg);
101 pci_write_config32(dev, reg, 0x00000000);
102 zeroes = pci_read_config32(dev, reg);
104 pci_write_config32(dev, reg, value);
106 return ones ^ zeroes;
110 * Given a device, a capability type, and a last position, return the next
111 * matching capability. Always start at the head of the list.
113 * @param dev Pointer to the device structure.
114 * @param cap PCI_CAP_LIST_ID of the PCI capability we're looking for.
115 * @param last Location of the PCI capability register to start from.
116 * @return The next matching capability.
118 unsigned pci_find_next_capability(struct device *dev, unsigned cap,
125 status = pci_read_config16(dev, PCI_STATUS);
126 if (!(status & PCI_STATUS_CAP_LIST))
129 switch (dev->hdr_type & 0x7f) {
130 case PCI_HEADER_TYPE_NORMAL:
131 case PCI_HEADER_TYPE_BRIDGE:
132 pos = PCI_CAPABILITY_LIST;
134 case PCI_HEADER_TYPE_CARDBUS:
135 pos = PCI_CB_CAPABILITY_LIST;
141 pos = pci_read_config8(dev, pos);
142 while (reps-- && (pos >= 0x40)) { /* Loop through the linked list. */
146 this_cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID);
147 printk(BIOS_SPEW, "Capability: type 0x%02x @ 0x%02x\n",
149 if (this_cap == 0xff)
152 if (!last && (this_cap == cap))
158 pos = pci_read_config8(dev, pos + PCI_CAP_LIST_NEXT);
164 * Given a device, and a capability type, return the next matching
165 * capability. Always start at the head of the list.
167 * @param dev Pointer to the device structure.
168 * @param cap PCI_CAP_LIST_ID of the PCI capability we're looking for.
169 * @return The next matching capability.
171 unsigned pci_find_capability(device_t dev, unsigned cap)
173 return pci_find_next_capability(dev, cap, 0);
177 * Given a device and register, read the size of the BAR for that register.
179 * @param dev Pointer to the device structure.
180 * @param index Address of the PCI configuration register.
183 struct resource *pci_get_resource(struct device *dev, unsigned long index)
185 struct resource *resource;
186 unsigned long value, attr;
187 resource_t moving, limit;
189 /* Initialize the resources to nothing. */
190 resource = new_resource(dev, index);
192 /* Get the initial value. */
193 value = pci_read_config32(dev, index);
195 /* See which bits move. */
196 moving = pci_moving_config32(dev, index);
198 /* Initialize attr to the bits that do not move. */
199 attr = value & ~moving;
201 /* If it is a 64bit resource look at the high half as well. */
202 if (((attr & PCI_BASE_ADDRESS_SPACE_IO) == 0) &&
203 ((attr & PCI_BASE_ADDRESS_MEM_LIMIT_MASK) ==
204 PCI_BASE_ADDRESS_MEM_LIMIT_64)) {
205 /* Find the high bits that move. */
207 ((resource_t) pci_moving_config32(dev, index + 4)) << 32;
210 /* Find the resource constraints.
211 * Start by finding the bits that move. From there:
212 * - Size is the least significant bit of the bits that move.
213 * - Limit is all of the bits that move plus all of the lower bits.
214 * See PCI Spec 6.2.5.1.
219 resource->align = resource->gran = 0;
220 while (!(moving & resource->size)) {
221 resource->size <<= 1;
222 resource->align += 1;
225 resource->limit = limit = moving | (resource->size - 1);
229 * Some broken hardware has read-only registers that do not
230 * really size correctly.
232 * Example: the Acer M7229 has BARs 1-4 normally read-only,
233 * so BAR1 at offset 0x10 reads 0x1f1. If you size that register
234 * by writing 0xffffffff to it, it will read back as 0x1f1 -- which
235 * is a violation of the spec.
237 * We catch this case and ignore it by observing which bits move.
239 * This also catches the common case of unimplemented registers
240 * that always read back as 0.
244 printk(BIOS_DEBUG, "%s register %02lx(%08lx), "
245 "read-only ignoring it\n",
246 dev_path(dev), index, value);
249 } else if (attr & PCI_BASE_ADDRESS_SPACE_IO) {
250 /* An I/O mapped base address. */
251 attr &= PCI_BASE_ADDRESS_IO_ATTR_MASK;
252 resource->flags |= IORESOURCE_IO;
253 /* I don't want to deal with 32bit I/O resources. */
254 resource->limit = 0xffff;
256 /* A Memory mapped base address. */
257 attr &= PCI_BASE_ADDRESS_MEM_ATTR_MASK;
258 resource->flags |= IORESOURCE_MEM;
259 if (attr & PCI_BASE_ADDRESS_MEM_PREFETCH)
260 resource->flags |= IORESOURCE_PREFETCH;
261 attr &= PCI_BASE_ADDRESS_MEM_LIMIT_MASK;
262 if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_32) {
264 resource->limit = 0xffffffffUL;
265 } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_1M) {
267 resource->limit = 0x000fffffUL;
268 } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_64) {
270 resource->limit = 0xffffffffffffffffULL;
271 resource->flags |= IORESOURCE_PCI64;
274 printk(BIOS_ERR, "Broken BAR with value %lx\n", attr);
275 printk(BIOS_ERR, " on dev %s at index %02lx\n",
276 dev_path(dev), index);
281 /* Don't let the limit exceed which bits can move. */
282 if (resource->limit > limit)
283 resource->limit = limit;
289 * Given a device and an index, read the size of the BAR for that register.
291 * @param dev Pointer to the device structure.
292 * @param index Address of the PCI configuration register.
294 static void pci_get_rom_resource(struct device *dev, unsigned long index)
296 struct resource *resource;
300 /* Initialize the resources to nothing. */
301 resource = new_resource(dev, index);
303 /* Get the initial value. */
304 value = pci_read_config32(dev, index);
306 /* See which bits move. */
307 moving = pci_moving_config32(dev, index);
309 /* Clear the Enable bit. */
310 moving = moving & ~PCI_ROM_ADDRESS_ENABLE;
312 /* Find the resource constraints.
313 * Start by finding the bits that move. From there:
314 * - Size is the least significant bit of the bits that move.
315 * - Limit is all of the bits that move plus all of the lower bits.
316 * See PCI Spec 6.2.5.1.
320 resource->align = resource->gran = 0;
321 while (!(moving & resource->size)) {
322 resource->size <<= 1;
323 resource->align += 1;
326 resource->limit = moving | (resource->size - 1);
327 resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY;
330 printk(BIOS_DEBUG, "%s register %02lx(%08lx), "
331 "read-only ignoring it\n",
332 dev_path(dev), index, value);
336 compact_resources(dev);
340 * Read the base address registers for a given device.
342 * @param dev Pointer to the dev structure.
343 * @param howmany How many registers to read (6 for device, 2 for bridge).
345 static void pci_read_bases(struct device *dev, unsigned int howmany)
349 for (index = PCI_BASE_ADDRESS_0;
350 (index < PCI_BASE_ADDRESS_0 + (howmany << 2));) {
351 struct resource *resource;
352 resource = pci_get_resource(dev, index);
353 index += (resource->flags & IORESOURCE_PCI64) ? 8 : 4;
356 compact_resources(dev);
359 static void pci_record_bridge_resource(struct device *dev, resource_t moving,
360 unsigned index, unsigned long type)
362 struct resource *resource;
371 /* Initialize the constraints on the current bus. */
372 resource = new_resource(dev, index);
376 while ((moving & step) == 0) {
380 resource->gran = gran;
381 resource->align = gran;
382 resource->limit = moving | (step - 1);
383 resource->flags = type | IORESOURCE_PCI_BRIDGE |
387 static void pci_bridge_read_bases(struct device *dev)
389 resource_t moving_base, moving_limit, moving;
391 /* See if the bridge I/O resources are implemented. */
392 moving_base = ((u32) pci_moving_config8(dev, PCI_IO_BASE)) << 8;
394 ((u32) pci_moving_config16(dev, PCI_IO_BASE_UPPER16)) << 16;
396 moving_limit = ((u32) pci_moving_config8(dev, PCI_IO_LIMIT)) << 8;
398 ((u32) pci_moving_config16(dev, PCI_IO_LIMIT_UPPER16)) << 16;
400 moving = moving_base & moving_limit;
402 /* Initialize the I/O space constraints on the current bus. */
403 pci_record_bridge_resource(dev, moving, PCI_IO_BASE, IORESOURCE_IO);
405 /* See if the bridge prefmem resources are implemented. */
407 ((resource_t) pci_moving_config16(dev, PCI_PREF_MEMORY_BASE)) << 16;
409 ((resource_t) pci_moving_config32(dev, PCI_PREF_BASE_UPPER32)) << 32;
412 ((resource_t) pci_moving_config16(dev, PCI_PREF_MEMORY_LIMIT)) << 16;
414 ((resource_t) pci_moving_config32(dev, PCI_PREF_LIMIT_UPPER32)) << 32;
416 moving = moving_base & moving_limit;
417 /* Initialize the prefetchable memory constraints on the current bus. */
418 pci_record_bridge_resource(dev, moving, PCI_PREF_MEMORY_BASE,
419 IORESOURCE_MEM | IORESOURCE_PREFETCH);
421 /* See if the bridge mem resources are implemented. */
422 moving_base = ((u32) pci_moving_config16(dev, PCI_MEMORY_BASE)) << 16;
423 moving_limit = ((u32) pci_moving_config16(dev, PCI_MEMORY_LIMIT)) << 16;
425 moving = moving_base & moving_limit;
427 /* Initialize the memory resources on the current bus. */
428 pci_record_bridge_resource(dev, moving, PCI_MEMORY_BASE,
431 compact_resources(dev);
434 void pci_dev_read_resources(struct device *dev)
436 pci_read_bases(dev, 6);
437 pci_get_rom_resource(dev, PCI_ROM_ADDRESS);
440 void pci_bus_read_resources(struct device *dev)
442 pci_bridge_read_bases(dev);
443 pci_read_bases(dev, 2);
444 pci_get_rom_resource(dev, PCI_ROM_ADDRESS1);
447 void pci_domain_read_resources(struct device *dev)
449 struct resource *res;
451 /* Initialize the system-wide I/O space constraints. */
452 res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
453 res->limit = 0xffffUL;
454 res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
457 /* Initialize the system-wide memory resources constraints. */
458 res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
459 res->limit = 0xffffffffULL;
460 res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
464 static void pci_set_resource(struct device *dev, struct resource *resource)
466 resource_t base, end;
468 /* Make certain the resource has actually been assigned a value. */
469 if (!(resource->flags & IORESOURCE_ASSIGNED)) {
470 printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010llx not "
471 "assigned\n", dev_path(dev), resource->index,
472 resource_type(resource), resource->size);
476 /* If this resource is fixed don't worry about it. */
477 if (resource->flags & IORESOURCE_FIXED)
480 /* If I have already stored this resource don't worry about it. */
481 if (resource->flags & IORESOURCE_STORED)
484 /* If the resource is subtractive don't worry about it. */
485 if (resource->flags & IORESOURCE_SUBTRACTIVE)
488 /* Only handle PCI memory and I/O resources for now. */
489 if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
492 /* Enable the resources in the command register. */
493 if (resource->size) {
494 if (resource->flags & IORESOURCE_MEM)
495 dev->command |= PCI_COMMAND_MEMORY;
496 if (resource->flags & IORESOURCE_IO)
497 dev->command |= PCI_COMMAND_IO;
498 if (resource->flags & IORESOURCE_PCI_BRIDGE)
499 dev->command |= PCI_COMMAND_MASTER;
502 /* Get the base address. */
503 base = resource->base;
506 end = resource_end(resource);
508 /* Now store the resource. */
509 resource->flags |= IORESOURCE_STORED;
512 * PCI bridges have no enable bit. They are disabled if the base of
513 * the range is greater than the limit. If the size is zero, disable
514 * by setting the base = limit and end = limit - 2^gran.
516 if (resource->size == 0 && (resource->flags & IORESOURCE_PCI_BRIDGE)) {
517 base = resource->limit;
518 end = resource->limit - (1 << resource->gran);
519 resource->base = base;
522 if (!(resource->flags & IORESOURCE_PCI_BRIDGE)) {
523 unsigned long base_lo, base_hi;
526 * Some chipsets allow us to set/clear the I/O bit
527 * (e.g. VIA 82C686A). So set it to be safe.
529 base_lo = base & 0xffffffff;
530 base_hi = (base >> 32) & 0xffffffff;
531 if (resource->flags & IORESOURCE_IO)
532 base_lo |= PCI_BASE_ADDRESS_SPACE_IO;
533 pci_write_config32(dev, resource->index, base_lo);
534 if (resource->flags & IORESOURCE_PCI64)
535 pci_write_config32(dev, resource->index + 4, base_hi);
536 } else if (resource->index == PCI_IO_BASE) {
537 /* Set the I/O ranges. */
538 pci_write_config8(dev, PCI_IO_BASE, base >> 8);
539 pci_write_config16(dev, PCI_IO_BASE_UPPER16, base >> 16);
540 pci_write_config8(dev, PCI_IO_LIMIT, end >> 8);
541 pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, end >> 16);
542 } else if (resource->index == PCI_MEMORY_BASE) {
543 /* Set the memory range. */
544 pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);
545 pci_write_config16(dev, PCI_MEMORY_LIMIT, end >> 16);
546 } else if (resource->index == PCI_PREF_MEMORY_BASE) {
547 /* Set the prefetchable memory range. */
548 pci_write_config16(dev, PCI_PREF_MEMORY_BASE, base >> 16);
549 pci_write_config32(dev, PCI_PREF_BASE_UPPER32, base >> 32);
550 pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, end >> 16);
551 pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, end >> 32);
553 /* Don't let me think I stored the resource. */
554 resource->flags &= ~IORESOURCE_STORED;
555 printk(BIOS_ERR, "ERROR: invalid resource->index %lx\n",
559 report_resource_stored(dev, resource, "");
562 void pci_dev_set_resources(struct device *dev)
564 struct resource *res;
568 for (res = dev->resource_list; res; res = res->next)
569 pci_set_resource(dev, res);
571 for (bus = dev->link_list; bus; bus = bus->next) {
573 assign_resources(bus);
576 /* Set a default latency timer. */
577 pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
579 /* Set a default secondary latency timer. */
580 if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE)
581 pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
583 /* Zero the IRQ settings. */
584 line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
586 pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
588 /* Set the cache line size, so far 64 bytes is good for everyone. */
589 pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
592 void pci_dev_enable_resources(struct device *dev)
594 const struct pci_operations *ops;
597 /* Set the subsystem vendor and device ID for mainboard devices. */
599 if (dev->on_mainboard && ops && ops->set_subsystem) {
600 printk(BIOS_DEBUG, "%s subsystem <- %04x/%04x\n",
601 dev_path(dev), dev->subsystem_vendor,
602 dev->subsystem_device);
603 ops->set_subsystem(dev, dev->subsystem_vendor,
604 dev->subsystem_device);
606 command = pci_read_config16(dev, PCI_COMMAND);
607 command |= dev->command;
610 * command |= (PCI_COMMAND_PARITY + PCI_COMMAND_SERR); // Error check.
613 printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command);
614 pci_write_config16(dev, PCI_COMMAND, command);
617 void pci_bus_enable_resources(struct device *dev)
622 * Enable I/O in command register if there is VGA card
623 * connected with (even it does not claim I/O resource).
625 if (dev->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA)
626 dev->command |= PCI_COMMAND_IO;
627 ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
628 ctrl |= dev->link_list->bridge_ctrl;
629 ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* Error check. */
630 printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
631 pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
633 pci_dev_enable_resources(dev);
636 void pci_bus_reset(struct bus *bus)
640 ctl = pci_read_config16(bus->dev, PCI_BRIDGE_CONTROL);
641 ctl |= PCI_BRIDGE_CTL_BUS_RESET;
642 pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, ctl);
645 ctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
646 pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, ctl);
650 void pci_dev_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
652 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
653 ((device & 0xffff) << 16) | (vendor & 0xffff));
656 /** Default handler: only runs the relevant PCI BIOS. */
657 void pci_dev_init(struct device *dev)
659 #if CONFIG_PCI_ROM_RUN == 1 || CONFIG_VGA_ROM_RUN == 1
660 struct rom_header *rom, *ram;
662 if (CONFIG_PCI_ROM_RUN != 1 && /* Only execute VGA ROMs. */
663 ((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA))
666 if (CONFIG_VGA_ROM_RUN != 1 && /* Only execute non-VGA ROMs. */
667 ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA))
670 rom = pci_rom_probe(dev);
674 ram = pci_rom_load(dev, rom);
678 #if CONFIG_HAVE_ACPI_RESUME && !CONFIG_S3_VGA_ROM_RUN
679 /* If S3_VGA_ROM_RUN is disabled, skip running VGA option
680 * ROMs when coming out of an S3 resume.
682 if ((acpi_slp_type == 3) &&
683 ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA))
686 run_bios(dev, (unsigned long)ram);
687 #endif /* CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN */
690 /** Default device operation for PCI devices */
691 static struct pci_operations pci_dev_ops_pci = {
692 .set_subsystem = pci_dev_set_subsystem,
695 struct device_operations default_pci_ops_dev = {
696 .read_resources = pci_dev_read_resources,
697 .set_resources = pci_dev_set_resources,
698 .enable_resources = pci_dev_enable_resources,
699 .init = pci_dev_init,
702 .ops_pci = &pci_dev_ops_pci,
705 /** Default device operations for PCI bridges */
706 static struct pci_operations pci_bus_ops_pci = {
710 struct device_operations default_pci_ops_bus = {
711 .read_resources = pci_bus_read_resources,
712 .set_resources = pci_dev_set_resources,
713 .enable_resources = pci_bus_enable_resources,
715 .scan_bus = pci_scan_bridge,
717 .reset_bus = pci_bus_reset,
718 .ops_pci = &pci_bus_ops_pci,
722 * Detect the type of downstream bridge.
724 * This function is a heuristic to detect which type of bus is downstream
725 * of a PCI-to-PCI bridge. This functions by looking for various capability
726 * blocks to figure out the type of downstream bridge. PCI-X, PCI-E, and
727 * Hypertransport all seem to have appropriate capabilities.
729 * When only a PCI-Express capability is found the type is examined to see
730 * which type of bridge we have.
732 * @param dev Pointer to the device structure of the bridge.
733 * @return Appropriate bridge operations.
735 static struct device_operations *get_pci_bridge_ops(device_t dev)
739 #if CONFIG_PCIX_PLUGIN_SUPPORT == 1
740 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
742 printk(BIOS_DEBUG, "%s subordinate bus PCI-X\n", dev_path(dev));
743 return &default_pcix_ops_bus;
746 #if CONFIG_AGP_PLUGIN_SUPPORT == 1
747 /* How do I detect a PCI to AGP bridge? */
749 #if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1
751 while ((pos = pci_find_next_capability(dev, PCI_CAP_ID_HT, pos))) {
753 flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
754 if ((flags >> 13) == 1) {
755 /* Host or Secondary Interface */
756 printk(BIOS_DEBUG, "%s subordinate bus HT\n",
758 return &default_ht_ops_bus;
762 #if CONFIG_PCIEXP_PLUGIN_SUPPORT == 1
763 pos = pci_find_capability(dev, PCI_CAP_ID_PCIE);
766 flags = pci_read_config16(dev, pos + PCI_EXP_FLAGS);
767 switch ((flags & PCI_EXP_FLAGS_TYPE) >> 4) {
768 case PCI_EXP_TYPE_ROOT_PORT:
769 case PCI_EXP_TYPE_UPSTREAM:
770 case PCI_EXP_TYPE_DOWNSTREAM:
771 printk(BIOS_DEBUG, "%s subordinate bus PCI Express\n",
773 return &default_pciexp_ops_bus;
774 case PCI_EXP_TYPE_PCI_BRIDGE:
775 printk(BIOS_DEBUG, "%s subordinate PCI\n",
777 return &default_pci_ops_bus;
783 return &default_pci_ops_bus;
787 * Set up PCI device operation.
789 * Check if it already has a driver. If not, use find_device_operations(),
790 * or set to a default based on type.
792 * @param dev Pointer to the device whose pci_ops you want to set.
795 static void set_pci_ops(struct device *dev)
797 struct pci_driver *driver;
803 * Look through the list of setup drivers and find one for
806 for (driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) {
807 if ((driver->vendor == dev->vendor) &&
808 (driver->device == dev->device)) {
809 dev->ops = (struct device_operations *)driver->ops;
810 printk(BIOS_SPEW, "%s [%04x/%04x] %sops\n",
811 dev_path(dev), driver->vendor, driver->device,
812 (driver->ops->scan_bus ? "bus " : ""));
817 /* If I don't have a specific driver use the default operations. */
818 switch (dev->hdr_type & 0x7f) { /* Header type */
819 case PCI_HEADER_TYPE_NORMAL:
820 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
822 dev->ops = &default_pci_ops_dev;
824 case PCI_HEADER_TYPE_BRIDGE:
825 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
827 dev->ops = get_pci_bridge_ops(dev);
829 #if CONFIG_CARDBUS_PLUGIN_SUPPORT == 1
830 case PCI_HEADER_TYPE_CARDBUS:
831 dev->ops = &default_cardbus_ops_bus;
837 printk(BIOS_ERR, "%s [%04x/%04x/%06x] has unknown "
838 "header type %02x, ignoring.\n", dev_path(dev),
839 dev->vendor, dev->device,
840 dev->class >> 8, dev->hdr_type);
846 * See if we have already allocated a device structure for a given devfn.
848 * Given a linked list of PCI device structures and a devfn number, find the
849 * device structure correspond to the devfn, if present. This function also
850 * removes the device structure from the linked list.
852 * @param list The device structure list.
853 * @param devfn A device/function number.
854 * @return Pointer to the device structure found or NULL if we have not
855 * allocated a device for this devfn yet.
857 static struct device *pci_scan_get_dev(struct device **list, unsigned int devfn)
862 for (; *list; list = &(*list)->sibling) {
863 if ((*list)->path.type != DEVICE_PATH_PCI) {
864 printk(BIOS_ERR, "child %s not a PCI device\n",
868 if ((*list)->path.pci.devfn == devfn) {
869 /* Unlink from the list. */
871 *list = (*list)->sibling;
878 * Just like alloc_dev() add the device to the list of devices on the
879 * bus. When the list of devices was formed we removed all of the
880 * parents children, and now we are interleaving static and dynamic
881 * devices in order on the bus.
884 struct device *child;
886 /* Find the last child of our parent. */
887 for (child = dev->bus->children; child && child->sibling;)
888 child = child->sibling;
890 /* Place the device on the list of children of its parent. */
892 child->sibling = dev;
894 dev->bus->children = dev;
903 * Determine the existence of a given PCI device. Allocate a new struct device
904 * if dev==NULL was passed in and the device exists in hardware.
906 * @param dev Pointer to the dev structure.
907 * @param bus Pointer to the bus structure.
908 * @param devfn A device/function number to look at.
909 * @return The device structure for the device (if found), NULL otherwise.
911 device_t pci_probe_dev(device_t dev, struct bus *bus, unsigned devfn)
916 /* Detect if a device is present. */
921 dummy.path.type = DEVICE_PATH_PCI;
922 dummy.path.pci.devfn = devfn;
924 id = pci_read_config32(&dummy, PCI_VENDOR_ID);
926 * Have we found something? Some broken boards return 0 if a
927 * slot is empty, but the expected answer is 0xffffffff.
929 if (id == 0xffffffff)
932 if ((id == 0x00000000) || (id == 0x0000ffff) ||
933 (id == 0xffff0000)) {
934 printk(BIOS_SPEW, "%s, bad id 0x%x\n",
935 dev_path(&dummy), id);
938 dev = alloc_dev(bus, &dummy.path);
941 * Enable/disable the device. Once we have found the device-
942 * specific operations this operations we will disable the
943 * device with those as well.
945 * This is geared toward devices that have subfunctions
946 * that do not show up by default.
948 * If a device is a stuff option on the motherboard
949 * it may be absent and enable_dev() must cope.
951 /* Run the magic enable sequence for the device. */
952 if (dev->chip_ops && dev->chip_ops->enable_dev)
953 dev->chip_ops->enable_dev(dev);
955 /* Now read the vendor and device ID. */
956 id = pci_read_config32(dev, PCI_VENDOR_ID);
959 * If the device does not have a PCI ID disable it. Possibly
960 * this is because we have already disabled the device. But
961 * this also handles optional devices that may not always
964 /* If the chain is fully enumerated quit */
965 if ((id == 0xffffffff) || (id == 0x00000000) ||
966 (id == 0x0000ffff) || (id == 0xffff0000)) {
968 printk(BIOS_INFO, "PCI: Static device %s not "
969 "found, disabling it.\n", dev_path(dev));
976 /* Read the rest of the PCI configuration information. */
977 hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
978 class = pci_read_config32(dev, PCI_CLASS_REVISION);
980 /* Store the interesting information in the device structure. */
981 dev->vendor = id & 0xffff;
982 dev->device = (id >> 16) & 0xffff;
983 dev->hdr_type = hdr_type;
985 /* Class code, the upper 3 bytes of PCI_CLASS_REVISION. */
986 dev->class = class >> 8;
988 /* Architectural/System devices always need to be bus masters. */
989 if ((dev->class >> 16) == PCI_BASE_CLASS_SYSTEM)
990 dev->command |= PCI_COMMAND_MASTER;
993 * Look at the vendor and device ID, or at least the header type and
994 * class and figure out which set of configuration methods to use.
995 * Unless we already have some PCI ops.
999 /* Now run the magic enable/disable sequence for the device. */
1000 if (dev->ops && dev->ops->enable)
1001 dev->ops->enable(dev);
1003 /* Display the device. */
1004 printk(BIOS_DEBUG, "%s [%04x/%04x] %s%s\n", dev_path(dev),
1005 dev->vendor, dev->device, dev->enabled ? "enabled" : "disabled",
1006 dev->ops ? "" : " No operations");
1014 * Determine the existence of devices and bridges on a PCI bus. If there are
1015 * bridges on the bus, recursively scan the buses behind the bridges.
1017 * This function is the default scan_bus() method for the root device
1020 * @param bus Pointer to the bus structure.
1021 * @param min_devfn Minimum devfn to look at in the scan, usually 0x00.
1022 * @param max_devfn Maximum devfn to look at in the scan, usually 0xff.
1023 * @param max Current bus number.
1024 * @return The maximum bus number found, after scanning all subordinate busses.
1026 unsigned int pci_scan_bus(struct bus *bus, unsigned min_devfn,
1027 unsigned max_devfn, unsigned int max)
1030 struct device *old_devices;
1031 struct device *child;
1033 #if CONFIG_PCI_BUS_SEGN_BITS
1034 printk(BIOS_DEBUG, "PCI: pci_scan_bus for bus %04x:%02x\n",
1035 bus->secondary >> 8, bus->secondary & 0xff);
1037 printk(BIOS_DEBUG, "PCI: pci_scan_bus for bus %02x\n", bus->secondary);
1040 /* Maximum sane devfn is 0xFF. */
1041 if (max_devfn > 0xff) {
1042 printk(BIOS_ERR, "PCI: pci_scan_bus limits devfn %x - "
1043 "devfn %x\n", min_devfn, max_devfn);
1044 printk(BIOS_ERR, "PCI: pci_scan_bus upper limit too big. "
1049 old_devices = bus->children;
1050 bus->children = NULL;
1055 * Probe all devices/functions on this bus with some optimization for
1056 * non-existence and single function devices.
1058 for (devfn = min_devfn; devfn <= max_devfn; devfn++) {
1061 /* First thing setup the device structure. */
1062 dev = pci_scan_get_dev(&old_devices, devfn);
1064 /* See if a device is present and setup the device structure. */
1065 dev = pci_probe_dev(dev, bus, devfn);
1068 * If this is not a multi function device, or the device is
1069 * not present don't waste time probing another function.
1070 * Skip to next device.
1072 if ((PCI_FUNC(devfn) == 0x00) && (!dev
1073 || (dev->enabled && ((dev->hdr_type & 0x80) != 0x80)))) {
1081 * Warn if any leftover static devices are are found.
1082 * There's probably a problem in devicetree.cb.
1086 printk(BIOS_WARNING, "PCI: Left over static devices:\n");
1087 for (left = old_devices; left; left = left->sibling)
1088 printk(BIOS_WARNING, "%s\n", dev_path(left));
1090 printk(BIOS_WARNING, "PCI: Check your devicetree.cb.\n");
1094 * For all children that implement scan_bus() (i.e. bridges)
1095 * scan the bus behind that child.
1097 for (child = bus->children; child; child = child->sibling)
1098 max = scan_bus(child, max);
1101 * We've scanned the bus and so we know all about what's on the other
1102 * side of any bridges that may be on this bus plus any devices.
1103 * Return how far we've got finding sub-buses.
1105 printk(BIOS_DEBUG, "PCI: pci_scan_bus returning with max=%03x\n", max);
1111 * Scan a PCI bridge and the buses behind the bridge.
1113 * Determine the existence of buses behind the bridge. Set up the bridge
1114 * according to the result of the scan.
1116 * This function is the default scan_bus() method for PCI bridge devices.
1118 * @param dev Pointer to the bridge device.
1119 * @param max The highest bus number assigned up to now.
1120 * @param do_scan_bus TODO
1121 * @return The maximum bus number found, after scanning all subordinate buses.
1123 unsigned int do_pci_scan_bridge(struct device *dev, unsigned int max,
1124 unsigned int (*do_scan_bus) (struct bus * bus,
1133 printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(dev));
1135 if (dev->link_list == NULL) {
1137 link = malloc(sizeof(*link));
1139 die("Couldn't allocate a link!\n");
1140 memset(link, 0, sizeof(*link));
1142 dev->link_list = link;
1145 bus = dev->link_list;
1148 * Set up the primary, secondary and subordinate bus numbers. We have
1149 * no idea how many buses are behind this bridge yet, so we set the
1150 * subordinate bus number to 0xff for the moment.
1152 bus->secondary = ++max;
1153 bus->subordinate = 0xff;
1155 /* Clear all status bits and turn off memory, I/O and master enables. */
1156 cr = pci_read_config16(dev, PCI_COMMAND);
1157 pci_write_config16(dev, PCI_COMMAND, 0x0000);
1158 pci_write_config16(dev, PCI_STATUS, 0xffff);
1161 * Read the existing primary/secondary/subordinate bus
1162 * number configuration.
1164 buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
1167 * Configure the bus numbers for this bridge: the configuration
1168 * transactions will not be propagated by the bridge if it is not
1169 * correctly configured.
1171 buses &= 0xff000000;
1172 buses |= (((unsigned int)(dev->bus->secondary) << 0) |
1173 ((unsigned int)(bus->secondary) << 8) |
1174 ((unsigned int)(bus->subordinate) << 16));
1175 pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
1177 /* Now we can scan all subordinate buses (those behind the bridge). */
1178 max = do_scan_bus(bus, 0x00, 0xff, max);
1181 * We know the number of buses behind this bridge. Set the subordinate
1182 * bus number to its real value.
1184 bus->subordinate = max;
1185 buses = (buses & 0xff00ffff) | ((unsigned int)(bus->subordinate) << 16);
1186 pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
1187 pci_write_config16(dev, PCI_COMMAND, cr);
1189 printk(BIOS_SPEW, "%s returns max %d\n", __func__, max);
1194 * Scan a PCI bridge and the buses behind the bridge.
1196 * Determine the existence of buses behind the bridge. Set up the bridge
1197 * according to the result of the scan.
1199 * This function is the default scan_bus() method for PCI bridge devices.
1201 * @param dev Pointer to the bridge device.
1202 * @param max The highest bus number assigned up to now.
1203 * @return The maximum bus number found, after scanning all subordinate buses.
1205 unsigned int pci_scan_bridge(struct device *dev, unsigned int max)
1207 return do_pci_scan_bridge(dev, max, pci_scan_bus);
1211 * Scan a PCI domain.
1213 * This function is the default scan_bus() method for PCI domains.
1215 * @param dev Pointer to the domain.
1216 * @param max The highest bus number assigned up to now.
1217 * @return The maximum bus number found, after scanning all subordinate busses.
1219 unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
1221 max = pci_scan_bus(dev->link_list, PCI_DEVFN(0, 0), 0xff, max);
1225 #if CONFIG_PC80_SYSTEM == 1
1227 * Assign IRQ numbers.
1229 * This function assigns IRQs for all functions contained within the indicated
1230 * device address. If the device does not exist or does not require interrupts
1231 * then this function has no effect.
1233 * This function should be called for each PCI slot in your system.
1235 * @param bus Pointer to the bus structure.
1237 * @param pIntAtoD An array of IRQ #s that are assigned to PINTA through PINTD
1238 * of this slot. The particular IRQ #s that are passed in depend on the
1239 * routing inside your southbridge and on your board.
1241 void pci_assign_irqs(unsigned bus, unsigned slot,
1242 const unsigned char pIntAtoD[4])
1248 /* Each slot may contain up to eight functions. */
1249 for (funct = 0; funct < 8; funct++) {
1250 pdev = dev_find_slot(bus, (slot << 3) + funct);
1255 line = pci_read_config8(pdev, PCI_INTERRUPT_PIN);
1257 /* PCI spec says all values except 1..4 are reserved. */
1258 if ((line < 1) || (line > 4))
1261 irq = pIntAtoD[line - 1];
1263 printk(BIOS_DEBUG, "Assigning IRQ %d to %d:%x.%d\n",
1264 irq, bus, slot, funct);
1266 pci_write_config8(pdev, PCI_INTERRUPT_LINE,
1267 pIntAtoD[line - 1]);
1269 #ifdef PARANOID_IRQ_ASSIGNMENTS
1270 irq = pci_read_config8(pdev, PCI_INTERRUPT_LINE);
1271 printk(BIOS_DEBUG, " Readback = %d\n", irq);
1274 #if CONFIG_PC80_SYSTEM == 1
1275 /* Change to level triggered. */
1276 i8259_configure_irq_trigger(pIntAtoD[line - 1],
1277 IRQ_LEVEL_TRIGGERED);