2 * This file is part of the coreboot project.
4 * It was originally based on the Linux kernel (drivers/pci/pci.c).
7 * Copyright (C) 2003-2004 Linux Networx
8 * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
9 * Copyright (C) 2003-2006 Ronald G. Minnich <rminnich@gmail.com>
10 * Copyright (C) 2004-2005 Li-Ta Lo <ollie@lanl.gov>
11 * Copyright (C) 2005-2006 Tyan
12 * (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
13 * Copyright (C) 2005-2009 coresystems GmbH
14 * (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
18 * PCI Bus Services, see include/linux/pci.h for further explanation.
20 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
21 * David Mosberger-Tang
23 * Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
26 #include <console/console.h>
32 #include <device/device.h>
33 #include <device/pci.h>
34 #include <device/pci_ids.h>
36 #if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1
37 #include <device/hypertransport.h>
39 #if CONFIG_PCIX_PLUGIN_SUPPORT == 1
40 #include <device/pcix.h>
42 #if CONFIG_PCIEXP_PLUGIN_SUPPORT == 1
43 #include <device/pciexp.h>
45 #if CONFIG_AGP_PLUGIN_SUPPORT == 1
46 #include <device/agp.h>
48 #if CONFIG_CARDBUS_PLUGIN_SUPPORT == 1
49 #include <device/cardbus.h>
51 #define CONFIG_PC80_SYSTEM 1
52 #if CONFIG_PC80_SYSTEM == 1
53 #include <pc80/i8259.h>
56 u8 pci_moving_config8(struct device *dev, unsigned int reg)
58 u8 value, ones, zeroes;
60 value = pci_read_config8(dev, reg);
62 pci_write_config8(dev, reg, 0xff);
63 ones = pci_read_config8(dev, reg);
65 pci_write_config8(dev, reg, 0x00);
66 zeroes = pci_read_config8(dev, reg);
68 pci_write_config8(dev, reg, value);
73 u16 pci_moving_config16(struct device *dev, unsigned int reg)
75 u16 value, ones, zeroes;
77 value = pci_read_config16(dev, reg);
79 pci_write_config16(dev, reg, 0xffff);
80 ones = pci_read_config16(dev, reg);
82 pci_write_config16(dev, reg, 0x0000);
83 zeroes = pci_read_config16(dev, reg);
85 pci_write_config16(dev, reg, value);
90 u32 pci_moving_config32(struct device *dev, unsigned int reg)
92 u32 value, ones, zeroes;
94 value = pci_read_config32(dev, reg);
96 pci_write_config32(dev, reg, 0xffffffff);
97 ones = pci_read_config32(dev, reg);
99 pci_write_config32(dev, reg, 0x00000000);
100 zeroes = pci_read_config32(dev, reg);
102 pci_write_config32(dev, reg, value);
104 return ones ^ zeroes;
108 * Given a device, a capability type, and a last position, return the next
109 * matching capability. Always start at the head of the list.
111 * @param dev Pointer to the device structure.
112 * @param cap PCI_CAP_LIST_ID of the PCI capability we're looking for.
113 * @param last Location of the PCI capability register to start from.
114 * @return The next matching capability.
116 unsigned pci_find_next_capability(struct device *dev, unsigned cap,
123 status = pci_read_config16(dev, PCI_STATUS);
124 if (!(status & PCI_STATUS_CAP_LIST))
127 switch (dev->hdr_type & 0x7f) {
128 case PCI_HEADER_TYPE_NORMAL:
129 case PCI_HEADER_TYPE_BRIDGE:
130 pos = PCI_CAPABILITY_LIST;
132 case PCI_HEADER_TYPE_CARDBUS:
133 pos = PCI_CB_CAPABILITY_LIST;
139 pos = pci_read_config8(dev, pos);
140 while (reps-- && (pos >= 0x40)) { /* Loop through the linked list. */
144 this_cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID);
145 printk(BIOS_SPEW, "Capability: type 0x%02x @ 0x%02x\n",
147 if (this_cap == 0xff)
150 if (!last && (this_cap == cap))
156 pos = pci_read_config8(dev, pos + PCI_CAP_LIST_NEXT);
162 * Given a device, and a capability type, return the next matching
163 * capability. Always start at the head of the list.
165 * @param dev Pointer to the device structure.
166 * @param cap PCI_CAP_LIST_ID of the PCI capability we're looking for.
167 * @return The next matching capability.
169 unsigned pci_find_capability(device_t dev, unsigned cap)
171 return pci_find_next_capability(dev, cap, 0);
175 * Given a device and register, read the size of the BAR for that register.
177 * @param dev Pointer to the device structure.
178 * @param index Address of the PCI configuration register.
181 struct resource *pci_get_resource(struct device *dev, unsigned long index)
183 struct resource *resource;
184 unsigned long value, attr;
185 resource_t moving, limit;
187 /* Initialize the resources to nothing. */
188 resource = new_resource(dev, index);
190 /* Get the initial value. */
191 value = pci_read_config32(dev, index);
193 /* See which bits move. */
194 moving = pci_moving_config32(dev, index);
196 /* Initialize attr to the bits that do not move. */
197 attr = value & ~moving;
199 /* If it is a 64bit resource look at the high half as well. */
200 if (((attr & PCI_BASE_ADDRESS_SPACE_IO) == 0) &&
201 ((attr & PCI_BASE_ADDRESS_MEM_LIMIT_MASK) ==
202 PCI_BASE_ADDRESS_MEM_LIMIT_64)) {
203 /* Find the high bits that move. */
205 ((resource_t) pci_moving_config32(dev, index + 4)) << 32;
208 /* Find the resource constraints.
209 * Start by finding the bits that move. From there:
210 * - Size is the least significant bit of the bits that move.
211 * - Limit is all of the bits that move plus all of the lower bits.
212 * See PCI Spec 6.2.5.1.
217 resource->align = resource->gran = 0;
218 while (!(moving & resource->size)) {
219 resource->size <<= 1;
220 resource->align += 1;
223 resource->limit = limit = moving | (resource->size - 1);
227 * Some broken hardware has read-only registers that do not
228 * really size correctly.
230 * Example: the Acer M7229 has BARs 1-4 normally read-only,
231 * so BAR1 at offset 0x10 reads 0x1f1. If you size that register
232 * by writing 0xffffffff to it, it will read back as 0x1f1 -- which
233 * is a violation of the spec.
235 * We catch this case and ignore it by observing which bits move.
237 * This also catches the common case of unimplemented registers
238 * that always read back as 0.
242 printk(BIOS_DEBUG, "%s register %02lx(%08lx), "
243 "read-only ignoring it\n",
244 dev_path(dev), index, value);
247 } else if (attr & PCI_BASE_ADDRESS_SPACE_IO) {
248 /* An I/O mapped base address. */
249 attr &= PCI_BASE_ADDRESS_IO_ATTR_MASK;
250 resource->flags |= IORESOURCE_IO;
251 /* I don't want to deal with 32bit I/O resources. */
252 resource->limit = 0xffff;
254 /* A Memory mapped base address. */
255 attr &= PCI_BASE_ADDRESS_MEM_ATTR_MASK;
256 resource->flags |= IORESOURCE_MEM;
257 if (attr & PCI_BASE_ADDRESS_MEM_PREFETCH)
258 resource->flags |= IORESOURCE_PREFETCH;
259 attr &= PCI_BASE_ADDRESS_MEM_LIMIT_MASK;
260 if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_32) {
262 resource->limit = 0xffffffffUL;
263 } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_1M) {
265 resource->limit = 0x000fffffUL;
266 } else if (attr == PCI_BASE_ADDRESS_MEM_LIMIT_64) {
268 resource->limit = 0xffffffffffffffffULL;
269 resource->flags |= IORESOURCE_PCI64;
272 printk(BIOS_ERR, "Broken BAR with value %lx\n", attr);
273 printk(BIOS_ERR, " on dev %s at index %02lx\n",
274 dev_path(dev), index);
279 /* Don't let the limit exceed which bits can move. */
280 if (resource->limit > limit)
281 resource->limit = limit;
287 * Given a device and an index, read the size of the BAR for that register.
289 * @param dev Pointer to the device structure.
290 * @param index Address of the PCI configuration register.
292 static void pci_get_rom_resource(struct device *dev, unsigned long index)
294 struct resource *resource;
298 /* Initialize the resources to nothing. */
299 resource = new_resource(dev, index);
301 /* Get the initial value. */
302 value = pci_read_config32(dev, index);
304 /* See which bits move. */
305 moving = pci_moving_config32(dev, index);
307 /* Clear the Enable bit. */
308 moving = moving & ~PCI_ROM_ADDRESS_ENABLE;
310 /* Find the resource constraints.
311 * Start by finding the bits that move. From there:
312 * - Size is the least significant bit of the bits that move.
313 * - Limit is all of the bits that move plus all of the lower bits.
314 * See PCI Spec 6.2.5.1.
318 resource->align = resource->gran = 0;
319 while (!(moving & resource->size)) {
320 resource->size <<= 1;
321 resource->align += 1;
324 resource->limit = moving | (resource->size - 1);
325 resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY;
328 printk(BIOS_DEBUG, "%s register %02lx(%08lx), "
329 "read-only ignoring it\n",
330 dev_path(dev), index, value);
334 compact_resources(dev);
338 * Read the base address registers for a given device.
340 * @param dev Pointer to the dev structure.
341 * @param howmany How many registers to read (6 for device, 2 for bridge).
343 static void pci_read_bases(struct device *dev, unsigned int howmany)
347 for (index = PCI_BASE_ADDRESS_0;
348 (index < PCI_BASE_ADDRESS_0 + (howmany << 2));) {
349 struct resource *resource;
350 resource = pci_get_resource(dev, index);
351 index += (resource->flags & IORESOURCE_PCI64) ? 8 : 4;
354 compact_resources(dev);
357 static void pci_record_bridge_resource(struct device *dev, resource_t moving,
358 unsigned index, unsigned long type)
360 struct resource *resource;
369 /* Initialize the constraints on the current bus. */
370 resource = new_resource(dev, index);
374 while ((moving & step) == 0) {
378 resource->gran = gran;
379 resource->align = gran;
380 resource->limit = moving | (step - 1);
381 resource->flags = type | IORESOURCE_PCI_BRIDGE |
385 static void pci_bridge_read_bases(struct device *dev)
387 resource_t moving_base, moving_limit, moving;
389 /* See if the bridge I/O resources are implemented. */
390 moving_base = ((u32) pci_moving_config8(dev, PCI_IO_BASE)) << 8;
392 ((u32) pci_moving_config16(dev, PCI_IO_BASE_UPPER16)) << 16;
394 moving_limit = ((u32) pci_moving_config8(dev, PCI_IO_LIMIT)) << 8;
396 ((u32) pci_moving_config16(dev, PCI_IO_LIMIT_UPPER16)) << 16;
398 moving = moving_base & moving_limit;
400 /* Initialize the I/O space constraints on the current bus. */
401 pci_record_bridge_resource(dev, moving, PCI_IO_BASE, IORESOURCE_IO);
403 /* See if the bridge prefmem resources are implemented. */
405 ((resource_t) pci_moving_config16(dev, PCI_PREF_MEMORY_BASE)) << 16;
407 ((resource_t) pci_moving_config32(dev, PCI_PREF_BASE_UPPER32)) << 32;
410 ((resource_t) pci_moving_config16(dev, PCI_PREF_MEMORY_LIMIT)) << 16;
412 ((resource_t) pci_moving_config32(dev, PCI_PREF_LIMIT_UPPER32)) << 32;
414 moving = moving_base & moving_limit;
415 /* Initialize the prefetchable memory constraints on the current bus. */
416 pci_record_bridge_resource(dev, moving, PCI_PREF_MEMORY_BASE,
417 IORESOURCE_MEM | IORESOURCE_PREFETCH);
419 /* See if the bridge mem resources are implemented. */
420 moving_base = ((u32) pci_moving_config16(dev, PCI_MEMORY_BASE)) << 16;
421 moving_limit = ((u32) pci_moving_config16(dev, PCI_MEMORY_LIMIT)) << 16;
423 moving = moving_base & moving_limit;
425 /* Initialize the memory resources on the current bus. */
426 pci_record_bridge_resource(dev, moving, PCI_MEMORY_BASE,
429 compact_resources(dev);
432 void pci_dev_read_resources(struct device *dev)
434 pci_read_bases(dev, 6);
435 pci_get_rom_resource(dev, PCI_ROM_ADDRESS);
438 void pci_bus_read_resources(struct device *dev)
440 pci_bridge_read_bases(dev);
441 pci_read_bases(dev, 2);
442 pci_get_rom_resource(dev, PCI_ROM_ADDRESS1);
445 void pci_domain_read_resources(struct device *dev)
447 struct resource *res;
449 /* Initialize the system-wide I/O space constraints. */
450 res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
451 res->limit = 0xffffUL;
452 res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
455 /* Initialize the system-wide memory resources constraints. */
456 res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
457 res->limit = 0xffffffffULL;
458 res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
462 static void pci_set_resource(struct device *dev, struct resource *resource)
464 resource_t base, end;
466 /* Make certain the resource has actually been assigned a value. */
467 if (!(resource->flags & IORESOURCE_ASSIGNED)) {
468 printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010llx not "
469 "assigned\n", dev_path(dev), resource->index,
470 resource_type(resource), resource->size);
474 /* If this resource is fixed don't worry about it. */
475 if (resource->flags & IORESOURCE_FIXED)
478 /* If I have already stored this resource don't worry about it. */
479 if (resource->flags & IORESOURCE_STORED)
482 /* If the resource is subtractive don't worry about it. */
483 if (resource->flags & IORESOURCE_SUBTRACTIVE)
486 /* Only handle PCI memory and I/O resources for now. */
487 if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
490 /* Enable the resources in the command register. */
491 if (resource->size) {
492 if (resource->flags & IORESOURCE_MEM)
493 dev->command |= PCI_COMMAND_MEMORY;
494 if (resource->flags & IORESOURCE_IO)
495 dev->command |= PCI_COMMAND_IO;
496 if (resource->flags & IORESOURCE_PCI_BRIDGE)
497 dev->command |= PCI_COMMAND_MASTER;
500 /* Get the base address. */
501 base = resource->base;
504 end = resource_end(resource);
506 /* Now store the resource. */
507 resource->flags |= IORESOURCE_STORED;
510 * PCI bridges have no enable bit. They are disabled if the base of
511 * the range is greater than the limit. If the size is zero, disable
512 * by setting the base = limit and end = limit - 2^gran.
514 if (resource->size == 0 && (resource->flags & IORESOURCE_PCI_BRIDGE)) {
515 base = resource->limit;
516 end = resource->limit - (1 << resource->gran);
517 resource->base = base;
520 if (!(resource->flags & IORESOURCE_PCI_BRIDGE)) {
521 unsigned long base_lo, base_hi;
524 * Some chipsets allow us to set/clear the I/O bit
525 * (e.g. VIA 82C686A). So set it to be safe.
527 base_lo = base & 0xffffffff;
528 base_hi = (base >> 32) & 0xffffffff;
529 if (resource->flags & IORESOURCE_IO)
530 base_lo |= PCI_BASE_ADDRESS_SPACE_IO;
531 pci_write_config32(dev, resource->index, base_lo);
532 if (resource->flags & IORESOURCE_PCI64)
533 pci_write_config32(dev, resource->index + 4, base_hi);
534 } else if (resource->index == PCI_IO_BASE) {
535 /* Set the I/O ranges. */
536 pci_write_config8(dev, PCI_IO_BASE, base >> 8);
537 pci_write_config16(dev, PCI_IO_BASE_UPPER16, base >> 16);
538 pci_write_config8(dev, PCI_IO_LIMIT, end >> 8);
539 pci_write_config16(dev, PCI_IO_LIMIT_UPPER16, end >> 16);
540 } else if (resource->index == PCI_MEMORY_BASE) {
541 /* Set the memory range. */
542 pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);
543 pci_write_config16(dev, PCI_MEMORY_LIMIT, end >> 16);
544 } else if (resource->index == PCI_PREF_MEMORY_BASE) {
545 /* Set the prefetchable memory range. */
546 pci_write_config16(dev, PCI_PREF_MEMORY_BASE, base >> 16);
547 pci_write_config32(dev, PCI_PREF_BASE_UPPER32, base >> 32);
548 pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, end >> 16);
549 pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, end >> 32);
551 /* Don't let me think I stored the resource. */
552 resource->flags &= ~IORESOURCE_STORED;
553 printk(BIOS_ERR, "ERROR: invalid resource->index %lx\n",
557 report_resource_stored(dev, resource, "");
560 void pci_dev_set_resources(struct device *dev)
562 struct resource *res;
566 for (res = dev->resource_list; res; res = res->next)
567 pci_set_resource(dev, res);
569 for (bus = dev->link_list; bus; bus = bus->next) {
571 assign_resources(bus);
574 /* Set a default latency timer. */
575 pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
577 /* Set a default secondary latency timer. */
578 if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE)
579 pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
581 /* Zero the IRQ settings. */
582 line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
584 pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
586 /* Set the cache line size, so far 64 bytes is good for everyone. */
587 pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
590 void pci_dev_enable_resources(struct device *dev)
592 const struct pci_operations *ops;
595 /* Set the subsystem vendor and device ID for mainboard devices. */
597 if (dev->on_mainboard && ops && ops->set_subsystem) {
598 printk(BIOS_DEBUG, "%s subsystem <- %02x/%02x\n", dev_path(dev),
599 CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
600 CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
601 ops->set_subsystem(dev,
602 CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
603 CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
605 command = pci_read_config16(dev, PCI_COMMAND);
606 command |= dev->command;
609 * command |= (PCI_COMMAND_PARITY + PCI_COMMAND_SERR); // Error check.
612 printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command);
613 pci_write_config16(dev, PCI_COMMAND, command);
616 void pci_bus_enable_resources(struct device *dev)
621 * Enable I/O in command register if there is VGA card
622 * connected with (even it does not claim I/O resource).
624 if (dev->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA)
625 dev->command |= PCI_COMMAND_IO;
626 ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
627 ctrl |= dev->link_list->bridge_ctrl;
628 ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* Error check. */
629 printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
630 pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
632 pci_dev_enable_resources(dev);
635 void pci_bus_reset(struct bus *bus)
639 ctl = pci_read_config16(bus->dev, PCI_BRIDGE_CONTROL);
640 ctl |= PCI_BRIDGE_CTL_BUS_RESET;
641 pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, ctl);
644 ctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
645 pci_write_config16(bus->dev, PCI_BRIDGE_CONTROL, ctl);
649 void pci_dev_set_subsystem(struct device *dev, unsigned vendor, unsigned device)
651 pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
652 ((device & 0xffff) << 16) | (vendor & 0xffff));
655 /** Default handler: only runs the relevant PCI BIOS. */
656 void pci_dev_init(struct device *dev)
658 #if CONFIG_PCI_ROM_RUN == 1 || CONFIG_VGA_ROM_RUN == 1
659 struct rom_header *rom, *ram;
661 if (CONFIG_PCI_ROM_RUN != 1 && /* Only execute VGA ROMs. */
662 ((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA))
665 if (CONFIG_VGA_ROM_RUN != 1 && /* Only execute non-VGA ROMs. */
666 ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA))
669 rom = pci_rom_probe(dev);
673 ram = pci_rom_load(dev, rom);
677 run_bios(dev, (unsigned long)ram);
679 #if CONFIG_CONSOLE_VGA == 1
680 if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA)
682 #endif /* CONFIG_CONSOLE_VGA */
683 #endif /* CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN */
686 /** Default device operation for PCI devices */
687 static struct pci_operations pci_dev_ops_pci = {
688 .set_subsystem = pci_dev_set_subsystem,
691 struct device_operations default_pci_ops_dev = {
692 .read_resources = pci_dev_read_resources,
693 .set_resources = pci_dev_set_resources,
694 .enable_resources = pci_dev_enable_resources,
695 .init = pci_dev_init,
698 .ops_pci = &pci_dev_ops_pci,
701 /** Default device operations for PCI bridges */
702 static struct pci_operations pci_bus_ops_pci = {
706 struct device_operations default_pci_ops_bus = {
707 .read_resources = pci_bus_read_resources,
708 .set_resources = pci_dev_set_resources,
709 .enable_resources = pci_bus_enable_resources,
711 .scan_bus = pci_scan_bridge,
713 .reset_bus = pci_bus_reset,
714 .ops_pci = &pci_bus_ops_pci,
718 * Detect the type of downstream bridge.
720 * This function is a heuristic to detect which type of bus is downstream
721 * of a PCI-to-PCI bridge. This functions by looking for various capability
722 * blocks to figure out the type of downstream bridge. PCI-X, PCI-E, and
723 * Hypertransport all seem to have appropriate capabilities.
725 * When only a PCI-Express capability is found the type is examined to see
726 * which type of bridge we have.
728 * @param dev Pointer to the device structure of the bridge.
729 * @return Appropriate bridge operations.
731 static struct device_operations *get_pci_bridge_ops(device_t dev)
735 #if CONFIG_PCIX_PLUGIN_SUPPORT == 1
736 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
738 printk(BIOS_DEBUG, "%s subordinate bus PCI-X\n", dev_path(dev));
739 return &default_pcix_ops_bus;
742 #if CONFIG_AGP_PLUGIN_SUPPORT == 1
743 /* How do I detect a PCI to AGP bridge? */
745 #if CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT == 1
747 while ((pos = pci_find_next_capability(dev, PCI_CAP_ID_HT, pos))) {
749 flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
750 if ((flags >> 13) == 1) {
751 /* Host or Secondary Interface */
752 printk(BIOS_DEBUG, "%s subordinate bus HT\n",
754 return &default_ht_ops_bus;
758 #if CONFIG_PCIEXP_PLUGIN_SUPPORT == 1
759 pos = pci_find_capability(dev, PCI_CAP_ID_PCIE);
762 flags = pci_read_config16(dev, pos + PCI_EXP_FLAGS);
763 switch ((flags & PCI_EXP_FLAGS_TYPE) >> 4) {
764 case PCI_EXP_TYPE_ROOT_PORT:
765 case PCI_EXP_TYPE_UPSTREAM:
766 case PCI_EXP_TYPE_DOWNSTREAM:
767 printk(BIOS_DEBUG, "%s subordinate bus PCI Express\n",
769 return &default_pciexp_ops_bus;
770 case PCI_EXP_TYPE_PCI_BRIDGE:
771 printk(BIOS_DEBUG, "%s subordinate PCI\n",
773 return &default_pci_ops_bus;
779 return &default_pci_ops_bus;
783 * Set up PCI device operation.
785 * Check if it already has a driver. If not, use find_device_operations(),
786 * or set to a default based on type.
788 * @param dev Pointer to the device whose pci_ops you want to set.
791 static void set_pci_ops(struct device *dev)
793 struct pci_driver *driver;
799 * Look through the list of setup drivers and find one for
802 for (driver = &pci_drivers[0]; driver != &epci_drivers[0]; driver++) {
803 if ((driver->vendor == dev->vendor) &&
804 (driver->device == dev->device)) {
805 dev->ops = (struct device_operations *)driver->ops;
806 printk(BIOS_SPEW, "%s [%04x/%04x] %sops\n",
807 dev_path(dev), driver->vendor, driver->device,
808 (driver->ops->scan_bus ? "bus " : ""));
813 /* If I don't have a specific driver use the default operations. */
814 switch (dev->hdr_type & 0x7f) { /* Header type */
815 case PCI_HEADER_TYPE_NORMAL:
816 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)
818 dev->ops = &default_pci_ops_dev;
820 case PCI_HEADER_TYPE_BRIDGE:
821 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
823 dev->ops = get_pci_bridge_ops(dev);
825 #if CONFIG_CARDBUS_PLUGIN_SUPPORT == 1
826 case PCI_HEADER_TYPE_CARDBUS:
827 dev->ops = &default_cardbus_ops_bus;
833 printk(BIOS_ERR, "%s [%04x/%04x/%06x] has unknown "
834 "header type %02x, ignoring.\n", dev_path(dev),
835 dev->vendor, dev->device,
836 dev->class >> 8, dev->hdr_type);
842 * See if we have already allocated a device structure for a given devfn.
844 * Given a linked list of PCI device structures and a devfn number, find the
845 * device structure correspond to the devfn, if present. This function also
846 * removes the device structure from the linked list.
848 * @param list The device structure list.
849 * @param devfn A device/function number.
850 * @return Pointer to the device structure found or NULL if we have not
851 * allocated a device for this devfn yet.
853 static struct device *pci_scan_get_dev(struct device **list, unsigned int devfn)
858 for (; *list; list = &(*list)->sibling) {
859 if ((*list)->path.type != DEVICE_PATH_PCI) {
860 printk(BIOS_ERR, "child %s not a PCI device\n",
864 if ((*list)->path.pci.devfn == devfn) {
865 /* Unlink from the list. */
867 *list = (*list)->sibling;
874 * Just like alloc_dev() add the device to the list of devices on the
875 * bus. When the list of devices was formed we removed all of the
876 * parents children, and now we are interleaving static and dynamic
877 * devices in order on the bus.
880 struct device *child;
882 /* Find the last child of our parent. */
883 for (child = dev->bus->children; child && child->sibling;)
884 child = child->sibling;
886 /* Place the device on the list of children of its parent. */
888 child->sibling = dev;
890 dev->bus->children = dev;
899 * Determine the existence of a given PCI device. Allocate a new struct device
900 * if dev==NULL was passed in and the device exists in hardware.
902 * @param dev Pointer to the dev structure.
903 * @param bus Pointer to the bus structure.
904 * @param devfn A device/function number to look at.
905 * @return The device structure for the device (if found), NULL otherwise.
907 device_t pci_probe_dev(device_t dev, struct bus *bus, unsigned devfn)
912 /* Detect if a device is present. */
917 dummy.path.type = DEVICE_PATH_PCI;
918 dummy.path.pci.devfn = devfn;
920 id = pci_read_config32(&dummy, PCI_VENDOR_ID);
922 * Have we found something? Some broken boards return 0 if a
923 * slot is empty, but the expected answer is 0xffffffff.
925 if (id == 0xffffffff)
928 if ((id == 0x00000000) || (id == 0x0000ffff) ||
929 (id == 0xffff0000)) {
930 printk(BIOS_SPEW, "%s, bad id 0x%x\n",
931 dev_path(&dummy), id);
934 dev = alloc_dev(bus, &dummy.path);
937 * Enable/disable the device. Once we have found the device-
938 * specific operations this operations we will disable the
939 * device with those as well.
941 * This is geared toward devices that have subfunctions
942 * that do not show up by default.
944 * If a device is a stuff option on the motherboard
945 * it may be absent and enable_dev() must cope.
947 /* Run the magic enable sequence for the device. */
948 if (dev->chip_ops && dev->chip_ops->enable_dev)
949 dev->chip_ops->enable_dev(dev);
951 /* Now read the vendor and device ID. */
952 id = pci_read_config32(dev, PCI_VENDOR_ID);
955 * If the device does not have a PCI ID disable it. Possibly
956 * this is because we have already disabled the device. But
957 * this also handles optional devices that may not always
960 /* If the chain is fully enumerated quit */
961 if ((id == 0xffffffff) || (id == 0x00000000) ||
962 (id == 0x0000ffff) || (id == 0xffff0000)) {
964 printk(BIOS_INFO, "PCI: Static device %s not "
965 "found, disabling it.\n", dev_path(dev));
972 /* Read the rest of the PCI configuration information. */
973 hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
974 class = pci_read_config32(dev, PCI_CLASS_REVISION);
976 /* Store the interesting information in the device structure. */
977 dev->vendor = id & 0xffff;
978 dev->device = (id >> 16) & 0xffff;
979 dev->hdr_type = hdr_type;
981 /* Class code, the upper 3 bytes of PCI_CLASS_REVISION. */
982 dev->class = class >> 8;
984 /* Architectural/System devices always need to be bus masters. */
985 if ((dev->class >> 16) == PCI_BASE_CLASS_SYSTEM)
986 dev->command |= PCI_COMMAND_MASTER;
989 * Look at the vendor and device ID, or at least the header type and
990 * class and figure out which set of configuration methods to use.
991 * Unless we already have some PCI ops.
995 /* Now run the magic enable/disable sequence for the device. */
996 if (dev->ops && dev->ops->enable)
997 dev->ops->enable(dev);
999 /* Display the device. */
1000 printk(BIOS_DEBUG, "%s [%04x/%04x] %s%s\n", dev_path(dev),
1001 dev->vendor, dev->device, dev->enabled ? "enabled" : "disabled",
1002 dev->ops ? "" : " No operations");
1010 * Determine the existence of devices and bridges on a PCI bus. If there are
1011 * bridges on the bus, recursively scan the buses behind the bridges.
1013 * This function is the default scan_bus() method for the root device
1016 * @param bus Pointer to the bus structure.
1017 * @param min_devfn Minimum devfn to look at in the scan, usually 0x00.
1018 * @param max_devfn Maximum devfn to look at in the scan, usually 0xff.
1019 * @param max Current bus number.
1020 * @return The maximum bus number found, after scanning all subordinate busses.
1022 unsigned int pci_scan_bus(struct bus *bus, unsigned min_devfn,
1023 unsigned max_devfn, unsigned int max)
1026 struct device *old_devices;
1027 struct device *child;
1029 #if CONFIG_PCI_BUS_SEGN_BITS
1030 printk(BIOS_DEBUG, "PCI: pci_scan_bus for bus %04x:%02x\n",
1031 bus->secondary >> 8, bus->secondary & 0xff);
1033 printk(BIOS_DEBUG, "PCI: pci_scan_bus for bus %02x\n", bus->secondary);
1036 /* Maximum sane devfn is 0xFF. */
1037 if (max_devfn > 0xff) {
1038 printk(BIOS_ERR, "PCI: pci_scan_bus limits devfn %x - "
1039 "devfn %x\n", min_devfn, max_devfn);
1040 printk(BIOS_ERR, "PCI: pci_scan_bus upper limit too big. "
1045 old_devices = bus->children;
1046 bus->children = NULL;
1051 * Probe all devices/functions on this bus with some optimization for
1052 * non-existence and single function devices.
1054 for (devfn = min_devfn; devfn <= max_devfn; devfn++) {
1057 /* First thing setup the device structure. */
1058 dev = pci_scan_get_dev(&old_devices, devfn);
1060 /* See if a device is present and setup the device structure. */
1061 dev = pci_probe_dev(dev, bus, devfn);
1064 * If this is not a multi function device, or the device is
1065 * not present don't waste time probing another function.
1066 * Skip to next device.
1068 if ((PCI_FUNC(devfn) == 0x00) && (!dev
1069 || (dev->enabled && ((dev->hdr_type & 0x80) != 0x80)))) {
1077 * Warn if any leftover static devices are are found.
1078 * There's probably a problem in devicetree.cb.
1082 printk(BIOS_WARNING, "PCI: Left over static devices:\n");
1083 for (left = old_devices; left; left = left->sibling)
1084 printk(BIOS_WARNING, "%s\n", dev_path(left));
1086 printk(BIOS_WARNING, "PCI: Check your devicetree.cb.\n");
1090 * For all children that implement scan_bus() (i.e. bridges)
1091 * scan the bus behind that child.
1093 for (child = bus->children; child; child = child->sibling)
1094 max = scan_bus(child, max);
1097 * We've scanned the bus and so we know all about what's on the other
1098 * side of any bridges that may be on this bus plus any devices.
1099 * Return how far we've got finding sub-buses.
1101 printk(BIOS_DEBUG, "PCI: pci_scan_bus returning with max=%03x\n", max);
1107 * Scan a PCI bridge and the buses behind the bridge.
1109 * Determine the existence of buses behind the bridge. Set up the bridge
1110 * according to the result of the scan.
1112 * This function is the default scan_bus() method for PCI bridge devices.
1114 * @param dev Pointer to the bridge device.
1115 * @param max The highest bus number assigned up to now.
1116 * @param do_scan_bus TODO
1117 * @return The maximum bus number found, after scanning all subordinate buses.
1119 unsigned int do_pci_scan_bridge(struct device *dev, unsigned int max,
1120 unsigned int (*do_scan_bus) (struct bus * bus,
1129 printk(BIOS_SPEW, "%s for %s\n", __func__, dev_path(dev));
1131 if (dev->link_list == NULL) {
1133 link = malloc(sizeof(*link));
1135 die("Couldn't allocate a link!\n");
1136 memset(link, 0, sizeof(*link));
1138 dev->link_list = link;
1141 bus = dev->link_list;
1144 * Set up the primary, secondary and subordinate bus numbers. We have
1145 * no idea how many buses are behind this bridge yet, so we set the
1146 * subordinate bus number to 0xff for the moment.
1148 bus->secondary = ++max;
1149 bus->subordinate = 0xff;
1151 /* Clear all status bits and turn off memory, I/O and master enables. */
1152 cr = pci_read_config16(dev, PCI_COMMAND);
1153 pci_write_config16(dev, PCI_COMMAND, 0x0000);
1154 pci_write_config16(dev, PCI_STATUS, 0xffff);
1157 * Read the existing primary/secondary/subordinate bus
1158 * number configuration.
1160 buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
1163 * Configure the bus numbers for this bridge: the configuration
1164 * transactions will not be propagated by the bridge if it is not
1165 * correctly configured.
1167 buses &= 0xff000000;
1168 buses |= (((unsigned int)(dev->bus->secondary) << 0) |
1169 ((unsigned int)(bus->secondary) << 8) |
1170 ((unsigned int)(bus->subordinate) << 16));
1171 pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
1173 /* Now we can scan all subordinate buses (those behind the bridge). */
1174 max = do_scan_bus(bus, 0x00, 0xff, max);
1177 * We know the number of buses behind this bridge. Set the subordinate
1178 * bus number to its real value.
1180 bus->subordinate = max;
1181 buses = (buses & 0xff00ffff) | ((unsigned int)(bus->subordinate) << 16);
1182 pci_write_config32(dev, PCI_PRIMARY_BUS, buses);
1183 pci_write_config16(dev, PCI_COMMAND, cr);
1185 printk(BIOS_SPEW, "%s returns max %d\n", __func__, max);
1190 * Scan a PCI bridge and the buses behind the bridge.
1192 * Determine the existence of buses behind the bridge. Set up the bridge
1193 * according to the result of the scan.
1195 * This function is the default scan_bus() method for PCI bridge devices.
1197 * @param dev Pointer to the bridge device.
1198 * @param max The highest bus number assigned up to now.
1199 * @return The maximum bus number found, after scanning all subordinate buses.
1201 unsigned int pci_scan_bridge(struct device *dev, unsigned int max)
1203 return do_pci_scan_bridge(dev, max, pci_scan_bus);
1207 * Scan a PCI domain.
1209 * This function is the default scan_bus() method for PCI domains.
1211 * @param dev Pointer to the domain.
1212 * @param max The highest bus number assigned up to now.
1213 * @return The maximum bus number found, after scanning all subordinate busses.
1215 unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
1217 max = pci_scan_bus(dev->link_list, PCI_DEVFN(0, 0), 0xff, max);
1221 #if CONFIG_PC80_SYSTEM == 1
1223 * Assign IRQ numbers.
1225 * This function assigns IRQs for all functions contained within the indicated
1226 * device address. If the device does not exist or does not require interrupts
1227 * then this function has no effect.
1229 * This function should be called for each PCI slot in your system.
1231 * @param bus Pointer to the bus structure.
1233 * @param pIntAtoD An array of IRQ #s that are assigned to PINTA through PINTD
1234 * of this slot. The particular IRQ #s that are passed in depend on the
1235 * routing inside your southbridge and on your board.
1237 void pci_assign_irqs(unsigned bus, unsigned slot,
1238 const unsigned char pIntAtoD[4])
1244 /* Each slot may contain up to eight functions. */
1245 for (funct = 0; funct < 8; funct++) {
1246 pdev = dev_find_slot(bus, (slot << 3) + funct);
1251 line = pci_read_config8(pdev, PCI_INTERRUPT_PIN);
1253 /* PCI spec says all values except 1..4 are reserved. */
1254 if ((line < 1) || (line > 4))
1257 irq = pIntAtoD[line - 1];
1259 printk(BIOS_DEBUG, "Assigning IRQ %d to %d:%x.%d\n",
1260 irq, bus, slot, funct);
1262 pci_write_config8(pdev, PCI_INTERRUPT_LINE,
1263 pIntAtoD[line - 1]);
1265 #ifdef PARANOID_IRQ_ASSIGNMENTS
1266 irq = pci_read_config8(pdev, PCI_INTERRUPT_LINE);
1267 printk(BIOS_DEBUG, " Readback = %d\n", irq);
1270 /* Change to level triggered. */
1271 i8259_configure_irq_trigger(pIntAtoD[line - 1],
1272 IRQ_LEVEL_TRIGGERED);