2 #include <console/console.h>
3 #include <device/device.h>
4 #include <device/path.h>
5 #include <device/pci.h>
6 #include <device/pci_ids.h>
7 #include <device/hypertransport.h>
8 #include <device/chip.h>
9 #include <part/hard_reset.h>
10 #include <part/fallback_boot.h>
12 static device_t ht_scan_get_devs(device_t *old_devices)
17 while(last && last->sibling &&
18 (last->sibling->path.type == DEVICE_PATH_PCI) &&
19 (last->sibling->path.u.pci.devfn > last->path.u.pci.devfn)) {
23 *old_devices = last->sibling;
29 static unsigned ht_read_freq_cap(device_t dev, unsigned pos)
31 /* Handle bugs in valid hypertransport frequency reporting */
34 freq_cap = pci_read_config16(dev, pos);
35 freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */
37 /* AMD 8131 Errata 48 */
38 if ((dev->vendor == PCI_VENDOR_ID_AMD) &&
39 (dev->device == PCI_DEVICE_ID_AMD_8131_PCIX)) {
40 freq_cap &= ~(1 << HT_FREQ_800Mhz);
42 /* AMD 8151 Errata 23 */
43 if ((dev->vendor == PCI_VENDOR_ID_AMD) &&
44 (dev->device == PCI_DEVICE_ID_AMD_8151_SYSCTRL)) {
45 freq_cap &= ~(1 << HT_FREQ_800Mhz);
47 /* AMD K8 Unsupported 1Ghz? */
48 if ((dev->vendor == PCI_VENDOR_ID_AMD) && (dev->device == 0x1100)) {
49 freq_cap &= ~(1 << HT_FREQ_1000Mhz);
57 unsigned char config_off, freq_off, freq_cap_off;
60 static int ht_setup_link(struct prev_link *prev, device_t dev, unsigned pos)
62 static const uint8_t link_width_to_pow2[]= { 3, 4, 0, 5, 1, 2, 0, 0 };
63 static const uint8_t pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 };
64 unsigned present_width_cap, upstream_width_cap;
65 unsigned present_freq_cap, upstream_freq_cap;
66 unsigned ln_present_width_in, ln_upstream_width_in;
67 unsigned ln_present_width_out, ln_upstream_width_out;
68 unsigned freq, old_freq;
69 unsigned present_width, upstream_width, old_width;
72 /* Set the hypertransport link width and frequency */
75 /* Read the capabilities */
76 present_freq_cap = ht_read_freq_cap(dev, pos + PCI_HT_CAP_SLAVE_FREQ_CAP0);
77 upstream_freq_cap = ht_read_freq_cap(prev->dev, prev->pos + prev->freq_cap_off);
78 present_width_cap = pci_read_config8(dev, pos + PCI_HT_CAP_SLAVE_WIDTH0);
79 upstream_width_cap = pci_read_config8(prev->dev, prev->pos + prev->config_off);
81 /* Calculate the highest useable frequency */
82 freq = log2(present_freq_cap & upstream_freq_cap);
84 /* Calculate the highest width */
85 ln_upstream_width_in = link_width_to_pow2[upstream_width_cap & 7];
86 ln_present_width_out = link_width_to_pow2[(present_width_cap >> 4) & 7];
87 if (ln_upstream_width_in > ln_present_width_out) {
88 ln_upstream_width_in = ln_present_width_out;
90 upstream_width = pow2_to_link_width[ln_upstream_width_in];
91 present_width = pow2_to_link_width[ln_upstream_width_in] << 4;
93 ln_upstream_width_out = link_width_to_pow2[(upstream_width_cap >> 4) & 7];
94 ln_present_width_in = link_width_to_pow2[present_width_cap & 7];
95 if (ln_upstream_width_out > ln_present_width_in) {
96 ln_upstream_width_out = ln_present_width_in;
98 upstream_width |= pow2_to_link_width[ln_upstream_width_out] << 4;
99 present_width |= pow2_to_link_width[ln_upstream_width_out];
101 /* Set the current device */
102 old_freq = pci_read_config8(dev, pos + PCI_HT_CAP_SLAVE_FREQ0);
103 if (freq != old_freq) {
104 pci_write_config8(dev, pos + PCI_HT_CAP_SLAVE_FREQ0, freq);
106 printk_spew("HyperT FreqP old %x new %x\n",old_freq,freq);
108 old_width = pci_read_config8(dev, pos + PCI_HT_CAP_SLAVE_WIDTH0 + 1);
109 if (present_width != old_width) {
110 pci_write_config8(dev, pos + PCI_HT_CAP_SLAVE_WIDTH0 + 1, present_width);
112 printk_spew("HyperT widthP old %x new %x\n",old_width, present_width);
115 /* Set the upstream device */
116 old_freq = pci_read_config8(prev->dev, prev->pos + prev->freq_off);
118 if (freq != old_freq) {
119 pci_write_config8(prev->dev, prev->pos + prev->freq_off, freq);
121 printk_spew("HyperT freqU old %x new %x\n", old_freq, freq);
123 old_width = pci_read_config8(prev->dev, prev->pos + prev->config_off + 1);
124 if (upstream_width != old_width) {
125 pci_write_config8(prev->dev, prev->pos + prev->config_off + 1, upstream_width);
127 printk_spew("HyperT widthU old %x new %x\n", old_width, upstream_width);
130 /* Remember the current link as the previous link */
133 prev->config_off = PCI_HT_CAP_SLAVE_WIDTH1;
134 prev->freq_off = PCI_HT_CAP_SLAVE_FREQ1;
135 prev->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP1;
141 static unsigned ht_lookup_slave_capability(struct device *dev)
145 switch(dev->hdr_type & 0x7f) {
146 case PCI_HEADER_TYPE_NORMAL:
147 case PCI_HEADER_TYPE_BRIDGE:
148 pos = PCI_CAPABILITY_LIST;
151 if (pos > PCI_CAP_LIST_NEXT) {
152 pos = pci_read_config8(dev, pos);
154 while(pos != 0) { /* loop through the linked list */
156 cap = pci_read_config8(dev, pos + PCI_CAP_LIST_ID);
157 printk_spew("Capability: 0x%02x @ 0x%02x\n", cap, pos);
158 if (cap == PCI_CAP_ID_HT) {
160 flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
161 printk_spew("flags: 0x%04x\n", (unsigned)flags);
162 if ((flags >> 13) == 0) {
163 /* Entry is a Slave secondary, success...*/
167 pos = pci_read_config8(dev, pos + PCI_CAP_LIST_NEXT);
172 static void ht_collapse_early_enumeration(struct bus *bus)
176 /* Spin through the devices and collapse any early
177 * hypertransport enumeration.
179 for(devfn = 0; devfn <= 0xff; devfn += 8) {
184 dummy.path.type = DEVICE_PATH_PCI;
185 dummy.path.u.pci.devfn = devfn;
186 id = pci_read_config32(&dummy, PCI_VENDOR_ID);
187 if (id == 0xffffffff || id == 0x00000000 ||
188 id == 0x0000ffff || id == 0xffff0000) {
191 dummy.vendor = id & 0xffff;
192 dummy.device = (id >> 16) & 0xffff;
193 dummy.hdr_type = pci_read_config8(&dummy, PCI_HEADER_TYPE);
194 pos = ht_lookup_slave_capability(&dummy);
199 /* Clear the unitid */
200 flags = pci_read_config16(&dummy, pos + PCI_CAP_FLAGS);
202 pci_write_config16(&dummy, pos + PCI_CAP_FLAGS, flags);
203 printk_spew("Collapsing %s [%04x/%04x]\n",
204 dev_path(&dummy), dummy.vendor, dummy.device);
208 unsigned int hypertransport_scan_chain(struct bus *bus, unsigned int max)
210 unsigned next_unitid, last_unitid, previous_unitid;
211 uint8_t previous_pos;
212 device_t old_devices, dev, func, *chain_last;
213 unsigned min_unitid = 1;
215 struct prev_link prev;
217 /* Restore the hypertransport chain to it's unitialized state */
218 ht_collapse_early_enumeration(bus);
220 /* See which static device nodes I have */
221 old_devices = bus->children;
223 chain_last = &bus->children;
225 /* Initialize the hypertransport enumeration state */
229 prev.config_off = PCI_HT_CAP_HOST_WIDTH;
230 prev.freq_off = PCI_HT_CAP_HOST_FREQ;
231 prev.freq_cap_off = PCI_HT_CAP_HOST_FREQ_CAP;
233 /* If present assign unitid to a hypertransport chain */
234 last_unitid = min_unitid -1;
235 next_unitid = min_unitid;
239 uint8_t hdr_type, pos;
241 unsigned count, static_count;
243 previous_unitid = last_unitid;
244 last_unitid = next_unitid;
246 /* Get setup the device_structure */
247 dev = ht_scan_get_devs(&old_devices);
252 dummy.path.type = DEVICE_PATH_PCI;
253 dummy.path.u.pci.devfn = 0;
254 id = pci_read_config32(&dummy, PCI_VENDOR_ID);
255 /* If the chain is fully enumerated quit */
256 if (id == 0xffffffff || id == 0x00000000 ||
257 id == 0x0000ffff || id == 0xffff0000) {
260 dev = alloc_dev(bus, &dummy.path);
263 /* Add this device to the pci bus chain */
265 /* Run the magice enable sequence for the device */
266 if (dev->chip && dev->chip->control && dev->chip->control->enable_dev) {
267 int enable = dev->enable;
269 dev->chip->control->enable_dev(dev);
270 dev->enable = enable;
272 /* Now read the vendor and device id */
273 id = pci_read_config32(dev, PCI_VENDOR_ID);
275 /* If the chain is fully enumerated quit */
276 if (id == 0xffffffff || id == 0x00000000 ||
277 id == 0x0000ffff || id == 0xffff0000) {
278 printk_err("Missing static device: %s\n",
283 /* Update the device chain tail */
284 for(func = dev; func; func = func->sibling) {
285 chain_last = &func->sibling;
288 /* Read the rest of the pci configuration information */
289 hdr_type = pci_read_config8(dev, PCI_HEADER_TYPE);
290 class = pci_read_config32(dev, PCI_CLASS_REVISION);
292 /* Store the interesting information in the device structure */
293 dev->vendor = id & 0xffff;
294 dev->device = (id >> 16) & 0xffff;
295 dev->hdr_type = hdr_type;
296 /* class code, the upper 3 bytes of PCI_CLASS_REVISION */
297 dev->class = class >> 8;
299 /* Find the hypertransport link capability */
300 pos = ht_lookup_slave_capability(dev);
302 printk_err("%s Hypertransport link capability not found",
307 /* Update the Unitid of the current device */
308 flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
309 flags &= ~0x1f; /* mask out base Unit ID */
310 flags |= next_unitid & 0x1f;
311 pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags);
313 /* Update the Unitd id in the device structure */
315 for(func = dev; func; func = func->sibling) {
316 func->path.u.pci.devfn += (next_unitid << 3);
317 static_count = (func->path.u.pci.devfn >> 3)
318 - (dev->path.u.pci.devfn >> 3) + 1;
321 /* Compute the number of unitids consumed */
322 count = (flags >> 5) & 0x1f; /* get unit count */
323 printk_spew("%s count: %04x static_count: %04x\n",
324 dev_path(dev), count, static_count);
325 if (count < static_count) {
326 count = static_count;
329 /* Update the Unitid of the next device */
330 next_unitid += count;
332 /* Setup the hypetransport link */
333 reset_needed |= ht_setup_link(&prev, dev, pos);
335 printk_debug("%s [%04x/%04x] %s next_unitid: %04x\n",
337 dev->vendor, dev->device,
338 (dev->enable? "enabled": "disabled"), next_unitid);
340 } while((last_unitid != next_unitid) && (next_unitid <= 0x1f));
341 #if HAVE_HARD_RESET == 1
343 printk_info("HyperT reset needed\n");
347 printk_debug("HyperT reset not needed\n");
350 if (next_unitid > 0x1f) {
353 return pci_scan_bus(bus, 0x00, (next_unitid << 3)|7, max);