2 * This file is part of the coreboot project.
4 * Copyright (C) 2003-2004 Linux Networx
5 * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
6 * Copyright (C) 2004 David Hendricks <sc@flagen.com>
7 * Copyright (C) 2004 Li-Ta Lo <ollie@lanl.gov>
8 * Copyright (C) 2005-2006 Tyan
9 * (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
10 * Copyright (C) 2005-2006 Stefan Reinauer <stepan@openbios.org>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; version 2 of the License.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
27 #include <console/console.h>
28 #include <device/device.h>
29 #include <device/path.h>
30 #include <device/pci.h>
31 #include <device/pci_ids.h>
32 #include <device/hypertransport.h>
35 * The hypertransport link is already optimized in pre-RAM code so don't do
41 #include <cpu/amd/model_fxx_rev.h>
44 static device_t ht_scan_get_devs(device_t *old_devices)
49 /* Extract the chain of devices to (first through last)
50 * for the next hypertransport device.
52 while(last && last->sibling &&
53 (last->sibling->path.type == DEVICE_PATH_PCI) &&
54 (last->sibling->path.pci.devfn > last->path.pci.devfn))
60 /* Unlink the chain from the list of old devices */
61 *old_devices = last->sibling;
64 /* Now add the device to the list of devices on the bus.
66 /* Find the last child of our parent */
67 for(child = first->bus->children; child && child->sibling; ) {
68 child = child->sibling;
70 /* Place the chain on the list of children of their parent. */
72 child->sibling = first;
74 first->bus->children = first;
81 static unsigned ht_read_freq_cap(device_t dev, unsigned pos)
83 /* Handle bugs in valid hypertransport frequency reporting */
86 freq_cap = pci_read_config16(dev, pos);
87 freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */
89 /* AMD 8131 Errata 48 */
90 if ((dev->vendor == PCI_VENDOR_ID_AMD) &&
91 (dev->device == PCI_DEVICE_ID_AMD_8131_PCIX)) {
92 freq_cap &= ~(1 << HT_FREQ_800Mhz);
94 /* AMD 8151 Errata 23 */
95 if ((dev->vendor == PCI_VENDOR_ID_AMD) &&
96 (dev->device == PCI_DEVICE_ID_AMD_8151_SYSCTRL)) {
97 freq_cap &= ~(1 << HT_FREQ_800Mhz);
99 /* AMD K8 Unsupported 1Ghz? */
100 if ((dev->vendor == PCI_VENDOR_ID_AMD) && (dev->device == 0x1100)) {
101 #if CONFIG_K8_HT_FREQ_1G_SUPPORT == 1
102 #if CONFIG_K8_REV_F_SUPPORT == 0
103 if (is_cpu_pre_e0()) { // only e0 later suupport 1GHz HT
104 freq_cap &= ~(1 << HT_FREQ_1000Mhz);
108 freq_cap &= ~(1 << HT_FREQ_1000Mhz);
119 unsigned char ctrl_off, config_off, freq_off, freq_cap_off;
122 static int ht_setup_link(struct ht_link *prev, device_t dev, unsigned pos)
125 static const uint8_t link_width_to_pow2[]= { 3, 4, 0, 5, 1, 2, 0, 0 };
126 static const uint8_t pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 };
127 unsigned present_width_cap, upstream_width_cap;
128 unsigned present_freq_cap, upstream_freq_cap;
129 unsigned ln_present_width_in, ln_upstream_width_in;
130 unsigned ln_present_width_out, ln_upstream_width_out;
131 unsigned freq, old_freq;
132 unsigned present_width, upstream_width, old_width;
134 struct ht_link cur[1];
138 /* Set the hypertransport link width and frequency */
140 /* See which side of the device our previous write to
141 * set the unitid came from.
145 linkb_to_host = (pci_read_config16(cur->dev, cur->pos + PCI_CAP_FLAGS) >> 10) & 1;
146 if (!linkb_to_host) {
147 cur->ctrl_off = PCI_HT_CAP_SLAVE_CTRL0;
148 cur->config_off = PCI_HT_CAP_SLAVE_WIDTH0;
149 cur->freq_off = PCI_HT_CAP_SLAVE_FREQ0;
150 cur->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP0;
153 cur->ctrl_off = PCI_HT_CAP_SLAVE_CTRL1;
154 cur->config_off = PCI_HT_CAP_SLAVE_WIDTH1;
155 cur->freq_off = PCI_HT_CAP_SLAVE_FREQ1;
156 cur->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP1;
159 /* Read the capabilities */
160 present_freq_cap = ht_read_freq_cap(cur->dev, cur->pos + cur->freq_cap_off);
161 upstream_freq_cap = ht_read_freq_cap(prev->dev, prev->pos + prev->freq_cap_off);
162 present_width_cap = pci_read_config8(cur->dev, cur->pos + cur->config_off);
163 upstream_width_cap = pci_read_config8(prev->dev, prev->pos + prev->config_off);
165 /* Calculate the highest useable frequency */
166 freq = log2(present_freq_cap & upstream_freq_cap);
168 /* Calculate the highest width */
169 ln_upstream_width_in = link_width_to_pow2[upstream_width_cap & 7];
170 ln_present_width_out = link_width_to_pow2[(present_width_cap >> 4) & 7];
171 if (ln_upstream_width_in > ln_present_width_out) {
172 ln_upstream_width_in = ln_present_width_out;
174 upstream_width = pow2_to_link_width[ln_upstream_width_in];
175 present_width = pow2_to_link_width[ln_upstream_width_in] << 4;
177 ln_upstream_width_out = link_width_to_pow2[(upstream_width_cap >> 4) & 7];
178 ln_present_width_in = link_width_to_pow2[present_width_cap & 7];
179 if (ln_upstream_width_out > ln_present_width_in) {
180 ln_upstream_width_out = ln_present_width_in;
182 upstream_width |= pow2_to_link_width[ln_upstream_width_out] << 4;
183 present_width |= pow2_to_link_width[ln_upstream_width_out];
185 /* Set the current device */
186 old_freq = pci_read_config8(cur->dev, cur->pos + cur->freq_off);
188 if (freq != old_freq) {
190 pci_write_config8(cur->dev, cur->pos + cur->freq_off, freq);
192 printk(BIOS_SPEW, "HyperT FreqP old %x new %x\n",old_freq,freq);
193 new_freq = pci_read_config8(cur->dev, cur->pos + cur->freq_off);
195 if (new_freq != freq) {
196 printk(BIOS_ERR, "%s Hypertransport frequency would not set wanted: %x got: %x\n",
197 dev_path(dev), freq, new_freq);
200 old_width = pci_read_config8(cur->dev, cur->pos + cur->config_off + 1);
201 if (present_width != old_width) {
203 pci_write_config8(cur->dev, cur->pos + cur->config_off + 1,
206 printk(BIOS_SPEW, "HyperT widthP old %x new %x\n",old_width, present_width);
207 new_width = pci_read_config8(cur->dev, cur->pos + cur->config_off + 1);
208 if (new_width != present_width) {
209 printk(BIOS_ERR, "%s Hypertransport width would not set wanted: %x got: %x\n",
210 dev_path(dev), present_width, new_width);
214 /* Set the upstream device */
215 old_freq = pci_read_config8(prev->dev, prev->pos + prev->freq_off);
217 if (freq != old_freq) {
219 pci_write_config8(prev->dev, prev->pos + prev->freq_off, freq);
221 printk(BIOS_SPEW, "HyperT freqU old %x new %x\n", old_freq, freq);
222 new_freq = pci_read_config8(prev->dev, prev->pos + prev->freq_off);
224 if (new_freq != freq) {
225 printk(BIOS_ERR, "%s Hypertransport frequency would not set wanted: %x got: %x\n",
226 dev_path(prev->dev), freq, new_freq);
229 old_width = pci_read_config8(prev->dev, prev->pos + prev->config_off + 1);
230 if (upstream_width != old_width) {
232 pci_write_config8(prev->dev, prev->pos + prev->config_off + 1, upstream_width);
234 printk(BIOS_SPEW, "HyperT widthU old %x new %x\n", old_width, upstream_width);
235 new_width = pci_read_config8(prev->dev, prev->pos + prev->config_off + 1);
236 if (new_width != upstream_width) {
237 printk(BIOS_ERR, "%s Hypertransport width would not set wanted: %x got: %x\n",
238 dev_path(prev->dev), upstream_width, new_width);
243 /* Remember the current link as the previous link,
244 * But look at the other offsets.
246 prev->dev = cur->dev;
247 prev->pos = cur->pos;
248 if (cur->ctrl_off == PCI_HT_CAP_SLAVE_CTRL0) {
249 prev->ctrl_off = PCI_HT_CAP_SLAVE_CTRL1;
250 prev->config_off = PCI_HT_CAP_SLAVE_WIDTH1;
251 prev->freq_off = PCI_HT_CAP_SLAVE_FREQ1;
252 prev->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP1;
254 prev->ctrl_off = PCI_HT_CAP_SLAVE_CTRL0;
255 prev->config_off = PCI_HT_CAP_SLAVE_WIDTH0;
256 prev->freq_off = PCI_HT_CAP_SLAVE_FREQ0;
257 prev->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP0;
263 static unsigned ht_lookup_slave_capability(struct device *dev)
268 pos = pci_find_next_capability(dev, PCI_CAP_ID_HT, pos);
271 flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
272 printk(BIOS_SPEW, "flags: 0x%04x\n", flags);
273 if ((flags >> 13) == 0) {
274 /* Entry is a Slave secondary, success... */
282 static void ht_collapse_early_enumeration(struct bus *bus, unsigned offset_unitid)
288 /* Initialize the hypertransport enumeration state */
291 prev.ctrl_off = PCI_HT_CAP_HOST_CTRL;
292 prev.config_off = PCI_HT_CAP_HOST_WIDTH;
293 prev.freq_off = PCI_HT_CAP_HOST_FREQ;
294 prev.freq_cap_off = PCI_HT_CAP_HOST_FREQ_CAP;
296 /* Wait until the link initialization is complete */
298 ctrl = pci_read_config16(prev.dev, prev.pos + prev.ctrl_off);
299 /* Is this the end of the hypertransport chain */
300 if (ctrl & (1 << 6)) {
303 /* Has the link failed? */
304 if (ctrl & (1 << 4)) {
306 * Either the link has failed, or we have
308 * Sometimes this can happen due to link
309 * retrain, so lets knock it down and see
312 ctrl |= ((1 << 4) | (1 <<8)); // Link fail + Crc
313 pci_write_config16(prev.dev, prev.pos + prev.ctrl_off, ctrl);
314 ctrl = pci_read_config16(prev.dev, prev.pos + prev.ctrl_off);
315 if (ctrl & ((1 << 4) | (1 << 8))) {
316 printk(BIOS_ALERT, "Detected error on Hypertransport Link\n");
320 } while((ctrl & (1 << 5)) == 0);
322 //actually, only for one HT device HT chain, and unitid is 0
323 #if CONFIG_HT_CHAIN_UNITID_BASE == 0
329 /* Check if is already collapsed */
330 if((!offset_unitid)|| (offset_unitid && (!((CONFIG_HT_CHAIN_END_UNITID_BASE == 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE <CONFIG_HT_CHAIN_UNITID_BASE))))) {
334 dummy.path.type = DEVICE_PATH_PCI;
335 dummy.path.pci.devfn = PCI_DEVFN(0, 0);
336 id = pci_read_config32(&dummy, PCI_VENDOR_ID);
337 if ( ! ( (id == 0xffffffff) || (id == 0x00000000) ||
338 (id == 0x0000ffff) || (id == 0xffff0000) ) ) {
343 /* Spin through the devices and collapse any early
344 * hypertransport enumeration.
346 for(devfn = PCI_DEVFN(1, 0); devfn <= 0xff; devfn += 8) {
351 dummy.path.type = DEVICE_PATH_PCI;
352 dummy.path.pci.devfn = devfn;
353 id = pci_read_config32(&dummy, PCI_VENDOR_ID);
354 if ( (id == 0xffffffff) || (id == 0x00000000) ||
355 (id == 0x0000ffff) || (id == 0xffff0000)) {
358 dummy.vendor = id & 0xffff;
359 dummy.device = (id >> 16) & 0xffff;
360 dummy.hdr_type = pci_read_config8(&dummy, PCI_HEADER_TYPE);
361 pos = ht_lookup_slave_capability(&dummy);
366 /* Clear the unitid */
367 flags = pci_read_config16(&dummy, pos + PCI_CAP_FLAGS);
369 pci_write_config16(&dummy, pos + PCI_CAP_FLAGS, flags);
370 printk(BIOS_SPEW, "Collapsing %s [%04x/%04x]\n",
371 dev_path(&dummy), dummy.vendor, dummy.device);
375 unsigned int hypertransport_scan_chain(struct bus *bus,
376 unsigned min_devfn, unsigned max_devfn, unsigned int max, unsigned *ht_unitid_base, unsigned offset_unitid)
378 //even CONFIG_HT_CHAIN_UNITID_BASE == 0, we still can go through this function, because of end_of_chain check, also We need it to optimize link
379 unsigned next_unitid, last_unitid;
380 device_t old_devices, dev, func;
381 unsigned min_unitid = (offset_unitid) ? CONFIG_HT_CHAIN_UNITID_BASE:1;
383 device_t last_func = 0;
387 #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
388 //let't record the device of last ht device, So we can set the Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE
389 unsigned real_last_unitid=0;
390 uint8_t real_last_pos=0;
391 device_t real_last_dev=NULL;
392 unsigned end_used = 0;
395 /* Restore the hypertransport chain to it's unitialized state */
396 ht_collapse_early_enumeration(bus, offset_unitid);
398 /* See which static device nodes I have */
399 old_devices = bus->children;
402 /* Initialize the hypertransport enumeration state */
405 prev.ctrl_off = PCI_HT_CAP_HOST_CTRL;
406 prev.config_off = PCI_HT_CAP_HOST_WIDTH;
407 prev.freq_off = PCI_HT_CAP_HOST_FREQ;
408 prev.freq_cap_off = PCI_HT_CAP_HOST_FREQ_CAP;
410 /* If present assign unitid to a hypertransport chain */
411 last_unitid = min_unitid -1;
412 max_unitid = next_unitid = min_unitid;
416 unsigned count, static_count;
419 last_unitid = next_unitid;
421 /* Wait until the link initialization is complete */
423 ctrl = pci_read_config16(prev.dev, prev.pos + prev.ctrl_off);
426 goto end_of_chain; // End of chain
428 if (ctrl & ((1 << 4) | (1 << 8))) {
430 * Either the link has failed, or we have
432 * Sometimes this can happen due to link
433 * retrain, so lets knock it down and see
436 ctrl |= ((1 << 4) | (1 <<8)); // Link fail + Crc
437 pci_write_config16(prev.dev, prev.pos + prev.ctrl_off, ctrl);
438 ctrl = pci_read_config16(prev.dev, prev.pos + prev.ctrl_off);
439 if (ctrl & ((1 << 4) | (1 << 8))) {
440 printk(BIOS_ALERT, "Detected error on Hypertransport Link\n");
444 } while((ctrl & (1 << 5)) == 0);
447 /* Get and setup the device_structure */
448 dev = ht_scan_get_devs(&old_devices);
450 /* See if a device is present and setup the
453 dev = pci_probe_dev(dev, bus, 0);
454 if (!dev || !dev->enabled) {
458 /* Find the hypertransport link capability */
459 pos = ht_lookup_slave_capability(dev);
461 printk(BIOS_ERR, "%s Hypertransport link capability not found",
466 /* Update the Unitid of the current device */
467 flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
469 /* If the devices has a unitid set and is at devfn 0 we are done.
470 * This can happen with shadow hypertransport devices,
471 * or if we have reached the bottom of a
472 * hypertransport device chain.
477 flags &= ~0x1f; /* mask out base Unit ID */
479 count = (flags >> 5) & 0x1f; /* get unit count */
480 #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
482 if(next_unitid > (max_devfn>>3)) { // max_devfn will be (0x17<<3)|7 or (0x1f<<3)|7
484 next_unitid = CONFIG_HT_CHAIN_END_UNITID_BASE;
494 flags |= next_unitid & 0x1f;
495 pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags);
497 /* Update the Unitd id in the device structure */
499 for(func = dev; func; func = func->sibling) {
500 func->path.pci.devfn += (next_unitid << 3);
501 static_count = (func->path.pci.devfn >> 3)
502 - (dev->path.pci.devfn >> 3) + 1;
505 /* Compute the number of unitids consumed */
506 printk(BIOS_SPEW, "%s count: %04x static_count: %04x\n",
507 dev_path(dev), count, static_count);
508 if (count < static_count) {
509 count = static_count;
512 /* Update the Unitid of the next device */
513 ht_unitid_base[ht_dev_num] = next_unitid;
516 #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
519 real_last_unitid = next_unitid;
523 next_unitid += count;
524 if (next_unitid > max_unitid) {
525 max_unitid = next_unitid;
528 /* Setup the hypetransport link */
529 bus->reset_needed |= ht_setup_link(&prev, dev, pos);
531 printk(BIOS_DEBUG, "%s [%04x/%04x] %s next_unitid: %04x\n",
533 dev->vendor, dev->device,
534 (dev->enabled? "enabled": "disabled"), next_unitid);
536 } while (last_unitid != next_unitid);
539 if(bus->reset_needed) {
540 printk(BIOS_INFO, "HyperT reset needed\n");
543 printk(BIOS_DEBUG, "HyperT reset not needed\n");
547 #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
548 if(offset_unitid && (ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used) {
550 flags = pci_read_config16(real_last_dev, real_last_pos + PCI_CAP_FLAGS);
552 flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f;
553 pci_write_config16(real_last_dev, real_last_pos + PCI_CAP_FLAGS, flags);
555 for(func = real_last_dev; func; func = func->sibling) {
556 func->path.pci.devfn -= ((real_last_unitid - CONFIG_HT_CHAIN_END_UNITID_BASE) << 3);
560 ht_unitid_base[ht_dev_num-1] = CONFIG_HT_CHAIN_END_UNITID_BASE; // update last one
562 printk(BIOS_DEBUG, " unitid: %04x --> %04x\n",
563 real_last_unitid, CONFIG_HT_CHAIN_END_UNITID_BASE);
567 next_unitid = max_unitid;
569 if (next_unitid > 0x20) {
572 if( (bus->secondary == 0) && (next_unitid > 0x18)) {
573 next_unitid = 0x18; /* avoid K8 on bus 0 */
576 /* Die if any leftover Static devices are are found.
577 * There's probably a problem in the Config.lb.
581 for(left = old_devices; left; left = left->sibling) {
582 printk(BIOS_DEBUG, "%s\n", dev_path(left));
584 printk(BIOS_ERR, "HT: Left over static devices. Check your Config.lb\n");
585 if(last_func && !last_func->sibling) // put back the left over static device, and let pci_scan_bus disable it
586 last_func->sibling = old_devices;
589 /* Now that nothing is overlapping it is safe to scan the
592 max = pci_scan_bus(bus, 0x00, ((next_unitid-1) << 3)|7, max);
597 * Scan a PCI bridge and the buses behind the bridge.
599 * Determine the existence of buses behind the bridge. Set up the bridge
600 * according to the result of the scan.
602 * This function is the default scan_bus() method for PCI bridge devices.
605 * @param min_devfn TODO
606 * @param max_devfn TODO
607 * @param max The highest bus number assgined up to now.
608 * @return The maximum bus number found, after scanning all subordinate busses.
610 static unsigned int hypertransport_scan_chain_x(struct bus *bus,
611 unsigned min_devfn, unsigned max_devfn, unsigned int max)
613 unsigned ht_unitid_base[4];
614 unsigned offset_unitid = 1;
615 return hypertransport_scan_chain(bus, min_devfn, max_devfn, max, ht_unitid_base, offset_unitid);
618 unsigned int ht_scan_bridge(struct device *dev, unsigned int max)
620 return do_pci_scan_bridge(dev, max, hypertransport_scan_chain_x);
623 /** Default device operations for hypertransport bridges */
624 static struct pci_operations ht_bus_ops_pci = {
628 struct device_operations default_ht_ops_bus = {
629 .read_resources = pci_bus_read_resources,
630 .set_resources = pci_dev_set_resources,
631 .enable_resources = pci_bus_enable_resources,
633 .scan_bus = ht_scan_bridge,
635 .reset_bus = pci_bus_reset,
636 .ops_pci = &ht_bus_ops_pci,