src/devices/hypertransport.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2003-2004 Linux Networx
   5  * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
   6  * Copyright (C) 2004 David Hendricks <sc@flagen.com>
   7  * Copyright (C) 2004 Li-Ta Lo <ollie@lanl.gov>
   8  * Copyright (C) 2005-2006 Tyan
   9  * (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
  10  * Copyright (C) 2005-2006 Stefan Reinauer <stepan@openbios.org>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; version 2 of the License.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  24  */
  25
  26 #include <bitops.h>
  27 #include <console/console.h>
  28 #include <device/device.h>
  29 #include <device/path.h>
  30 #include <device/pci.h>
  31 #include <device/pci_ids.h>
  32 #include <device/hypertransport.h>
  33
  34 /*
  35  * The hypertransport link is already optimized in pre-RAM code so don't do
  36  * it again.
  37  */
  38 #define OPT_HT_LINK 0
  39
  40 #if OPT_HT_LINK == 1
  41 #include <cpu/amd/model_fxx_rev.h>
  42 #endif
  43
  44 static device_t ht_scan_get_devs(device_t *old_devices)
  45 {
  46         device_t first, last;
  47         first = *old_devices;
  48         last = first;
  49         /* Extract the chain of devices to (first through last)
  50          * for the next hypertransport device.
  51          */
  52         while(last && last->sibling &&
  53                 (last->sibling->path.type == DEVICE_PATH_PCI) &&
  54                 (last->sibling->path.pci.devfn > last->path.pci.devfn))
  55         {
  56                 last = last->sibling;
  57         }
  58         if (first) {
  59                 device_t child;
  60                 /* Unlink the chain from the list of old devices */
  61                 *old_devices = last->sibling;
  62                 last->sibling = 0;
  63
  64                 /* Now add the device to the list of devices on the bus.
  65                  */
  66                 /* Find the last child of our parent */
  67                 for(child = first->bus->children; child && child->sibling; ) {
  68                         child = child->sibling;
  69                 }
  70                 /* Place the chain on the list of children of their parent. */
  71                 if (child) {
  72                         child->sibling = first;
  73                 } else {
  74                         first->bus->children = first;
  75                 }
  76         }
  77         return first;
  78 }
  79
  80 #if OPT_HT_LINK == 1
  81 static unsigned ht_read_freq_cap(device_t dev, unsigned pos)
  82 {
  83         /* Handle bugs in valid hypertransport frequency reporting */
  84         unsigned freq_cap;
  85
  86         freq_cap = pci_read_config16(dev, pos);
  87         freq_cap &= ~(1 << HT_FREQ_VENDOR); /* Ignore Vendor HT frequencies */
  88
  89         /* AMD 8131 Errata 48 */
  90         if ((dev->vendor == PCI_VENDOR_ID_AMD) &&
  91                 (dev->device == PCI_DEVICE_ID_AMD_8131_PCIX)) {
  92                 freq_cap &= ~(1 << HT_FREQ_800Mhz);
  93         }
  94         /* AMD 8151 Errata 23 */
  95         if ((dev->vendor == PCI_VENDOR_ID_AMD) &&
  96                 (dev->device == PCI_DEVICE_ID_AMD_8151_SYSCTRL)) {
  97                 freq_cap &= ~(1 << HT_FREQ_800Mhz);
  98         }
  99         /* AMD K8 Unsupported 1Ghz? */
 100         if ((dev->vendor == PCI_VENDOR_ID_AMD) && (dev->device == 0x1100)) {
 101 #if CONFIG_K8_HT_FREQ_1G_SUPPORT == 1
 102         #if CONFIG_K8_REV_F_SUPPORT == 0
 103                 if (is_cpu_pre_e0()) { // only e0 later suupport 1GHz HT
 104                         freq_cap &= ~(1 << HT_FREQ_1000Mhz);
 105                 }
 106         #endif
 107 #else
 108                 freq_cap &= ~(1 << HT_FREQ_1000Mhz);
 109 #endif
 110
 111         }
 112         return freq_cap;
 113 }
 114 #endif
 115
 116 struct ht_link {
 117         struct device *dev;
 118         unsigned pos;
 119         unsigned char ctrl_off, config_off, freq_off, freq_cap_off;
 120 };
 121
 122 static int ht_setup_link(struct ht_link *prev, device_t dev, unsigned pos)
 123 {
 124 #if OPT_HT_LINK == 1
 125         static const uint8_t link_width_to_pow2[]= { 3, 4, 0, 5, 1, 2, 0, 0 };
 126         static const uint8_t pow2_to_link_width[] = { 0x7, 4, 5, 0, 1, 3 };
 127         unsigned present_width_cap,    upstream_width_cap;
 128         unsigned present_freq_cap,     upstream_freq_cap;
 129         unsigned ln_present_width_in,  ln_upstream_width_in;
 130         unsigned ln_present_width_out, ln_upstream_width_out;
 131         unsigned freq, old_freq;
 132         unsigned present_width, upstream_width, old_width;
 133 #endif
 134         struct ht_link cur[1];
 135         int reset_needed;
 136         int linkb_to_host;
 137
 138         /* Set the hypertransport link width and frequency */
 139         reset_needed = 0;
 140         /* See which side of the device our previous write to
 141          * set the unitid came from.
 142          */
 143         cur->dev = dev;
 144         cur->pos = pos;
 145         linkb_to_host = (pci_read_config16(cur->dev, cur->pos + PCI_CAP_FLAGS) >> 10) & 1;
 146         if (!linkb_to_host) {
 147                 cur->ctrl_off     = PCI_HT_CAP_SLAVE_CTRL0;
 148                 cur->config_off   = PCI_HT_CAP_SLAVE_WIDTH0;
 149                 cur->freq_off     = PCI_HT_CAP_SLAVE_FREQ0;
 150                 cur->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP0;
 151         }
 152         else {
 153                 cur->ctrl_off     = PCI_HT_CAP_SLAVE_CTRL1;
 154                 cur->config_off   = PCI_HT_CAP_SLAVE_WIDTH1;
 155                 cur->freq_off     = PCI_HT_CAP_SLAVE_FREQ1;
 156                 cur->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP1;
 157         }
 158 #if OPT_HT_LINK == 1
 159         /* Read the capabilities */
 160         present_freq_cap   = ht_read_freq_cap(cur->dev, cur->pos + cur->freq_cap_off);
 161         upstream_freq_cap  = ht_read_freq_cap(prev->dev, prev->pos + prev->freq_cap_off);
 162         present_width_cap  = pci_read_config8(cur->dev, cur->pos + cur->config_off);
 163         upstream_width_cap = pci_read_config8(prev->dev, prev->pos + prev->config_off);
 164
 165         /* Calculate the highest useable frequency */
 166         freq = log2(present_freq_cap & upstream_freq_cap);
 167
 168         /* Calculate the highest width */
 169         ln_upstream_width_in = link_width_to_pow2[upstream_width_cap & 7];
 170         ln_present_width_out = link_width_to_pow2[(present_width_cap >> 4) & 7];
 171         if (ln_upstream_width_in > ln_present_width_out) {
 172                 ln_upstream_width_in = ln_present_width_out;
 173         }
 174         upstream_width = pow2_to_link_width[ln_upstream_width_in];
 175         present_width  = pow2_to_link_width[ln_upstream_width_in] << 4;
 176
 177         ln_upstream_width_out = link_width_to_pow2[(upstream_width_cap >> 4) & 7];
 178         ln_present_width_in   = link_width_to_pow2[present_width_cap & 7];
 179         if (ln_upstream_width_out > ln_present_width_in) {
 180                 ln_upstream_width_out = ln_present_width_in;
 181         }
 182         upstream_width |= pow2_to_link_width[ln_upstream_width_out] << 4;
 183         present_width  |= pow2_to_link_width[ln_upstream_width_out];
 184
 185         /* Set the current device */
 186         old_freq = pci_read_config8(cur->dev, cur->pos + cur->freq_off);
 187         old_freq &= 0x0f;
 188         if (freq != old_freq) {
 189                 unsigned new_freq;
 190                 pci_write_config8(cur->dev, cur->pos + cur->freq_off, freq);
 191                 reset_needed = 1;
 192                 printk(BIOS_SPEW, "HyperT FreqP old %x new %x\n",old_freq,freq);
 193                 new_freq = pci_read_config8(cur->dev, cur->pos + cur->freq_off);
 194                 new_freq &= 0x0f;
 195                 if (new_freq != freq) {
 196                         printk(BIOS_ERR, "%s Hypertransport frequency would not set wanted: %x got: %x\n",
 197                                 dev_path(dev), freq, new_freq);
 198                 }
 199         }
 200         old_width = pci_read_config8(cur->dev, cur->pos + cur->config_off + 1);
 201         if (present_width != old_width) {
 202                 unsigned new_width;
 203                 pci_write_config8(cur->dev, cur->pos + cur->config_off + 1,
 204                         present_width);
 205                 reset_needed = 1;
 206                 printk(BIOS_SPEW, "HyperT widthP old %x new %x\n",old_width, present_width);
 207                 new_width = pci_read_config8(cur->dev, cur->pos + cur->config_off + 1);
 208                 if (new_width != present_width) {
 209                         printk(BIOS_ERR, "%s Hypertransport width would not set wanted: %x got: %x\n",
 210                                 dev_path(dev), present_width, new_width);
 211                 }
 212         }
 213
 214         /* Set the upstream device */
 215         old_freq = pci_read_config8(prev->dev, prev->pos + prev->freq_off);
 216         old_freq &= 0x0f;
 217         if (freq != old_freq) {
 218                 unsigned new_freq;
 219                 pci_write_config8(prev->dev, prev->pos + prev->freq_off, freq);
 220                 reset_needed = 1;
 221                 printk(BIOS_SPEW, "HyperT freqU old %x new %x\n", old_freq, freq);
 222                 new_freq = pci_read_config8(prev->dev, prev->pos + prev->freq_off);
 223                 new_freq &= 0x0f;
 224                 if (new_freq != freq) {
 225                         printk(BIOS_ERR, "%s Hypertransport frequency would not set wanted: %x got: %x\n",
 226                                 dev_path(prev->dev), freq, new_freq);
 227                 }
 228         }
 229         old_width = pci_read_config8(prev->dev, prev->pos + prev->config_off + 1);
 230         if (upstream_width != old_width) {
 231                 unsigned new_width;
 232                 pci_write_config8(prev->dev, prev->pos + prev->config_off + 1, upstream_width);
 233                 reset_needed = 1;
 234                 printk(BIOS_SPEW, "HyperT widthU old %x new %x\n", old_width, upstream_width);
 235                 new_width = pci_read_config8(prev->dev, prev->pos + prev->config_off + 1);
 236                 if (new_width != upstream_width) {
 237                         printk(BIOS_ERR, "%s Hypertransport width would not set wanted: %x got: %x\n",
 238                                 dev_path(prev->dev), upstream_width, new_width);
 239                 }
 240         }
 241 #endif
 242
 243         /* Remember the current link as the previous link,
 244          * But look at the other offsets.
 245          */
 246         prev->dev = cur->dev;
 247         prev->pos = cur->pos;
 248         if (cur->ctrl_off == PCI_HT_CAP_SLAVE_CTRL0) {
 249                 prev->ctrl_off     = PCI_HT_CAP_SLAVE_CTRL1;
 250                 prev->config_off   = PCI_HT_CAP_SLAVE_WIDTH1;
 251                 prev->freq_off     = PCI_HT_CAP_SLAVE_FREQ1;
 252                 prev->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP1;
 253         } else {
 254                 prev->ctrl_off     = PCI_HT_CAP_SLAVE_CTRL0;
 255                 prev->config_off   = PCI_HT_CAP_SLAVE_WIDTH0;
 256                 prev->freq_off     = PCI_HT_CAP_SLAVE_FREQ0;
 257                 prev->freq_cap_off = PCI_HT_CAP_SLAVE_FREQ_CAP0;
 258         }
 259
 260         return reset_needed;
 261 }
 262
 263 static unsigned ht_lookup_slave_capability(struct device *dev)
 264 {
 265         unsigned pos;
 266         pos = 0;
 267         do {
 268                 pos = pci_find_next_capability(dev, PCI_CAP_ID_HT, pos);
 269                 if (pos) {
 270                         unsigned flags;
 271                         flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
 272                         printk(BIOS_SPEW, "flags: 0x%04x\n", flags);
 273                         if ((flags >> 13) == 0) {
 274                                 /* Entry is a Slave secondary, success... */
 275                                 break;
 276                         }
 277                 }
 278         } while(pos);
 279         return pos;
 280 }
 281
 282 static void ht_collapse_early_enumeration(struct bus *bus, unsigned offset_unitid)
 283 {
 284         unsigned int devfn;
 285         struct ht_link prev;
 286         unsigned ctrl;
 287
 288         /* Initialize the hypertransport enumeration state */
 289         prev.dev = bus->dev;
 290         prev.pos = bus->cap;
 291         prev.ctrl_off     = PCI_HT_CAP_HOST_CTRL;
 292         prev.config_off   = PCI_HT_CAP_HOST_WIDTH;
 293         prev.freq_off     = PCI_HT_CAP_HOST_FREQ;
 294         prev.freq_cap_off = PCI_HT_CAP_HOST_FREQ_CAP;
 295
 296         /* Wait until the link initialization is complete */
 297         do {
 298                 ctrl = pci_read_config16(prev.dev, prev.pos + prev.ctrl_off);
 299                 /* Is this the end of the hypertransport chain */
 300                 if (ctrl & (1 << 6)) {
 301                         return;
 302                 }
 303                 /* Has the link failed? */
 304                 if (ctrl & (1 << 4)) {
 305                         /*
 306                          * Either the link has failed, or we have
 307                          * a CRC error.
 308                          * Sometimes this can happen due to link
 309                          * retrain, so lets knock it down and see
 310                          * if its transient
 311                          */
 312                         ctrl |= ((1 << 4) | (1 <<8)); // Link fail + Crc
 313                         pci_write_config16(prev.dev, prev.pos + prev.ctrl_off, ctrl);
 314                         ctrl = pci_read_config16(prev.dev, prev.pos + prev.ctrl_off);
 315                         if (ctrl & ((1 << 4) | (1 << 8))) {
 316                                 printk(BIOS_ALERT, "Detected error on Hypertransport Link\n");
 317                                 return;
 318                         }
 319                 }
 320         } while((ctrl & (1 << 5)) == 0);
 321
 322                 //actually, only for one HT device HT chain, and unitid is 0
 323 #if CONFIG_HT_CHAIN_UNITID_BASE == 0
 324         if(offset_unitid) {
 325                 return;
 326         }
 327 #endif
 328
 329         /* Check if is already collapsed */
 330         if((!offset_unitid)|| (offset_unitid && (!((CONFIG_HT_CHAIN_END_UNITID_BASE == 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE <CONFIG_HT_CHAIN_UNITID_BASE))))) {
 331                 struct device dummy;
 332                 uint32_t id;
 333                 dummy.bus              = bus;
 334                 dummy.path.type        = DEVICE_PATH_PCI;
 335                 dummy.path.pci.devfn = PCI_DEVFN(0, 0);
 336                 id = pci_read_config32(&dummy, PCI_VENDOR_ID);
 337                 if ( ! ( (id == 0xffffffff) || (id == 0x00000000) ||
 338                     (id == 0x0000ffff) || (id == 0xffff0000) ) ) {
 339                              return;
 340                 }
 341         }
 342
 343         /* Spin through the devices and collapse any early
 344          * hypertransport enumeration.
 345          */
 346         for(devfn = PCI_DEVFN(1, 0); devfn <= 0xff; devfn += 8) {
 347                 struct device dummy;
 348                 uint32_t id;
 349                 unsigned pos, flags;
 350                 dummy.bus              = bus;
 351                 dummy.path.type        = DEVICE_PATH_PCI;
 352                 dummy.path.pci.devfn = devfn;
 353                 id = pci_read_config32(&dummy, PCI_VENDOR_ID);
 354                 if (    (id == 0xffffffff) || (id == 0x00000000) ||
 355                         (id == 0x0000ffff) || (id == 0xffff0000)) {
 356                         continue;
 357                 }
 358                 dummy.vendor = id & 0xffff;
 359                 dummy.device = (id >> 16) & 0xffff;
 360                 dummy.hdr_type = pci_read_config8(&dummy, PCI_HEADER_TYPE);
 361                 pos = ht_lookup_slave_capability(&dummy);
 362                 if (!pos){
 363                         continue;
 364                 }
 365
 366                 /* Clear the unitid */
 367                 flags = pci_read_config16(&dummy, pos + PCI_CAP_FLAGS);
 368                 flags &= ~0x1f;
 369                 pci_write_config16(&dummy, pos + PCI_CAP_FLAGS, flags);
 370                 printk(BIOS_SPEW, "Collapsing %s [%04x/%04x]\n",
 371                         dev_path(&dummy), dummy.vendor, dummy.device);
 372         }
 373 }
 374
 375 unsigned int hypertransport_scan_chain(struct bus *bus,
 376         unsigned min_devfn, unsigned max_devfn, unsigned int max, unsigned *ht_unitid_base, unsigned offset_unitid)
 377 {
 378         //even CONFIG_HT_CHAIN_UNITID_BASE == 0, we still can go through this function, because of end_of_chain check, also We need it to optimize link
 379         unsigned next_unitid, last_unitid;
 380         device_t old_devices, dev, func;
 381         unsigned min_unitid = (offset_unitid) ? CONFIG_HT_CHAIN_UNITID_BASE:1;
 382         struct ht_link prev;
 383         device_t last_func = 0;
 384         int ht_dev_num = 0;
 385         unsigned max_unitid;
 386
 387 #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
 388         //let't record the device of last ht device, So we can set the Unitid to CONFIG_HT_CHAIN_END_UNITID_BASE
 389         unsigned real_last_unitid=0;
 390         uint8_t real_last_pos=0;
 391         device_t real_last_dev=NULL;
 392         unsigned end_used = 0;
 393 #endif
 394
 395         /* Restore the hypertransport chain to it's unitialized state */
 396         ht_collapse_early_enumeration(bus, offset_unitid);
 397
 398         /* See which static device nodes I have */
 399         old_devices = bus->children;
 400         bus->children = 0;
 401
 402         /* Initialize the hypertransport enumeration state */
 403         prev.dev = bus->dev;
 404         prev.pos = bus->cap;
 405         prev.ctrl_off     = PCI_HT_CAP_HOST_CTRL;
 406         prev.config_off   = PCI_HT_CAP_HOST_WIDTH;
 407         prev.freq_off     = PCI_HT_CAP_HOST_FREQ;
 408         prev.freq_cap_off = PCI_HT_CAP_HOST_FREQ_CAP;
 409
 410         /* If present assign unitid to a hypertransport chain */
 411         last_unitid = min_unitid -1;
 412         max_unitid = next_unitid = min_unitid;
 413         do {
 414                 uint8_t pos;
 415                 uint16_t flags;
 416                 unsigned count, static_count;
 417                 unsigned ctrl;
 418
 419                 last_unitid = next_unitid;
 420
 421                 /* Wait until the link initialization is complete */
 422                 do {
 423                         ctrl = pci_read_config16(prev.dev, prev.pos + prev.ctrl_off);
 424
 425                         if (ctrl & (1 << 6))
 426                                 goto end_of_chain;      // End of chain
 427
 428                         if (ctrl & ((1 << 4) | (1 << 8))) {
 429                                 /*
 430                                  * Either the link has failed, or we have
 431                                  * a CRC error.
 432                                  * Sometimes this can happen due to link
 433                                  * retrain, so lets knock it down and see
 434                                  * if its transient
 435                                  */
 436                                 ctrl |= ((1 << 4) | (1 <<8)); // Link fail + Crc
 437                                 pci_write_config16(prev.dev, prev.pos + prev.ctrl_off, ctrl);
 438                                 ctrl = pci_read_config16(prev.dev, prev.pos + prev.ctrl_off);
 439                                 if (ctrl & ((1 << 4) | (1 << 8))) {
 440                                         printk(BIOS_ALERT, "Detected error on Hypertransport Link\n");
 441                                         goto end_of_chain;
 442                                 }
 443                         }
 444                 } while((ctrl & (1 << 5)) == 0);
 445
 446
 447                 /* Get and setup the device_structure */
 448                 dev = ht_scan_get_devs(&old_devices);
 449
 450                 /* See if a device is present and setup the
 451                  * device structure.
 452                  */
 453                 dev = pci_probe_dev(dev, bus, 0);
 454                 if (!dev || !dev->enabled) {
 455                         break;
 456                 }
 457
 458                 /* Find the hypertransport link capability */
 459                 pos = ht_lookup_slave_capability(dev);
 460                 if (pos == 0) {
 461                         printk(BIOS_ERR, "%s Hypertransport link capability not found",
 462                                 dev_path(dev));
 463                         break;
 464                 }
 465
 466                 /* Update the Unitid of the current device */
 467                 flags = pci_read_config16(dev, pos + PCI_CAP_FLAGS);
 468
 469                 /* If the devices has a unitid set and is at devfn 0 we are done.
 470                  * This can happen with shadow hypertransport devices,
 471                  * or if we have reached the bottom of a
 472                  * hypertransport device chain.
 473                  */
 474                 if (flags & 0x1f) {
 475                         break;
 476                 }
 477                 flags &= ~0x1f; /* mask out base Unit ID */
 478
 479                 count = (flags >> 5) & 0x1f; /* get unit count */
 480 #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
 481                 if(offset_unitid) {
 482                         if(next_unitid > (max_devfn>>3)) { // max_devfn will be (0x17<<3)|7 or (0x1f<<3)|7
 483                                 if(!end_used) {
 484                                         next_unitid = CONFIG_HT_CHAIN_END_UNITID_BASE;
 485                                         end_used = 1;
 486                                 } else {
 487                                         goto end_of_chain;
 488                                 }
 489                         }
 490
 491                 }
 492 #endif
 493
 494                 flags |= next_unitid & 0x1f;
 495                 pci_write_config16(dev, pos + PCI_CAP_FLAGS, flags);
 496
 497                 /* Update the Unitd id in the device structure */
 498                 static_count = 1;
 499                 for(func = dev; func; func = func->sibling) {
 500                         func->path.pci.devfn += (next_unitid << 3);
 501                         static_count = (func->path.pci.devfn >> 3)
 502                                 - (dev->path.pci.devfn >> 3) + 1;
 503                         last_func = func;
 504                 }
 505                 /* Compute the number of unitids consumed */
 506                 printk(BIOS_SPEW, "%s count: %04x static_count: %04x\n",
 507                         dev_path(dev), count, static_count);
 508                 if (count < static_count) {
 509                         count = static_count;
 510                 }
 511
 512                 /* Update the Unitid of the next device */
 513                 ht_unitid_base[ht_dev_num] = next_unitid;
 514                 ht_dev_num++;
 515
 516 #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
 517                 if (offset_unitid) {
 518                         real_last_pos = pos;
 519                         real_last_unitid = next_unitid;
 520                         real_last_dev = dev;
 521                 }
 522 #endif
 523                 next_unitid +=  count;
 524                 if (next_unitid > max_unitid) {
 525                         max_unitid = next_unitid;
 526                 }
 527
 528                 /* Setup the hypetransport link */
 529                 bus->reset_needed |= ht_setup_link(&prev, dev, pos);
 530
 531                 printk(BIOS_DEBUG, "%s [%04x/%04x] %s next_unitid: %04x\n",
 532                         dev_path(dev),
 533                         dev->vendor, dev->device,
 534                         (dev->enabled? "enabled": "disabled"), next_unitid);
 535
 536         } while (last_unitid != next_unitid);
 537  end_of_chain:
 538 #if OPT_HT_LINK == 1
 539         if(bus->reset_needed) {
 540                 printk(BIOS_INFO, "HyperT reset needed\n");
 541         }
 542         else {
 543                 printk(BIOS_DEBUG, "HyperT reset not needed\n");
 544         }
 545 #endif
 546
 547 #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
 548         if(offset_unitid && (ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE)  && !end_used) {
 549                 uint16_t flags;
 550                 flags = pci_read_config16(real_last_dev, real_last_pos + PCI_CAP_FLAGS);
 551                 flags &= ~0x1f;
 552                 flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f;
 553                 pci_write_config16(real_last_dev, real_last_pos + PCI_CAP_FLAGS, flags);
 554
 555                 for(func = real_last_dev; func; func = func->sibling) {
 556                         func->path.pci.devfn -= ((real_last_unitid - CONFIG_HT_CHAIN_END_UNITID_BASE) << 3);
 557                         last_func = func;
 558                 }
 559
 560                 ht_unitid_base[ht_dev_num-1] = CONFIG_HT_CHAIN_END_UNITID_BASE; // update last one
 561
 562                 printk(BIOS_DEBUG, " unitid: %04x --> %04x\n",
 563                                 real_last_unitid, CONFIG_HT_CHAIN_END_UNITID_BASE);
 564
 565         }
 566 #endif
 567         next_unitid = max_unitid;
 568
 569         if (next_unitid > 0x20) {
 570                 next_unitid = 0x20;
 571         }
 572         if( (bus->secondary == 0) && (next_unitid > 0x18)) {
 573                 next_unitid = 0x18; /* avoid K8 on bus 0 */
 574         }
 575
 576         /* Die if any leftover Static devices are are found.
 577          * There's probably a problem in the Config.lb.
 578          */
 579         if(old_devices) {
 580                 device_t left;
 581                 for(left = old_devices; left; left = left->sibling) {
 582                         printk(BIOS_DEBUG, "%s\n", dev_path(left));
 583                 }
 584                 printk(BIOS_ERR, "HT: Left over static devices.  Check your Config.lb\n");
 585                 if(last_func  && !last_func->sibling) // put back the left over static device, and let pci_scan_bus disable it
 586                         last_func->sibling = old_devices;
 587         }
 588
 589         /* Now that nothing is overlapping it is safe to scan the
 590          * children.
 591          */
 592         max = pci_scan_bus(bus, 0x00, ((next_unitid-1) << 3)|7, max);
 593         return max;
 594 }
 595
 596 /**
 597  * Scan a PCI bridge and the buses behind the bridge.
 598  *
 599  * Determine the existence of buses behind the bridge. Set up the bridge
 600  * according to the result of the scan.
 601  *
 602  * This function is the default scan_bus() method for PCI bridge devices.
 603  *
 604  * @param bus TODO
 605  * @param min_devfn TODO
 606  * @param max_devfn TODO
 607  * @param max The highest bus number assgined up to now.
 608  * @return The maximum bus number found, after scanning all subordinate busses.
 609  */
 610 static unsigned int hypertransport_scan_chain_x(struct bus *bus,
 611         unsigned min_devfn, unsigned max_devfn, unsigned int max)
 612 {
 613         unsigned ht_unitid_base[4];
 614         unsigned offset_unitid = 1;
 615         return hypertransport_scan_chain(bus, min_devfn, max_devfn, max, ht_unitid_base, offset_unitid);
 616 }
 617
 618 unsigned int ht_scan_bridge(struct device *dev, unsigned int max)
 619 {
 620         return do_pci_scan_bridge(dev, max, hypertransport_scan_chain_x);
 621 }
 622
 623 /** Default device operations for hypertransport bridges */
 624 static struct pci_operations ht_bus_ops_pci = {
 625         .set_subsystem = 0,
 626 };
 627
 628 struct device_operations default_ht_ops_bus = {
 629         .read_resources   = pci_bus_read_resources,
 630         .set_resources    = pci_dev_set_resources,
 631         .enable_resources = pci_bus_enable_resources,
 632         .init             = 0,
 633         .scan_bus         = ht_scan_bridge,
 634         .enable           = 0,
 635         .reset_bus        = pci_bus_reset,
 636         .ops_pci          = &ht_bus_ops_pci,
 637 };