2 * This file is part of the coreboot project.
4 * Copyright (C) 2005 Linux Networx
5 * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
6 * Copyright (C) 2005 Ronald G. Minnich <rminnich@gmail.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 #include <console/console.h>
23 #include <device/device.h>
24 #include <device/pci.h>
25 #include <device/pci_ids.h>
26 #include <device/cardbus.h>
29 * I don't think this code is quite correct but it is close.
30 * Anyone with a cardbus bridge and a little time should be able
31 * to make it usable quickly. -- Eric Biederman 24 March 2005
35 * IO should be max 256 bytes. However, since we may have a P2P bridge below
36 * a cardbus bridge, we need 4K.
38 #define CARDBUS_IO_SIZE 4096
39 #define CARDBUS_MEM_SIZE (32 * 1024 * 1024)
41 static void cardbus_record_bridge_resource(device_t dev, resource_t moving,
42 resource_t min_size, unsigned int index, unsigned long type)
44 struct resource *resource;
46 /* Initialize the constraints on the current bus. */
52 resource = new_resource(dev, index);
56 while ((moving & step) == 0) {
60 resource->gran = gran;
61 resource->align = gran;
62 resource->limit = moving | (step - 1);
63 resource->flags = type;
66 * Don't let the minimum size exceed what we
67 * can put in the resource.
69 if ((min_size - 1) > resource->limit)
70 min_size = resource->limit + 1;
72 resource->size = min_size;
77 static void cardbus_size_bridge_resource(device_t dev, unsigned int index)
79 struct resource *resource;
82 resource = find_resource(dev, index);
84 min_size = resource->size;
86 * Always allocate at least the miniumum size to a
87 * cardbus bridge in case a new card is plugged in.
89 if (resource->size < min_size)
90 resource->size = min_size;
94 void cardbus_read_resources(device_t dev)
96 resource_t moving_base, moving_limit, moving;
100 /* See if needs a card control registers base address. */
102 pci_get_resource(dev, PCI_BASE_ADDRESS_0);
104 compact_resources(dev);
106 /* See which bridge I/O resources are implemented. */
107 moving_base = pci_moving_config32(dev, PCI_CB_IO_BASE_0);
108 moving_limit = pci_moving_config32(dev, PCI_CB_IO_LIMIT_0);
109 moving = moving_base & moving_limit;
111 /* Initialize the I/O space constraints on the current bus. */
112 cardbus_record_bridge_resource(dev, moving, CARDBUS_IO_SIZE,
113 PCI_CB_IO_BASE_0, IORESOURCE_IO);
114 cardbus_size_bridge_resource(dev, PCI_CB_IO_BASE_0);
116 /* See which bridge I/O resources are implemented. */
117 moving_base = pci_moving_config32(dev, PCI_CB_IO_BASE_1);
118 moving_limit = pci_moving_config32(dev, PCI_CB_IO_LIMIT_1);
119 moving = moving_base & moving_limit;
121 /* Initialize the I/O space constraints on the current bus. */
122 cardbus_record_bridge_resource(dev, moving, CARDBUS_IO_SIZE,
123 PCI_CB_IO_BASE_1, IORESOURCE_IO);
125 /* If I can, enable prefetch for mem0. */
126 ctl = pci_read_config16(dev, PCI_CB_BRIDGE_CONTROL);
127 ctl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
128 ctl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
129 ctl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
130 pci_write_config16(dev, PCI_CB_BRIDGE_CONTROL, ctl);
131 ctl = pci_read_config16(dev, PCI_CB_BRIDGE_CONTROL);
133 /* See which bridge memory resources are implemented. */
134 moving_base = pci_moving_config32(dev, PCI_CB_MEMORY_BASE_0);
135 moving_limit = pci_moving_config32(dev, PCI_CB_MEMORY_LIMIT_0);
136 moving = moving_base & moving_limit;
138 /* Initialize the memory space constraints on the current bus. */
139 type = IORESOURCE_MEM;
140 if (ctl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)
141 type |= IORESOURCE_PREFETCH;
142 cardbus_record_bridge_resource(dev, moving, CARDBUS_MEM_SIZE,
143 PCI_CB_MEMORY_BASE_0, type);
144 if (type & IORESOURCE_PREFETCH)
145 cardbus_size_bridge_resource(dev, PCI_CB_MEMORY_BASE_0);
147 /* See which bridge memory resources are implemented. */
148 moving_base = pci_moving_config32(dev, PCI_CB_MEMORY_BASE_1);
149 moving_limit = pci_moving_config32(dev, PCI_CB_MEMORY_LIMIT_1);
150 moving = moving_base & moving_limit;
152 /* Initialize the memory space constraints on the current bus. */
153 cardbus_record_bridge_resource(dev, moving, CARDBUS_MEM_SIZE,
154 PCI_CB_MEMORY_BASE_1, IORESOURCE_MEM);
155 cardbus_size_bridge_resource(dev, PCI_CB_MEMORY_BASE_1);
157 compact_resources(dev);
160 void cardbus_enable_resources(device_t dev)
164 ctrl = pci_read_config16(dev, PCI_CB_BRIDGE_CONTROL);
165 ctrl |= (dev->link_list->bridge_ctrl & (
166 PCI_BRIDGE_CTL_PARITY |
167 PCI_BRIDGE_CTL_SERR |
168 PCI_BRIDGE_CTL_NO_ISA |
170 PCI_BRIDGE_CTL_MASTER_ABORT |
171 PCI_BRIDGE_CTL_BUS_RESET));
173 ctrl |= (PCI_CB_BRIDGE_CTL_PARITY + PCI_CB_BRIDGE_CTL_SERR);
174 printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
175 pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
177 pci_dev_enable_resources(dev);
180 struct device_operations default_cardbus_ops_bus = {
181 .read_resources = cardbus_read_resources,
182 .set_resources = pci_dev_set_resources,
183 .enable_resources = cardbus_enable_resources,
185 .scan_bus = pci_scan_bridge,
187 .reset_bus = pci_bus_reset,