2 * This file is part of the coreboot project.
4 * Copyright (C) 2008-2010 coresystems GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 // Make sure no stage 2 code is included:
25 #if !defined(CONFIG_NORTHBRIDGE_AMD_AMDK8) && !defined(CONFIG_NORTHBRIDGE_AMD_FAM10)
27 // FIXME: Is this piece of code southbridge specific, or
28 // can it be cleaned up so this include is not required?
29 // It's needed right now because we get our DEFAULT_PMBASE from
31 #if defined(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)
32 #include "../../../southbridge/intel/i82801gx/i82801gx.h"
33 #elif defined(CONFIG_SOUTHBRIDGE_INTEL_I82801DX)
34 #include "../../../southbridge/intel/i82801dx/i82801dx.h"
35 #elif defined(CONFIG_SOUTHBRIDGE_INTEL_SCH)
36 #include "../../../southbridge/intel/sch/sch.h"
38 #error "Southbridge needs SMM handler support."
41 #define LAPIC_ID 0xfee00020
43 .global smm_relocation_start
44 .global smm_relocation_end
46 /* initially SMM is some sort of real mode. */
50 * This trampoline code relocates SMBASE to 0xa0000 - ( lapicid * 0x400 )
52 * Why 0x400? It is a safe value to cover the save state area per CPU. On
53 * current AMD CPUs this area is _documented_ to be 0x200 bytes. On Intel
54 * Core 2 CPUs the _documented_ parts of the save state area is 48 bytes
55 * bigger, effectively sizing our data structures 0x300 bytes.
57 * LAPICID SMBASE SMM Entry SAVE STATE
58 * 0 0xa0000 0xa8000 0xafd00
59 * 1 0x9fc00 0xa7c00 0xaf900
60 * 2 0x9f800 0xa7800 0xaf500
61 * 3 0x9f400 0xa7400 0xaf100
62 * 4 0x9f000 0xa7000 0xaed00
63 * 5 0x9ec00 0xa6c00 0xae900
64 * 6 0x9e800 0xa6800 0xae500
65 * 7 0x9e400 0xa6400 0xae100
66 * 8 0x9e000 0xa6000 0xadd00
67 * 9 0x9dc00 0xa5c00 0xad900
68 * 10 0x9d800 0xa5800 0xad500
69 * 11 0x9d400 0xa5400 0xad100
70 * 12 0x9d000 0xa5000 0xacd00
71 * 13 0x9cc00 0xa4c00 0xac900
72 * 14 0x9c800 0xa4800 0xac500
73 * 15 0x9c400 0xa4400 0xac100
77 * 31 0x98400 0xa0400 0xa8100
79 * With 32 cores, the SMM handler would need to fit between
80 * 0xa0000-0xa0400 and the stub plus stack would need to go
81 * at 0xa8000-0xa8100 (example for core 0). That is not enough.
83 * This means we're basically limited to 16 cpu cores before
84 * we need to use the TSEG/HSEG for the actual SMM handler plus stack.
85 * When we exceed 32 cores, we also need to put SMBASE to TSEG/HSEG.
87 * If we figure out the documented values above are safe to use,
88 * we could pack the structure above even more, so we could use the
89 * scheme to pack save state areas for 63 AMD CPUs or 58 Intel CPUs
92 * Note: Some versions of Pentium M need their SMBASE aligned to 32k.
93 * On those the above only works for up to 2 cores. But for now we only
94 * care fore Core (2) Duo/Solo
99 /* Check revision to see if AMD64 style SMM_BASE
100 * Intel Core Solo/Duo: 0x30007
101 * Intel Core2 Solo/Duo: 0x30100
103 * This check does not make much sense, unless someone ports
104 * SMI handling to AMD64 CPUs.
107 mov $0x38000 + 0x7efc, %ebx
108 addr32 mov (%ebx), %al
112 mov $0x38000 + 0x7ef8, %ebx
115 mov $0x38000 + 0x7f00, %ebx
118 /* Get this CPU's LAPIC ID */
120 addr32 movl (%esi), %ecx
123 /* calculate offset by multiplying the
124 * apic ID by 1024 (0x400)
130 subl %edx, %eax /* subtract offset, see above */
132 addr32 movl %eax, (%ebx)
135 /* The next section of code is potentially southbridge specific */
137 /* Clear SMI status */
138 movw $(DEFAULT_PMBASE + 0x34), %dx
142 /* Clear PM1 status */
143 movw $(DEFAULT_PMBASE + 0x00), %dx
147 /* Set EOS bit so other SMIs can occur */
148 movw $(DEFAULT_PMBASE + 0x30), %dx
153 /* End of southbridge specific section. */
155 #if defined(CONFIG_DEBUG_SMM_RELOCATION) && CONFIG_DEBUG_SMM_RELOCATION
156 /* print [SMM-x] so we can determine if CPUx went to SMM */
157 movw $CONFIG_TTYS0_BASE, %dx
167 /* calculate ascii of cpu number. More than 9 cores? -> FIXME */
179 /* That's it. return */