2 * This file is part of the coreboot project.
4 * Copyright (C) 2008-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
23 #include <arch/romcc_io.h>
24 #include <console/console.h>
25 #include <cpu/x86/cache.h>
26 #include <cpu/x86/smm.h>
28 typedef enum { SMI_LOCKED, SMI_UNLOCKED } smi_semaphore;
30 /* SMI multiprocessing semaphore */
31 static volatile smi_semaphore smi_handler_status = SMI_UNLOCKED;
33 static int smi_obtain_lock(void)
41 : "=g" (ret), "=m" (smi_handler_status)
46 return (ret == SMI_UNLOCKED);
49 void smi_release_lock(void)
54 : "=m" (smi_handler_status)
60 #define LAPIC_ID 0xfee00020
61 static inline __attribute__((always_inline)) unsigned long nodeid(void)
63 return (*((volatile unsigned long *)(LAPIC_ID)) >> 24);
66 void io_trap_handler(int smif)
68 /* If a handler function handled a given IO trap, it
69 * shall return a non-zero value
71 printk(BIOS_DEBUG, "SMI function trap 0x%x: ", smif);
73 if (southbridge_io_trap_handler(smif))
76 if (mainboard_io_trap_handler(smif))
79 printk(BIOS_DEBUG, "Unknown function\n");
83 * @brief Set the EOS bit
85 static void smi_set_eos(void)
87 southbridge_smi_set_eos();
93 * @brief Backup PCI address to make sure we do not mess up the OS
95 static void smi_backup_pci_address(void)
97 pci_orig = inl(0xcf8);
101 * @brief Restore PCI address previously backed up
103 static void smi_restore_pci_address(void)
105 outl(pci_orig, 0xcf8);
109 * @brief Interrupt handler for SMI#
111 * @param smm_revision revision of the smm state save map
114 void smi_handler(u32 smm_revision)
117 smm_state_save_area_t state_save;
119 /* Are we ok to execute the handler? */
120 if (!smi_obtain_lock()) {
121 /* For security reasons we don't release the other CPUs
122 * until the CPU with the lock is actually done
124 while (smi_handler_status == SMI_LOCKED) /* wait */ ;
128 smi_backup_pci_address();
134 printk(BIOS_SPEW, "\nSMI# #%d\n", node);
136 switch (smm_revision) {
139 state_save.type = LEGACY;
140 state_save.legacy_state_save = (legacy_smm_state_save_area_t *)
141 (0xa8000 + 0x7e00 - (node * 0x400));
144 state_save.type = EM64T;
145 state_save.em64t_state_save = (em64t_smm_state_save_area_t *)
146 (0xa8000 + 0x7d00 - (node * 0x400));
149 state_save.type = AMD64;
150 state_save.amd64_state_save = (amd64_smm_state_save_area_t *)
151 (0xa8000 + 0x7e00 - (node * 0x400));
154 printk(BIOS_DEBUG, "smm_revision: 0x%08x\n", smm_revision);
155 printk(BIOS_DEBUG, "SMI# not supported on your CPU\n");
156 /* Don't release lock, so no further SMI will happen,
157 * if we don't handle it anyways.
162 /* Call chipset specific SMI handlers. */
164 cpu_smi_handler(node, &state_save);
165 if (northbridge_smi_handler)
166 northbridge_smi_handler(node, &state_save);
167 if (southbridge_smi_handler)
168 southbridge_smi_handler(node, &state_save);
170 smi_restore_pci_address();
174 /* De-assert SMI# signal to allow another SMI */