src/cpu/x86/smm/smihandler.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  * Copyright (C) 2008-2009 coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; version 2 of
   9  * the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  19  * MA 02110-1301 USA
  20  */
  21
  22 #include <arch/io.h>
  23 #include <arch/romcc_io.h>
  24 #include <console/console.h>
  25 #include <cpu/x86/cache.h>
  26 #include <cpu/x86/smm.h>
  27
  28 typedef enum { SMI_LOCKED, SMI_UNLOCKED } smi_semaphore;
  29
  30 /* SMI multiprocessing semaphore */
  31 static volatile smi_semaphore smi_handler_status __attribute__ ((aligned (4)))  = SMI_UNLOCKED;
  32
  33 static int smi_obtain_lock(void)
  34 {
  35         u8 ret = SMI_LOCKED;
  36
  37         asm volatile (
  38                 "movb %2, %%al\n"
  39                 "xchgb %%al, %1\n"
  40                 "movb %%al, %0\n"
  41                 : "=g" (ret), "=m" (smi_handler_status)
  42                 : "g" (SMI_LOCKED)
  43                 : "eax"
  44         );
  45
  46         return (ret == SMI_UNLOCKED);
  47 }
  48
  49 void smi_release_lock(void)
  50 {
  51         asm volatile (
  52                 "movb %1, %%al\n"
  53                 "xchgb %%al, %0\n"
  54                 : "=m" (smi_handler_status)
  55                 : "g" (SMI_UNLOCKED)
  56                 : "eax"
  57         );
  58 }
  59
  60 #define LAPIC_ID 0xfee00020
  61 static inline __attribute__((always_inline)) unsigned long nodeid(void)
  62 {
  63         return (*((volatile unsigned long *)(LAPIC_ID)) >> 24);
  64 }
  65
  66 void io_trap_handler(int smif)
  67 {
  68         /* If a handler function handled a given IO trap, it
  69          * shall return a non-zero value
  70          */
  71         printk(BIOS_DEBUG, "SMI function trap 0x%x: ", smif);
  72
  73         if (southbridge_io_trap_handler(smif))
  74                 return;
  75
  76         if (mainboard_io_trap_handler(smif))
  77                 return;
  78
  79         printk(BIOS_DEBUG, "Unknown function\n");
  80 }
  81
  82 /**
  83  * @brief Set the EOS bit
  84  */
  85 static void smi_set_eos(void)
  86 {
  87         southbridge_smi_set_eos();
  88 }
  89
  90 static u32 pci_orig;
  91
  92 /**
  93  * @brief Backup PCI address to make sure we do not mess up the OS
  94  */
  95 static void smi_backup_pci_address(void)
  96 {
  97         pci_orig = inl(0xcf8);
  98 }
  99
 100 /**
 101  * @brief Restore PCI address previously backed up
 102  */
 103 static void smi_restore_pci_address(void)
 104 {
 105         outl(pci_orig, 0xcf8);
 106 }
 107
 108 /**
 109  * @brief Interrupt handler for SMI#
 110  *
 111  * @param smm_revision revision of the smm state save map
 112  */
 113
 114 void smi_handler(u32 smm_revision)
 115 {
 116         unsigned int node;
 117         smm_state_save_area_t state_save;
 118
 119         /* Are we ok to execute the handler? */
 120         if (!smi_obtain_lock()) {
 121                 /* For security reasons we don't release the other CPUs
 122                  * until the CPU with the lock is actually done
 123                  */
 124                 while (smi_handler_status == SMI_LOCKED) {
 125                         asm volatile (
 126                                 ".byte 0xf3, 0x90\n"  /* hint a CPU we are in spinlock (PAUSE instruction, REP NOP) */
 127                         );
 128                 }
 129                 return;
 130         }
 131
 132         smi_backup_pci_address();
 133
 134         node=nodeid();
 135
 136         console_init();
 137
 138         printk(BIOS_SPEW, "\nSMI# #%d\n", node);
 139
 140         switch (smm_revision) {
 141         case 0x00030002:
 142         case 0x00030007:
 143                 state_save.type = LEGACY;
 144                 state_save.legacy_state_save = (legacy_smm_state_save_area_t *)
 145                         (0xa8000 + 0x7e00 - (node * 0x400));
 146                 break;
 147         case 0x00030100:
 148                 state_save.type = EM64T;
 149                 state_save.em64t_state_save = (em64t_smm_state_save_area_t *)
 150                         (0xa8000 + 0x7d00 - (node * 0x400));
 151                 break;
 152         case 0x00030064:
 153                 state_save.type = AMD64;
 154                 state_save.amd64_state_save = (amd64_smm_state_save_area_t *)
 155                         (0xa8000 + 0x7e00 - (node * 0x400));
 156                 break;
 157         default:
 158                 printk(BIOS_DEBUG, "smm_revision: 0x%08x\n", smm_revision);
 159                 printk(BIOS_DEBUG, "SMI# not supported on your CPU\n");
 160                 /* Don't release lock, so no further SMI will happen,
 161                  * if we don't handle it anyways.
 162                  */
 163                 return;
 164         }
 165
 166         /* Call chipset specific SMI handlers. */
 167         if (cpu_smi_handler)
 168                 cpu_smi_handler(node, &state_save);
 169         if (northbridge_smi_handler)
 170                 northbridge_smi_handler(node, &state_save);
 171         if (southbridge_smi_handler)
 172                 southbridge_smi_handler(node, &state_save);
 173
 174         smi_restore_pci_address();
 175
 176         smi_release_lock();
 177
 178         /* De-assert SMI# signal to allow another SMI */
 179         smi_set_eos();
 180 }