2 * This file is part of the coreboot project.
4 * Copyright (C) 2008 coresystems GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
23 #include <arch/romcc_io.h>
24 #include <console/console.h>
25 #include <cpu/x86/cache.h>
26 #include <cpu/x86/smm.h>
28 void southbridge_smi_set_eos(void);
32 typedef enum { SMI_LOCKED, SMI_UNLOCKED } smi_semaphore;
34 /* SMI multiprocessing semaphore */
35 static volatile smi_semaphore smi_handler_status = SMI_UNLOCKED;
37 static int smi_obtain_lock(void)
45 : "=g" (ret), "=m" (smi_handler_status)
50 return (ret == SMI_UNLOCKED);
53 static void smi_release_lock(void)
58 : "=m" (smi_handler_status)
64 #define LAPIC_ID 0xfee00020
65 static inline __attribute__((always_inline)) unsigned long nodeid(void)
67 return (*((volatile unsigned long *)(LAPIC_ID)) >> 24);
70 /* ********************* smi_util ************************* */
90 static int uart_can_tx_byte(void)
92 return inb(TTYS0_BASE + UART_LSR) & 0x20;
95 static void uart_wait_to_tx_byte(void)
97 while(!uart_can_tx_byte())
101 static void uart_wait_until_sent(void)
103 while(!(inb(TTYS0_BASE + UART_LSR) & 0x40))
107 static void uart_tx_byte(unsigned char data)
109 uart_wait_to_tx_byte();
110 outb(data, TTYS0_BASE + UART_TBR);
111 /* Make certain the data clears the fifos */
112 uart_wait_until_sent();
115 void console_tx_flush(void)
117 uart_wait_to_tx_byte();
120 void console_tx_byte(unsigned char byte)
127 /* ********************* smi_util ************************* */
130 void io_trap_handler(int smif)
132 /* If a handler function handled a given IO trap, it
133 * shall return a non-zero value
135 printk_debug("SMI function trap 0x%x: ", smif);
137 if (southbridge_io_trap_handler(smif))
140 if (mainboard_io_trap_handler(smif))
143 printk_debug("Unknown function\n");
147 * @brief Set the EOS bit
149 static void smi_set_eos(void)
151 southbridge_smi_set_eos();
155 * @brief Interrupt handler for SMI#
157 * @param smm_revision revision of the smm state save map
160 void smi_handler(u32 smm_revision)
163 smm_state_save_area_t state_save;
165 /* Are we ok to execute the handler? */
166 if (!smi_obtain_lock())
172 console_loglevel = DEFAULT_CONSOLE_LOGLEVEL;
174 console_loglevel = 1;
177 printk_debug("\nSMI# #%d\n", node);
179 switch (smm_revision) {
181 state_save.type = LEGACY;
182 state_save.legacy_state_save = (legacy_smm_state_save_area_t *)
183 (0xa8000 + 0x7e00 - (node * 0x400));
186 state_save.type = EM64T;
187 state_save.em64t_state_save = (em64t_smm_state_save_area_t *)
188 (0xa8000 + 0x7d00 - (node * 0x400));
191 state_save.type = AMD64;
192 state_save.amd64_state_save = (amd64_smm_state_save_area_t *)
193 (0xa8000 + 0x7e00 - (node * 0x400));
196 printk_debug("smm_revision: 0x%08x\n", smm_revision);
197 printk_debug("SMI# not supported on your CPU\n");
198 /* Don't release lock, so no further SMI will happen,
199 * if we don't handle it anyways.
204 southbridge_smi_handler(node, &state_save);
208 /* De-assert SMI# signal to allow another SMI */