2 * intel_mtrr.c: setting MTRR to decent values for cache initialization on P6
4 * Derived from intel_set_mtrr in intel_subr.c and mtrr.c in linux kernel
6 * Copyright 2000 Silicon Integrated System Corporation
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 * Reference: Intel Architecture Software Developer's Manual, Volume 3: System Programming
26 #include <console/console.h>
27 #include <device/device.h>
28 #include <cpu/x86/msr.h>
29 #include <cpu/x86/mtrr.h>
30 #include <cpu/x86/cache.h>
32 #define arraysize(x) (sizeof(x)/sizeof((x)[0]))
34 #warning "FIXME I do not properly handle address more than 36 physical address bits"
36 # define ADDRESS_BITS 40
38 # define ADDRESS_BITS 36
40 #define ADDRESS_BITS_HIGH (ADDRESS_BITS - 32)
41 #define ADDRESS_MASK_HIGH ((1u << ADDRESS_BITS_HIGH) - 1)
43 static unsigned int mtrr_msr[] = {
44 MTRRfix64K_00000_MSR, MTRRfix16K_80000_MSR, MTRRfix16K_A0000_MSR,
45 MTRRfix4K_C0000_MSR, MTRRfix4K_C8000_MSR, MTRRfix4K_D0000_MSR, MTRRfix4K_D8000_MSR,
46 MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR,
50 static void enable_fixed_mtrr(void)
54 msr = rdmsr(MTRRdefType_MSR);
56 wrmsr(MTRRdefType_MSR, msr);
59 static void enable_var_mtrr(void)
63 msr = rdmsr(MTRRdefType_MSR);
65 wrmsr(MTRRdefType_MSR, msr);
68 /* setting variable mtrr, comes from linux kernel source */
69 static void set_var_mtrr(unsigned int reg, unsigned long basek, unsigned long sizek, unsigned char type)
73 base.hi = basek >> 22;
74 base.lo = basek << 10;
76 //printk_debug("ADDRESS_MASK_HIGH=%#x\n", ADDRESS_MASK_HIGH);
78 if (sizek < 4*1024*1024) {
79 mask.hi = ADDRESS_MASK_HIGH;
80 mask.lo = ~((sizek << 10) -1);
83 mask.hi = ADDRESS_MASK_HIGH & (~((sizek >> 22) -1));
90 // it is recommended that we disable and enable cache when we
95 zero.lo = zero.hi = 0;
96 /* The invalid bit is kept in the mask, so we simply clear the
97 relevant mask register to disable a range. */
98 wrmsr (MTRRphysMask_MSR(reg), zero);
100 /* Bit 32-35 of MTRRphysMask should be set to 1 */
103 wrmsr (MTRRphysBase_MSR(reg), base);
104 wrmsr (MTRRphysMask_MSR(reg), mask);
109 /* fms: find most sigificant bit set, stolen from Linux Kernel Source. */
110 static inline unsigned int fms(unsigned int x)
114 __asm__("bsrl %1,%0\n\t"
117 "1:" : "=r" (r) : "g" (x));
121 /* fms: find least sigificant bit set */
122 static inline unsigned int fls(unsigned int x)
126 __asm__("bsfl %1,%0\n\t"
129 "1:" : "=r" (r) : "g" (x));
133 /* setting up variable and fixed mtrr
135 * From Intel Vol. III Section 9.12.4, the Range Size and Base Alignment has some kind of requirement:
136 * 1. The range size must be 2^N byte for N >= 12 (i.e 4KB minimum).
137 * 2. The base address must be 2^N aligned, where the N here is equal to the N in previous
138 * requirement. So a 8K range must be 8K aligned not 4K aligned.
140 * These requirement is meet by "decompositing" the ramsize into Sum(Cn * 2^n, n = [0..N], Cn = [0, 1]).
141 * For Cm = 1, there is a WB range of 2^m size at base address Sum(Cm * 2^m, m = [N..n]).
142 * A 124MB (128MB - 4MB SMA) example:
143 * ramsize = 124MB == 64MB (at 0MB) + 32MB (at 64MB) + 16MB (at 96MB ) + 8MB (at 112MB) + 4MB (120MB).
144 * But this wastes a lot of MTRR registers so we use another more "aggresive" way with Uncacheable Regions.
146 * In the Uncacheable Region scheme, we try to cover the whole ramsize by one WB region as possible,
147 * If (an only if) this can not be done we will try to decomposite the ramesize, the mathematical formula
148 * whould be ramsize = Sum(Cn * 2^n, n = [0..N], Cn = [-1, 0, 1]). For Cn = -1, a Uncachable Region is used.
149 * The same 124MB example:
150 * ramsize = 124MB == 128MB WB (at 0MB) + 4MB UC (at 124MB)
151 * or a 156MB (128MB + 32MB - 4MB SMA) example:
152 * ramsize = 156MB == 128MB WB (at 0MB) + 32MB WB (at 128MB) + 4MB UC (at 156MB)
154 /* 2 MTRRS are reserved for the operating system */
162 #define MTRRS (BIOS_MTRRS + OS_MTRRS)
165 static void set_fixed_mtrrs(unsigned int first, unsigned int last, unsigned char type)
168 unsigned int fixed_msr = NUM_FIXED_RANGES >> 3;
170 msr.lo = msr.hi = 0; /* Shut up gcc */
171 for(i = first; i < last; i++) {
172 /* When I switch to a new msr read it in */
173 if (fixed_msr != i >> 3) {
174 /* But first write out the old msr */
175 if (fixed_msr < (NUM_FIXED_RANGES >> 3)) {
177 wrmsr(mtrr_msr[fixed_msr], msr);
181 msr = rdmsr(mtrr_msr[fixed_msr]);
184 msr.lo &= ~(0xff << ((i&3)*8));
185 msr.lo |= type << ((i&3)*8);
187 msr.hi &= ~(0xff << ((i&3)*8));
188 msr.hi |= type << ((i&3)*8);
191 /* Write out the final msr */
192 if (fixed_msr < (NUM_FIXED_RANGES >> 3)) {
194 wrmsr(mtrr_msr[fixed_msr], msr);
199 static unsigned fixed_mtrr_index(unsigned long addrk)
202 index = (addrk - 0) >> 6;
204 index = ((addrk - 8*64) >> 4) + 8;
207 index = ((addrk - (8*64 + 16*16)) >> 2) + 24;
209 if (index > NUM_FIXED_RANGES) {
210 index = NUM_FIXED_RANGES;
215 static unsigned int range_to_mtrr(unsigned int reg,
216 unsigned long range_startk, unsigned long range_sizek,
217 unsigned long next_range_startk)
219 if (!range_sizek || (reg >= BIOS_MTRRS)) {
223 unsigned long max_align, align;
225 /* Compute the maximum size I can make a range */
226 max_align = fls(range_startk);
227 align = fms(range_sizek);
228 if (align > max_align) {
232 printk_debug("Setting variable MTRR %d, base: %4dMB, range: %4dMB, type WB\n",
233 reg, range_startk >>10, sizek >> 10);
234 set_var_mtrr(reg++, range_startk, sizek, MTRR_TYPE_WRBACK);
235 range_startk += sizek;
236 range_sizek -= sizek;
237 if (reg >= BIOS_MTRRS)
243 static unsigned long resk(uint64_t value)
245 unsigned long resultk;
246 if (value < (1ULL << 42)) {
247 resultk = value >> 10;
250 resultk = 0xffffffff;
255 void x86_setup_mtrrs(void)
257 /* Try this the simple way of incrementally adding together
258 * mtrrs. If this doesn't work out we can get smart again
259 * and clear out the mtrrs.
262 unsigned long range_startk, range_sizek;
266 /* Initialized the fixed_mtrrs to uncached */
267 printk_debug("Setting fixed MTRRs(%d-%d) type: UC\n",
268 0, NUM_FIXED_RANGES);
269 set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHEABLE);
271 /* Now see which of the fixed mtrrs cover ram.
273 for(dev = all_devices; dev; dev = dev->next) {
274 struct resource *res, *last;
275 last = &dev->resource[dev->resources];
276 for(res = &dev->resource[0]; res < last; res++) {
277 unsigned int start_mtrr;
278 unsigned int last_mtrr;
279 if (!(res->flags & IORESOURCE_MEM) ||
280 !(res->flags & IORESOURCE_CACHEABLE))
284 start_mtrr = fixed_mtrr_index(resk(res->base));
285 last_mtrr = fixed_mtrr_index(resk((res->base + res->size)));
286 if (start_mtrr >= NUM_FIXED_RANGES) {
289 printk_debug("Setting fixed MTRRs(%d-%d) Type: WB\n",
290 start_mtrr, last_mtrr);
291 set_fixed_mtrrs(start_mtrr, last_mtrr, MTRR_TYPE_WRBACK);
294 printk_debug("DONE fixed MTRRs\n");
295 /* Cache as many memory areas as possible */
296 /* FIXME is there an algorithm for computing the optimal set of mtrrs?
297 * In some cases it is definitely possible to do better.
302 for(dev = all_devices; dev; dev = dev->next) {
303 struct resource *res, *last;
304 last = &dev->resource[dev->resources];
305 for(res = &dev->resource[0]; res < last; res++) {
306 unsigned long basek, sizek;
307 if (!(res->flags & IORESOURCE_MEM) ||
308 !(res->flags & IORESOURCE_CACHEABLE)) {
311 basek = resk(res->base);
312 sizek = resk(res->size);
313 /* See if I can merge with the last range
314 * Either I am below 1M and the fixed mtrrs handle it, or
317 if ((basek <= 1024) || (range_startk + range_sizek == basek)) {
318 unsigned long endk = basek + sizek;
319 range_sizek = endk - range_startk;
322 /* Write the range mtrrs */
323 if (range_sizek != 0) {
324 reg = range_to_mtrr(reg, range_startk, range_sizek, basek);
327 if (reg >= BIOS_MTRRS)
330 /* Allocate an msr */
331 range_startk = basek;
336 /* Write the last range */
337 reg = range_to_mtrr(reg, range_startk, range_sizek, 0);
338 printk_debug("DONE variable MTRRs\n");
339 printk_debug("Clear out the extra MTRR's\n");
340 /* Clear out the extra MTRR's */
342 set_var_mtrr(reg++, 0, 0, 0);
344 /* enable fixed MTRR */
345 printk_spew("call enable_fixed_mtrr()\n");
347 printk_spew("call enable_var_mtrr()\n");
349 printk_spew("Leave %s\n", __FUNCTION__);
353 int x86_mtrr_check(void)
355 /* Only Pentium Pro and later have MTRR */
357 printk_debug("\nMTRR check\n");
362 printk_debug("Fixed MTRRs : ");
364 printk_debug("Enabled\n");
366 printk_debug("Disabled\n");
368 printk_debug("Variable MTRRs: ");
370 printk_debug("Enabled\n");
372 printk_debug("Disabled\n");
377 return ((int) msr.lo);