2 * mtrr.c: setting MTRR to decent values for cache initialization on P6
4 * Derived from intel_set_mtrr in intel_subr.c and mtrr.c in linux kernel
6 * Copyright 2000 Silicon Integrated System Corporation
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 * Reference: Intel Architecture Software Developer's Manual, Volume 3: System Programming
27 2005.1 yhlu add NC support to spare mtrrs for 64G memory above installed
28 2005.6 Eric add address bit in x86_setup_mtrrs
29 2005.6 yhlu split x86_setup_var_mtrrs and x86_setup_fixed_mtrrs,
30 for AMD, it will not use x86_setup_fixed_mtrrs
34 #include <console/console.h>
35 #include <device/device.h>
36 #include <cpu/x86/msr.h>
37 #include <cpu/x86/mtrr.h>
38 #include <cpu/x86/cache.h>
40 static unsigned int mtrr_msr[] = {
41 MTRRfix64K_00000_MSR, MTRRfix16K_80000_MSR, MTRRfix16K_A0000_MSR,
42 MTRRfix4K_C0000_MSR, MTRRfix4K_C8000_MSR, MTRRfix4K_D0000_MSR, MTRRfix4K_D8000_MSR,
43 MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR,
47 void enable_fixed_mtrr(void)
51 msr = rdmsr(MTRRdefType_MSR);
53 wrmsr(MTRRdefType_MSR, msr);
56 static void enable_var_mtrr(void)
60 msr = rdmsr(MTRRdefType_MSR);
62 wrmsr(MTRRdefType_MSR, msr);
65 /* setting variable mtrr, comes from linux kernel source */
66 static void set_var_mtrr(
67 unsigned int reg, unsigned long basek, unsigned long sizek,
68 unsigned char type, unsigned address_bits)
71 unsigned address_mask_high;
76 // it is recommended that we disable and enable cache when we
82 zero.lo = zero.hi = 0;
83 /* The invalid bit is kept in the mask, so we simply clear the
84 relevant mask register to disable a range. */
85 wrmsr (MTRRphysMask_MSR(reg), zero);
92 address_mask_high = ((1u << (address_bits - 32u)) - 1u);
94 base.hi = basek >> 22;
95 base.lo = basek << 10;
97 printk_spew("ADDRESS_MASK_HIGH=%#x\n", address_mask_high);
99 if (sizek < 4*1024*1024) {
100 mask.hi = address_mask_high;
101 mask.lo = ~((sizek << 10) -1);
104 mask.hi = address_mask_high & (~((sizek >> 22) -1));
108 // it is recommended that we disable and enable cache when we
112 /* Bit 32-35 of MTRRphysMask should be set to 1 */
115 wrmsr (MTRRphysBase_MSR(reg), base);
116 wrmsr (MTRRphysMask_MSR(reg), mask);
121 /* fms: find most sigificant bit set, stolen from Linux Kernel Source. */
122 static inline unsigned int fms(unsigned int x)
126 __asm__("bsrl %1,%0\n\t"
129 "1:" : "=r" (r) : "g" (x));
133 /* fms: find least sigificant bit set */
134 static inline unsigned int fls(unsigned int x)
138 __asm__("bsfl %1,%0\n\t"
141 "1:" : "=r" (r) : "g" (x));
145 /* setting up variable and fixed mtrr
147 * From Intel Vol. III Section 9.12.4, the Range Size and Base Alignment has some kind of requirement:
148 * 1. The range size must be 2^N byte for N >= 12 (i.e 4KB minimum).
149 * 2. The base address must be 2^N aligned, where the N here is equal to the N in previous
150 * requirement. So a 8K range must be 8K aligned not 4K aligned.
152 * These requirement is meet by "decompositing" the ramsize into Sum(Cn * 2^n, n = [0..N], Cn = [0, 1]).
153 * For Cm = 1, there is a WB range of 2^m size at base address Sum(Cm * 2^m, m = [N..n]).
154 * A 124MB (128MB - 4MB SMA) example:
155 * ramsize = 124MB == 64MB (at 0MB) + 32MB (at 64MB) + 16MB (at 96MB ) + 8MB (at 112MB) + 4MB (120MB).
156 * But this wastes a lot of MTRR registers so we use another more "aggresive" way with Uncacheable Regions.
158 * In the Uncacheable Region scheme, we try to cover the whole ramsize by one WB region as possible,
159 * If (an only if) this can not be done we will try to decomposite the ramesize, the mathematical formula
160 * whould be ramsize = Sum(Cn * 2^n, n = [0..N], Cn = [-1, 0, 1]). For Cn = -1, a Uncachable Region is used.
161 * The same 124MB example:
162 * ramsize = 124MB == 128MB WB (at 0MB) + 4MB UC (at 124MB)
163 * or a 156MB (128MB + 32MB - 4MB SMA) example:
164 * ramsize = 156MB == 128MB WB (at 0MB) + 32MB WB (at 128MB) + 4MB UC (at 156MB)
166 /* 2 MTRRS are reserved for the operating system */
174 #define MTRRS (BIOS_MTRRS + OS_MTRRS)
177 static void set_fixed_mtrrs(unsigned int first, unsigned int last, unsigned char type)
180 unsigned int fixed_msr = NUM_FIXED_RANGES >> 3;
182 msr.lo = msr.hi = 0; /* Shut up gcc */
183 for(i = first; i < last; i++) {
184 /* When I switch to a new msr read it in */
185 if (fixed_msr != i >> 3) {
186 /* But first write out the old msr */
187 if (fixed_msr < (NUM_FIXED_RANGES >> 3)) {
189 wrmsr(mtrr_msr[fixed_msr], msr);
193 msr = rdmsr(mtrr_msr[fixed_msr]);
196 msr.lo &= ~(0xff << ((i&3)*8));
197 msr.lo |= type << ((i&3)*8);
199 msr.hi &= ~(0xff << ((i&3)*8));
200 msr.hi |= type << ((i&3)*8);
203 /* Write out the final msr */
204 if (fixed_msr < (NUM_FIXED_RANGES >> 3)) {
206 wrmsr(mtrr_msr[fixed_msr], msr);
211 static unsigned fixed_mtrr_index(unsigned long addrk)
214 index = (addrk - 0) >> 6;
216 index = ((addrk - 8*64) >> 4) + 8;
219 index = ((addrk - (8*64 + 16*16)) >> 2) + 24;
221 if (index > NUM_FIXED_RANGES) {
222 index = NUM_FIXED_RANGES;
227 static unsigned int range_to_mtrr(unsigned int reg,
228 unsigned long range_startk, unsigned long range_sizek,
229 unsigned long next_range_startk, unsigned char type, unsigned address_bits)
232 printk_debug("range_to_mtrr called for empty range\n");
235 if (reg >= BIOS_MTRRS) {
236 printk_err("Running out of variable MTRRs!\n");
240 unsigned long max_align, align;
242 /* Compute the maximum size I can make a range */
243 max_align = fls(range_startk);
244 align = fms(range_sizek);
245 if (align > max_align) {
249 printk_debug("Setting variable MTRR %d, base: %4ldMB, range: %4ldMB, type %s\n",
250 reg, range_startk >>10, sizek >> 10,
251 (type==MTRR_TYPE_UNCACHEABLE)?"UC":
252 ((type==MTRR_TYPE_WRBACK)?"WB":"Other")
254 set_var_mtrr(reg++, range_startk, sizek, type, address_bits);
255 range_startk += sizek;
256 range_sizek -= sizek;
257 if (reg >= BIOS_MTRRS) {
258 printk_err("Running out of variable MTRRs!\n");
265 static unsigned long resk(uint64_t value)
267 unsigned long resultk;
268 if (value < (1ULL << 42)) {
269 resultk = value >> 10;
272 resultk = 0xffffffff;
277 static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resource *res)
279 unsigned int start_mtrr;
280 unsigned int last_mtrr;
281 start_mtrr = fixed_mtrr_index(resk(res->base));
282 last_mtrr = fixed_mtrr_index(resk((res->base + res->size)));
283 if (start_mtrr >= NUM_FIXED_RANGES) {
286 printk_debug("Setting fixed MTRRs(%d-%d) Type: WB\n",
287 start_mtrr, last_mtrr);
288 set_fixed_mtrrs(start_mtrr, last_mtrr, MTRR_TYPE_WRBACK);
292 #ifndef CONFIG_VAR_MTRR_HOLE
293 #define CONFIG_VAR_MTRR_HOLE 1
296 struct var_mtrr_state {
297 unsigned long range_startk, range_sizek;
299 #if CONFIG_VAR_MTRR_HOLE
300 unsigned long hole_startk, hole_sizek;
302 unsigned address_bits;
305 void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res)
307 struct var_mtrr_state *state = gp;
308 unsigned long basek, sizek;
309 if (state->reg >= BIOS_MTRRS)
311 basek = resk(res->base);
312 sizek = resk(res->size);
313 /* See if I can merge with the last range
314 * Either I am below 1M and the fixed mtrrs handle it, or
317 if ((basek <= 1024) || (state->range_startk + state->range_sizek == basek)) {
318 unsigned long endk = basek + sizek;
319 state->range_sizek = endk - state->range_startk;
322 /* Write the range mtrrs */
323 if (state->range_sizek != 0) {
324 #if CONFIG_VAR_MTRR_HOLE
325 if (state->hole_sizek == 0) {
326 /* We need to put that on to hole */
327 unsigned long endk = basek + sizek;
328 state->hole_startk = state->range_startk + state->range_sizek;
329 state->hole_sizek = basek - state->hole_startk;
330 state->range_sizek = endk - state->range_startk;
334 state->reg = range_to_mtrr(state->reg, state->range_startk,
335 state->range_sizek, basek, MTRR_TYPE_WRBACK, state->address_bits);
336 #if CONFIG_VAR_MTRR_HOLE
337 state->reg = range_to_mtrr(state->reg, state->hole_startk,
338 state->hole_sizek, basek, MTRR_TYPE_UNCACHEABLE, state->address_bits);
340 state->range_startk = 0;
341 state->range_sizek = 0;
342 #if CONFIG_VAR_MTRR_HOLE
343 state->hole_startk = 0;
344 state->hole_sizek = 0;
347 /* Allocate an msr */
348 printk_spew(" Allocate an msr - basek = %08x, sizek = %08x,\n", basek, sizek);
349 state->range_startk = basek;
350 state->range_sizek = sizek;
353 void x86_setup_fixed_mtrrs(void)
355 /* Try this the simple way of incrementally adding together
356 * mtrrs. If this doesn't work out we can get smart again
357 * and clear out the mtrrs.
361 /* Initialized the fixed_mtrrs to uncached */
362 printk_debug("Setting fixed MTRRs(%d-%d) Type: UC\n",
363 0, NUM_FIXED_RANGES);
364 set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHEABLE);
366 /* Now see which of the fixed mtrrs cover ram.
368 search_global_resources(
369 IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
370 set_fixed_mtrr_resource, NULL);
371 printk_debug("DONE fixed MTRRs\n");
373 /* enable fixed MTRR */
374 printk_spew("call enable_fixed_mtrr()\n");
378 void x86_setup_var_mtrrs(unsigned address_bits)
379 /* this routine needs to know how many address bits a given processor
380 * supports. CPUs get grumpy when you set too many bits in
381 * their mtrr registers :( I would generically call cpuid here
382 * and find out how many physically supported but some cpus are
383 * buggy, and report more bits then they actually support.
386 /* Try this the simple way of incrementally adding together
387 * mtrrs. If this doesn't work out we can get smart again
388 * and clear out the mtrrs.
390 struct var_mtrr_state var_state;
392 /* Cache as many memory areas as possible */
393 /* FIXME is there an algorithm for computing the optimal set of mtrrs?
394 * In some cases it is definitely possible to do better.
396 var_state.range_startk = 0;
397 var_state.range_sizek = 0;
398 #if CONFIG_VAR_MTRR_HOLE
399 var_state.hole_startk = 0;
400 var_state.hole_sizek = 0;
403 var_state.address_bits = address_bits;
404 search_global_resources(
405 IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
406 set_var_mtrr_resource, &var_state);
408 /* Write the last range */
409 var_state.reg = range_to_mtrr(var_state.reg, var_state.range_startk,
410 var_state.range_sizek, 0, MTRR_TYPE_WRBACK, var_state.address_bits);
411 #if CONFIG_VAR_MTRR_HOLE
412 var_state.reg = range_to_mtrr(var_state.reg, var_state.hole_startk,
413 var_state.hole_sizek, 0, MTRR_TYPE_UNCACHEABLE, var_state.address_bits);
415 printk_debug("DONE variable MTRRs\n");
416 printk_debug("Clear out the extra MTRR's\n");
417 /* Clear out the extra MTRR's */
418 while(var_state.reg < MTRRS) {
419 set_var_mtrr(var_state.reg++, 0, 0, 0, var_state.address_bits);
421 printk_spew("call enable_var_mtrr()\n");
423 printk_spew("Leave %s\n", __FUNCTION__);
427 void x86_setup_mtrrs(unsigned address_bits)
429 x86_setup_fixed_mtrrs();
430 x86_setup_var_mtrrs(address_bits);
434 int x86_mtrr_check(void)
436 /* Only Pentium Pro and later have MTRR */
438 printk_debug("\nMTRR check\n");
443 printk_debug("Fixed MTRRs : ");
445 printk_debug("Enabled\n");
447 printk_debug("Disabled\n");
449 printk_debug("Variable MTRRs: ");
451 printk_debug("Enabled\n");
453 printk_debug("Disabled\n");
458 return ((int) msr.lo);