3 #include <cpu/x86/cache.h>
4 #include <cpu/x86/mtrr.h>
5 #include <cpu/x86/msr.h>
7 /* Validate XIP_ROM_SIZE and XIP_ROM_BASE */
8 #if defined(XIP_ROM_SIZE) && !defined(XIP_ROM_BASE)
9 #error "XIP_ROM_SIZE without XIP_ROM_BASE"
11 #if defined(XIP_ROM_BASE) && !defined(XIP_ROM_SIZE)
12 #error "XIP_ROM_BASE without XIP_ROM_SIZE"
14 #if !defined(CONFIG_LB_MEM_TOPK)
15 #error "CONFIG_LB_MEM_TOPK not defined"
18 #if defined(XIP_ROM_SIZE) && ((XIP_ROM_SIZE & (XIP_ROM_SIZE -1)) != 0)
19 #error "XIP_ROM_SIZE is not a power of 2"
21 #if defined(XIP_ROM_SIZE) && ((XIP_ROM_BASE % XIP_ROM_SIZE) != 0)
22 #error "XIP_ROM_BASE is not a multiple of XIP_ROM_SIZE"
25 #if (CONFIG_LB_MEM_TOPK & (CONFIG_LB_MEM_TOPK -1)) != 0
26 # error "CONFIG_LB_MEM_TOPK must be a power of 2"
29 static void disable_var_mtrr(unsigned reg)
31 /* The invalid bit is kept in the mask so we simply
32 * clear the relevent mask register to disable a
36 zero.lo = zero.hi = 0;
37 wrmsr(MTRRphysMask_MSR(reg), zero);
40 static void set_var_mtrr(
41 unsigned reg, unsigned base, unsigned size, unsigned type)
44 /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
46 basem.lo = base | type;
48 wrmsr(MTRRphysBase_MSR(reg), basem);
49 maskm.lo = ~(size - 1) | 0x800;
51 wrmsr(MTRRphysMask_MSR(reg), maskm);
54 static void cache_lbmem(int type)
56 /* Enable caching for 0 - 1MB using variable mtrr */
58 set_var_mtrr(0, 0x00000000, CONFIG_LB_MEM_TOPK << 10, type);
63 /* the fixed and variable MTTRs are power-up with random values,
64 * clear them to MTRR_TYPE_UNCACHEABLE for safty.
66 static void do_early_mtrr_init(const unsigned long *mtrr_msrs)
69 * The cache is not enabled in cr0 nor in MTRRdefType_MSR
70 * entry32.inc ensures the cache is not enabled in cr0
73 const unsigned long *msr_addr;
76 print_spew("Clearing mtrr\r\n");
78 /* Inialize all of the relevant msrs to 0 */
82 for(msr_addr = mtrr_msrs; (msr_nr = *msr_addr); msr_addr++) {
86 #if defined(XIP_ROM_SIZE)
87 /* enable write through caching so we can do execute in place
90 set_var_mtrr(1, XIP_ROM_BASE, XIP_ROM_SIZE, MTRR_TYPE_WRBACK);
93 /* Set the default memory type and enable fixed and variable MTRRs
95 /* Enable Variable MTRRs */
98 wrmsr(MTRRdefType_MSR, msr);
102 static void early_mtrr_init(void)
104 static const unsigned long mtrr_msrs[] = {
111 0x200, 0x201, 0x202, 0x203,
112 0x204, 0x205, 0x206, 0x207,
113 0x208, 0x209, 0x20A, 0x20B,
114 0x20C, 0x20D, 0x20E, 0x20F,
115 /* NULL end of table */
119 do_early_mtrr_init(mtrr_msrs);
123 #endif /* EARLYMTRR_C */