2 #include <arch/intel.h>
3 #include <cpu/x86/mtrr.h>
4 #include <cpu/x86/lapic_def.h>
6 .globl _secondary_start, _secondary_start_end
12 movl %eax, %cr3 /* Invalidate TLB*/
14 /* On hyper threaded cpus, invalidating the cache here is
15 * very very bad. Don't.
18 /* setup the data segment */
22 data32 lgdt gdtaddr - _secondary_start
25 andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */
26 orl $0x60000001, %eax /* CD, NW, PE = 1 */
39 /* Load the Interrupt descriptor table */
42 /* Set the stack pointer, and flag that we are done */
44 movl secondary_stack, %esp
45 movl %eax, secondary_stack
47 call secondary_cpu_init
52 .word gdt_limit /* the table limit */
53 .long gdt /* we know the offset */