src/cpu/x86/lapic/lapic_cpu_init.c

   1 #include <cpu/x86/lapic.h>
   2 #include <delay.h>
   3 #include <string.h>
   4 #include <console/console.h>
   5 #include <arch/hlt.h>
   6 #include <device/device.h>
   7 #include <device/path.h>
   8 #include <smp/atomic.h>
   9 #include <smp/spinlock.h>
  10 #include <cpu/cpu.h>
  11
  12
  13 #if CONFIG_SMP == 1
  14 /* This is a lot more paranoid now, since Linux can NOT handle
  15  * being told there is a CPU when none exists. So any errors
  16  * will return 0, meaning no CPU.
  17  *
  18  * We actually handling that case by noting which cpus startup
  19  * and not telling anyone about the ones that dont.
  20  */
  21 static int lapic_start_cpu(unsigned long apicid)
  22 {
  23         int timeout;
  24         unsigned long send_status, accept_status, start_eip;
  25         int j, num_starts, maxlvt;
  26         extern char _secondary_start[];
  27
  28         /*
  29          * Starting actual IPI sequence...
  30          */
  31
  32         printk_spew("Asserting INIT.\n");
  33
  34         /*
  35          * Turn INIT on target chip
  36          */
  37         lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
  38
  39         /*
  40          * Send IPI
  41          */
  42
  43         lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT
  44                                 | LAPIC_DM_INIT);
  45
  46         printk_spew("Waiting for send to finish...\n");
  47         timeout = 0;
  48         do {
  49                 printk_spew("+");
  50                 udelay(100);
  51                 send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
  52         } while (send_status && (timeout++ < 1000));
  53         if (timeout >= 1000) {
  54                 printk_err("CPU %d: First apic write timed out. Disabling\n",
  55                          apicid);
  56                 // too bad.
  57                 printk_err("ESR is 0x%x\n", lapic_read(LAPIC_ESR));
  58                 if (lapic_read(LAPIC_ESR)) {
  59                         printk_err("Try to reset ESR\n");
  60                         lapic_write_around(LAPIC_ESR, 0);
  61                         printk_err("ESR is 0x%x\n", lapic_read(LAPIC_ESR));
  62                 }
  63                 return 0;
  64         }
  65         mdelay(10);
  66
  67         printk_spew("Deasserting INIT.\n");
  68
  69         /* Target chip */
  70         lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
  71
  72         /* Send IPI */
  73         lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT);
  74
  75         printk_spew("Waiting for send to finish...\n");
  76         timeout = 0;
  77         do {
  78                 printk_spew("+");
  79                 udelay(100);
  80                 send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
  81         } while (send_status && (timeout++ < 1000));
  82         if (timeout >= 1000) {
  83                 printk_err("CPU %d: Second apic write timed out. Disabling\n",
  84                          apicid);
  85                 // too bad.
  86                 return 0;
  87         }
  88
  89         start_eip = (unsigned long)_secondary_start;
  90         printk_spew("start_eip=0x%08lx\n", start_eip);
  91
  92         num_starts = 2;
  93
  94         /*
  95          * Run STARTUP IPI loop.
  96          */
  97         printk_spew("#startup loops: %d.\n", num_starts);
  98
  99         maxlvt = 4;
 100
 101         for (j = 1; j <= num_starts; j++) {
 102                 printk_spew("Sending STARTUP #%d to %u.\n", j, apicid);
 103                 lapic_read_around(LAPIC_SPIV);
 104                 lapic_write(LAPIC_ESR, 0);
 105                 lapic_read(LAPIC_ESR);
 106                 printk_spew("After apic_write.\n");
 107
 108                 /*
 109                  * STARTUP IPI
 110                  */
 111
 112                 /* Target chip */
 113                 lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
 114
 115                 /* Boot on the stack */
 116                 /* Kick the second */
 117                 lapic_write_around(LAPIC_ICR, LAPIC_DM_STARTUP
 118                                         | (start_eip >> 12));
 119
 120                 /*
 121                  * Give the other CPU some time to accept the IPI.
 122                  */
 123                 udelay(300);
 124
 125                 printk_spew("Startup point 1.\n");
 126
 127                 printk_spew("Waiting for send to finish...\n");
 128                 timeout = 0;
 129                 do {
 130                         printk_spew("+");
 131                         udelay(100);
 132                         send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
 133                 } while (send_status && (timeout++ < 1000));
 134
 135                 /*
 136                  * Give the other CPU some time to accept the IPI.
 137                  */
 138                 udelay(200);
 139                 /*
 140                  * Due to the Pentium erratum 3AP.
 141                  */
 142                 if (maxlvt > 3) {
 143                         lapic_read_around(LAPIC_SPIV);
 144                         lapic_write(LAPIC_ESR, 0);
 145                 }
 146                 accept_status = (lapic_read(LAPIC_ESR) & 0xEF);
 147                 if (send_status || accept_status)
 148                         break;
 149         }
 150         printk_spew("After Startup.\n");
 151         if (send_status)
 152                 printk_warning("APIC never delivered???\n");
 153         if (accept_status)
 154                 printk_warning("APIC delivery error (%lx).\n", accept_status);
 155         if (send_status || accept_status)
 156                 return 0;
 157         return 1;
 158 }
 159
 160 /* Number of cpus that are currently running in linuxbios */
 161 static atomic_t active_cpus = ATOMIC_INIT(1);
 162
 163 /* start_cpu_lock covers last_cpu_index and secondary_stack.
 164  * Only starting one cpu at a time let's me remove the logic
 165  * for select the stack from assembly language.
 166  *
 167  * In addition communicating by variables to the cpu I
 168  * am starting allows me to veryify it has started before
 169  * start_cpu returns.
 170  */
 171
 172 static spinlock_t start_cpu_lock = SPIN_LOCK_UNLOCKED;
 173 static unsigned last_cpu_index = 0;
 174 volatile unsigned long secondary_stack;
 175
 176 int start_cpu(device_t cpu)
 177 {
 178         extern unsigned char _estack[];
 179         struct cpu_info *info;
 180         unsigned long stack_end;
 181         unsigned long apicid;
 182         unsigned long index;
 183         unsigned long count;
 184         int result;
 185
 186         spin_lock(&start_cpu_lock);
 187
 188         /* Get the cpu's apicid */
 189         apicid = cpu->path.u.apic.apic_id;
 190
 191         /* Get an index for the new processor */
 192         index = ++last_cpu_index;
 193
 194         /* Find end of the new processors stack */
 195         stack_end = ((unsigned long)_estack) - (STACK_SIZE*index) - sizeof(struct cpu_info);
 196
 197         /* Record the index and which cpu structure we are using */
 198         info = (struct cpu_info *)stack_end;
 199         info->index = index;
 200         info->cpu   = cpu;
 201
 202         /* Advertise the new stack to start_cpu */
 203         secondary_stack = stack_end;
 204
 205         /* Until the cpu starts up report the cpu is not enabled */
 206         cpu->enabled = 0;
 207         cpu->initialized = 0;
 208
 209         /* Start the cpu */
 210         result = lapic_start_cpu(apicid);
 211
 212         if (result) {
 213                 result = 0;
 214                 /* Wait 1s or until the new the new cpu calls in */
 215                 for(count = 0; count < 100000 ; count++) {
 216                         if (secondary_stack == 0) {
 217                                 result = 1;
 218                                 break;
 219                         }
 220                         udelay(10);
 221                 }
 222         }
 223         secondary_stack = 0;
 224         spin_unlock(&start_cpu_lock);
 225         return result;
 226 }
 227
 228 /* C entry point of secondary cpus */
 229 void secondary_cpu_init(void)
 230 {
 231         atomic_inc(&active_cpus);
 232 #if CONFIG_MAX_CPUS>2
 233         spin_lock(&start_cpu_lock);
 234 #endif
 235         cpu_initialize();
 236 #if CONFIG_MAX_CPUS>2
 237         spin_unlock(&start_cpu_lock);
 238 #endif
 239         atomic_dec(&active_cpus);
 240         stop_this_cpu();
 241 }
 242
 243 static void initialize_other_cpus(struct bus *cpu_bus)
 244 {
 245         int old_active_count, active_count;
 246         device_t cpu;
 247         /* Loop through the cpus once getting them started */
 248         for(cpu = cpu_bus->children; cpu ; cpu = cpu->sibling) {
 249                 if (cpu->path.type != DEVICE_PATH_APIC) {
 250                         continue;
 251                 }
 252                 if (!cpu->enabled) {
 253                         continue;
 254                 }
 255                 if (cpu->initialized) {
 256                         continue;
 257                 }
 258                 if (!start_cpu(cpu)) {
 259                         /* Record the error in cpu? */
 260                         printk_err("CPU  %u would not start!\n",
 261                                 cpu->path.u.apic.apic_id);
 262                 }
 263 #if CONFIG_MAX_CPUS>2
 264                 udelay(10);
 265 #endif
 266         }
 267
 268         /* Now loop until the other cpus have finished initializing */
 269         old_active_count = 1;
 270         active_count = atomic_read(&active_cpus);
 271         while(active_count > 1) {
 272                 if (active_count != old_active_count) {
 273                         printk_info("Waiting for %d CPUS to stop\n", active_count - 1);
 274                         old_active_count = active_count;
 275                 }
 276                 udelay(10);
 277                 active_count = atomic_read(&active_cpus);
 278         }
 279         for(cpu = cpu_bus->children; cpu; cpu = cpu->sibling) {
 280                 if (cpu->path.type != DEVICE_PATH_APIC) {
 281                         continue;
 282                 }
 283                 if (!cpu->initialized) {
 284                         printk_err("CPU %u did not initialize!\n",
 285                                 cpu->path.u.apic.apic_id);
 286 #warning "FIXME do I need a mainboard_cpu_fixup function?"
 287                 }
 288         }
 289         printk_debug("All AP CPUs stopped\n");
 290 }
 291
 292 #else /* CONFIG_SMP */
 293 #define initialize_other_cpus(root) do {} while(0)
 294 #endif /* CONFIG_SMP */
 295
 296 void initialize_cpus(struct bus *cpu_bus)
 297 {
 298         struct device_path cpu_path;
 299         struct cpu_info *info;
 300
 301         /* Find the info struct for this cpu */
 302         info = cpu_info();
 303
 304 #if NEED_LAPIC == 1
 305         /* Ensure the local apic is enabled */
 306         enable_lapic();
 307
 308         /* Get the device path of the boot cpu */
 309         cpu_path.type           = DEVICE_PATH_APIC;
 310         cpu_path.u.apic.apic_id = lapicid();
 311 #else
 312         /* Get the device path of the boot cpu */
 313         cpu_path.type           = DEVICE_PATH_CPU;
 314         cpu_path.u.cpu.id       = 0;
 315 #endif
 316
 317         /* Find the device structure for the boot cpu */
 318         info->cpu = alloc_find_dev(cpu_bus, &cpu_path);
 319
 320         /* Initialize the bootstrap processor */
 321         cpu_initialize();
 322
 323         /* Now initialize the rest of the cpus */
 324         initialize_other_cpus(cpu_bus);
 325 }
 326