src/cpu/x86/lapic/lapic_cpu_init.c

   1 /*
   2         2005.12 yhlu add linuxbios_ram cross the vga font buffer handling
   3         2005.12 yhlu add _RAMBASE above 1M support for SMP
   4 */
   5
   6 #include <cpu/x86/lapic.h>
   7 #include <delay.h>
   8 #include <string.h>
   9 #include <console/console.h>
  10 #include <arch/hlt.h>
  11 #include <device/device.h>
  12 #include <device/path.h>
  13 #include <smp/atomic.h>
  14 #include <smp/spinlock.h>
  15 #include <cpu/cpu.h>
  16
  17 #if CONFIG_SMP == 1
  18
  19 /* This is a lot more paranoid now, since Linux can NOT handle
  20  * being told there is a CPU when none exists. So any errors
  21  * will return 0, meaning no CPU.
  22  *
  23  * We actually handling that case by noting which cpus startup
  24  * and not telling anyone about the ones that dont.
  25  */
  26 static unsigned long get_valid_start_eip(unsigned long orig_start_eip)
  27 {
  28         return (unsigned long)orig_start_eip & 0xffff; // 16 bit to avoid 0xa0000
  29 }
  30
  31 static void copy_secondary_start_to_1m_below(void)
  32 {
  33 #if _RAMBASE >= 0x100000
  34         extern char _secondary_start[];
  35         extern char _secondary_start_end[];
  36         unsigned long code_size;
  37         unsigned long start_eip;
  38
  39         /* _secondary_start need to be masked 20 above bit, because 16 bit code in secondary.S
  40                 Also We need to copy the _secondary_start to the below 1M region
  41         */
  42         start_eip = get_valid_start_eip((unsigned long)_secondary_start);
  43         code_size = (unsigned long)_secondary_start_end - (unsigned long)_secondary_start;
  44
  45         /* copy the _secondary_start to the ram below 1M*/
  46         memcpy((unsigned char *)start_eip, (unsigned char *)_secondary_start, code_size);
  47
  48         printk_debug("start_eip=0x%08lx, offset=0x%08lx, code_size=0x%08lx\n", start_eip, ((unsigned long)_secondary_start - start_eip), code_size);
  49 #endif
  50 }
  51
  52 static int lapic_start_cpu(unsigned long apicid)
  53 {
  54         int timeout;
  55         unsigned long send_status, accept_status, start_eip;
  56         int j, num_starts, maxlvt;
  57         extern char _secondary_start[];
  58
  59         /*
  60          * Starting actual IPI sequence...
  61          */
  62
  63         printk_spew("Asserting INIT.\n");
  64
  65         /*
  66          * Turn INIT on target chip
  67          */
  68         lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
  69
  70         /*
  71          * Send IPI
  72          */
  73
  74         lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT
  75                                 | LAPIC_DM_INIT);
  76
  77         printk_spew("Waiting for send to finish...\n");
  78         timeout = 0;
  79         do {
  80                 printk_spew("+");
  81                 udelay(100);
  82                 send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
  83         } while (send_status && (timeout++ < 1000));
  84         if (timeout >= 1000) {
  85                 printk_err("CPU %d: First apic write timed out. Disabling\n",
  86                          apicid);
  87                 // too bad.
  88                 printk_err("ESR is 0x%x\n", lapic_read(LAPIC_ESR));
  89                 if (lapic_read(LAPIC_ESR)) {
  90                         printk_err("Try to reset ESR\n");
  91                         lapic_write_around(LAPIC_ESR, 0);
  92                         printk_err("ESR is 0x%x\n", lapic_read(LAPIC_ESR));
  93                 }
  94                 return 0;
  95         }
  96         mdelay(10);
  97
  98         printk_spew("Deasserting INIT.\n");
  99
 100         /* Target chip */
 101         lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
 102
 103         /* Send IPI */
 104         lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT);
 105
 106         printk_spew("Waiting for send to finish...\n");
 107         timeout = 0;
 108         do {
 109                 printk_spew("+");
 110                 udelay(100);
 111                 send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
 112         } while (send_status && (timeout++ < 1000));
 113         if (timeout >= 1000) {
 114                 printk_err("CPU %d: Second apic write timed out. Disabling\n",
 115                          apicid);
 116                 // too bad.
 117                 return 0;
 118         }
 119
 120 #if _RAMBASE >= 0x100000
 121         start_eip = get_valid_start_eip((unsigned long)_secondary_start);
 122 #else
 123         start_eip = (unsigned long)_secondary_start;
 124 #endif
 125
 126         num_starts = 2;
 127
 128         /*
 129          * Run STARTUP IPI loop.
 130          */
 131         printk_spew("#startup loops: %d.\n", num_starts);
 132
 133         maxlvt = 4;
 134
 135         for (j = 1; j <= num_starts; j++) {
 136                 printk_spew("Sending STARTUP #%d to %u.\n", j, apicid);
 137                 lapic_read_around(LAPIC_SPIV);
 138                 lapic_write(LAPIC_ESR, 0);
 139                 lapic_read(LAPIC_ESR);
 140                 printk_spew("After apic_write.\n");
 141
 142                 /*
 143                  * STARTUP IPI
 144                  */
 145
 146                 /* Target chip */
 147                 lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
 148
 149                 /* Boot on the stack */
 150                 /* Kick the second */
 151                 lapic_write_around(LAPIC_ICR, LAPIC_DM_STARTUP
 152                                         | (start_eip >> 12));
 153
 154                 /*
 155                  * Give the other CPU some time to accept the IPI.
 156                  */
 157                 udelay(300);
 158
 159                 printk_spew("Startup point 1.\n");
 160
 161                 printk_spew("Waiting for send to finish...\n");
 162                 timeout = 0;
 163                 do {
 164                         printk_spew("+");
 165                         udelay(100);
 166                         send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
 167                 } while (send_status && (timeout++ < 1000));
 168
 169                 /*
 170                  * Give the other CPU some time to accept the IPI.
 171                  */
 172                 udelay(200);
 173                 /*
 174                  * Due to the Pentium erratum 3AP.
 175                  */
 176                 if (maxlvt > 3) {
 177                         lapic_read_around(LAPIC_SPIV);
 178                         lapic_write(LAPIC_ESR, 0);
 179                 }
 180                 accept_status = (lapic_read(LAPIC_ESR) & 0xEF);
 181                 if (send_status || accept_status)
 182                         break;
 183         }
 184         printk_spew("After Startup.\n");
 185         if (send_status)
 186                 printk_warning("APIC never delivered???\n");
 187         if (accept_status)
 188                 printk_warning("APIC delivery error (%lx).\n", accept_status);
 189         if (send_status || accept_status)
 190                 return 0;
 191         return 1;
 192 }
 193
 194 /* Number of cpus that are currently running in linuxbios */
 195 static atomic_t active_cpus = ATOMIC_INIT(1);
 196
 197 /* start_cpu_lock covers last_cpu_index and secondary_stack.
 198  * Only starting one cpu at a time let's me remove the logic
 199  * for select the stack from assembly language.
 200  *
 201  * In addition communicating by variables to the cpu I
 202  * am starting allows me to veryify it has started before
 203  * start_cpu returns.
 204  */
 205
 206 static spinlock_t start_cpu_lock = SPIN_LOCK_UNLOCKED;
 207 static unsigned last_cpu_index = 0;
 208 volatile unsigned long secondary_stack;
 209
 210 int start_cpu(device_t cpu)
 211 {
 212         extern unsigned char _estack[];
 213         struct cpu_info *info;
 214         unsigned long stack_end;
 215         unsigned long apicid;
 216         unsigned long index;
 217         unsigned long count;
 218         int result;
 219
 220         spin_lock(&start_cpu_lock);
 221
 222         /* Get the cpu's apicid */
 223         apicid = cpu->path.u.apic.apic_id;
 224
 225         /* Get an index for the new processor */
 226         index = ++last_cpu_index;
 227
 228         /* Find end of the new processors stack */
 229 #if (CONFIG_LB_MEM_TOPK>1024) && (_RAMBASE < 0x100000) && ((CONFIG_CONSOLE_VGA==1) || (CONFIG_PCI_ROM_RUN == 1))
 230         if(index<1) { // only keep bsp on low
 231                 stack_end = ((unsigned long)_estack) - (STACK_SIZE*index) - sizeof(struct cpu_info);
 232         } else {
 233                 // for all APs, let use stack after pgtbl, 20480 is the pgtbl size for every cpu
 234                 stack_end = 0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPUS - (STACK_SIZE*index);
 235 #if (0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPU) > (CONFIG_LB_MEM_TOPK<<10)
 236                 #warning "We may need to increase CONFIG_LB_MEM_TOPK, it need to be more than (0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPU)\n"
 237 #endif
 238                 if(stack_end > (CONFIG_LB_MEM_TOPK<<10)) {
 239                         printk_debug("start_cpu: Please increase the CONFIG_LB_MEM_TOPK more than %dK\n", stack_end>>10);
 240                         die("Can not go on\n");
 241                 }
 242                 stack_end -= sizeof(struct cpu_info);
 243         }
 244 #else
 245         stack_end = ((unsigned long)_estack) - (STACK_SIZE*index) - sizeof(struct cpu_info);
 246 #endif
 247
 248
 249         /* Record the index and which cpu structure we are using */
 250         info = (struct cpu_info *)stack_end;
 251         info->index = index;
 252         info->cpu   = cpu;
 253
 254         /* Advertise the new stack to start_cpu */
 255         secondary_stack = stack_end;
 256
 257         /* Until the cpu starts up report the cpu is not enabled */
 258         cpu->enabled = 0;
 259         cpu->initialized = 0;
 260
 261         /* Start the cpu */
 262         result = lapic_start_cpu(apicid);
 263
 264         if (result) {
 265                 result = 0;
 266                 /* Wait 1s or until the new the new cpu calls in */
 267                 for(count = 0; count < 100000 ; count++) {
 268                         if (secondary_stack == 0) {
 269                                 result = 1;
 270                                 break;
 271                         }
 272                         udelay(10);
 273                 }
 274         }
 275         secondary_stack = 0;
 276         spin_unlock(&start_cpu_lock);
 277         return result;
 278 }
 279
 280 /* C entry point of secondary cpus */
 281 void secondary_cpu_init(void)
 282 {
 283         atomic_inc(&active_cpus);
 284 #if SERIAL_CPU_INIT == 1
 285   #if CONFIG_MAX_CPUS>2
 286         spin_lock(&start_cpu_lock);
 287   #endif
 288 #endif
 289         cpu_initialize();
 290 #if SERIAL_CPU_INIT == 1
 291   #if CONFIG_MAX_CPUS>2
 292         spin_unlock(&start_cpu_lock);
 293   #endif
 294 #endif
 295
 296         atomic_dec(&active_cpus);
 297         stop_this_cpu();
 298 }
 299
 300 static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu)
 301 {
 302         device_t cpu;
 303         /* Loop through the cpus once getting them started */
 304
 305         for(cpu = cpu_bus->children; cpu ; cpu = cpu->sibling) {
 306                 if (cpu->path.type != DEVICE_PATH_APIC) {
 307                         continue;
 308                 }
 309         #if SERIAL_CPU_INIT == 0
 310                 if(cpu==bsp_cpu) {
 311                         continue;
 312                 }
 313         #endif
 314
 315                 if (!cpu->enabled) {
 316                         continue;
 317                 }
 318
 319                 if (cpu->initialized) {
 320                         continue;
 321                 }
 322
 323                 if (!start_cpu(cpu)) {
 324                         /* Record the error in cpu? */
 325                         printk_err("CPU  %u would not start!\n",
 326                                 cpu->path.u.apic.apic_id);
 327                 }
 328 #if SERIAL_CPU_INIT == 1
 329   #if CONFIG_MAX_CPUS>2
 330                 udelay(10);
 331   #endif
 332 #endif
 333         }
 334
 335 }
 336
 337 static void wait_other_cpus_stop(struct bus *cpu_bus)
 338 {
 339         device_t cpu;
 340         int old_active_count, active_count;
 341         /* Now loop until the other cpus have finished initializing */
 342         old_active_count = 1;
 343         active_count = atomic_read(&active_cpus);
 344         while(active_count > 1) {
 345                 if (active_count != old_active_count) {
 346                         printk_info("Waiting for %d CPUS to stop\n", active_count - 1);
 347                         old_active_count = active_count;
 348                 }
 349                 udelay(10);
 350                 active_count = atomic_read(&active_cpus);
 351         }
 352         for(cpu = cpu_bus->children; cpu; cpu = cpu->sibling) {
 353                 if (cpu->path.type != DEVICE_PATH_APIC) {
 354                         continue;
 355                 }
 356                 if (!cpu->initialized) {
 357                         printk_err("CPU %u did not initialize!\n",
 358                                 cpu->path.u.apic.apic_id);
 359 #warning "FIXME do I need a mainboard_cpu_fixup function?"
 360                 }
 361         }
 362         printk_debug("All AP CPUs stopped\n");
 363 }
 364
 365 #else /* CONFIG_SMP */
 366 #define initialize_other_cpus(root) do {} while(0)
 367 #endif /* CONFIG_SMP */
 368
 369 void initialize_cpus(struct bus *cpu_bus)
 370 {
 371         struct device_path cpu_path;
 372         struct cpu_info *info;
 373
 374         /* Find the info struct for this cpu */
 375         info = cpu_info();
 376
 377 #if NEED_LAPIC == 1
 378         /* Ensure the local apic is enabled */
 379         enable_lapic();
 380
 381         /* Get the device path of the boot cpu */
 382         cpu_path.type           = DEVICE_PATH_APIC;
 383         cpu_path.u.apic.apic_id = lapicid();
 384 #else
 385         /* Get the device path of the boot cpu */
 386         cpu_path.type           = DEVICE_PATH_CPU;
 387         cpu_path.u.cpu.id       = 0;
 388 #endif
 389
 390         /* Find the device structure for the boot cpu */
 391         info->cpu = alloc_find_dev(cpu_bus, &cpu_path);
 392
 393 #if CONFIG_SMP == 1
 394         copy_secondary_start_to_1m_below(); // why here? In case some day we can start core1 in amd_sibling_init
 395 #endif
 396
 397 #if CONFIG_SMP == 1
 398         #if SERIAL_CPU_INIT == 0
 399         /* start all aps at first, so we can init ECC all together */
 400         start_other_cpus(cpu_bus, info->cpu);
 401         #endif
 402 #endif
 403
 404         /* Initialize the bootstrap processor */
 405         cpu_initialize();
 406
 407
 408 #if CONFIG_SMP == 1
 409         #if SERIAL_CPU_INIT == 1
 410         /* start all aps */
 411         start_other_cpus(cpu_bus, info->cpu);
 412         #endif
 413
 414         /* Now wait the rest of the cpus stop*/
 415         wait_other_cpus_stop(cpu_bus);
 416 #endif
 417
 418 }
 419