src/cpu/x86/lapic/lapic_cpu_init.c

   1 /*
   2         2005.12 yhlu add linuxbios_ram cross the vga font buffer handling
   3         2005.12 yhlu add _RAMBASE above 1M support for SMP
   4 */
   5
   6 #include <cpu/x86/lapic.h>
   7 #include <delay.h>
   8 #include <string.h>
   9 #include <console/console.h>
  10 #include <arch/hlt.h>
  11 #include <device/device.h>
  12 #include <device/path.h>
  13 #include <smp/atomic.h>
  14 #include <smp/spinlock.h>
  15 #include <cpu/cpu.h>
  16
  17 #if CONFIG_SMP == 1
  18
  19 /* This is a lot more paranoid now, since Linux can NOT handle
  20  * being told there is a CPU when none exists. So any errors
  21  * will return 0, meaning no CPU.
  22  *
  23  * We actually handling that case by noting which cpus startup
  24  * and not telling anyone about the ones that dont.
  25  */
  26 static unsigned long get_valid_start_eip(unsigned long orig_start_eip)
  27 {
  28         return (unsigned long)orig_start_eip & 0xfffff; // 20 bit
  29 }
  30
  31 static void copy_secondary_start_to_1m_below(void)
  32 {
  33 #if _RAMBASE > 0x100000
  34         extern char _secondary_start[];
  35         extern char _secondary_start_end[];
  36         unsigned long code_size;
  37         unsigned long start_eip;
  38
  39         /* _secondary_start need to be masked 20 above bit, because 16 bit code in secondary.S
  40                 Also We need to copy the _secondary_start to the below 1M region
  41         */
  42         start_eip = get_valid_start_eip((unsigned long)_secondary_start);
  43         code_size = (unsigned long)_secondary_start_end - (unsigned long)_secondary_start;
  44
  45         /* copy the _secondary_start to the ram below 1M*/
  46         memcpy(start_eip, (unsigned long)_secondary_start, code_size);
  47
  48         printk_debug("start_eip=0x%08lx, offset=0x%08lx, code_size=0x%08lx\n", start_eip, ((unsigned long)_secondary_start - start_eip), code_size);
  49 #endif
  50 }
  51
  52 static int lapic_start_cpu(unsigned long apicid)
  53 {
  54         int timeout;
  55         unsigned long send_status, accept_status, start_eip;
  56         int j, num_starts, maxlvt;
  57         extern char _secondary_start[];
  58
  59         /*
  60          * Starting actual IPI sequence...
  61          */
  62
  63         printk_spew("Asserting INIT.\n");
  64
  65         /*
  66          * Turn INIT on target chip
  67          */
  68         lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
  69
  70         /*
  71          * Send IPI
  72          */
  73
  74         lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT
  75                                 | LAPIC_DM_INIT);
  76
  77         printk_spew("Waiting for send to finish...\n");
  78         timeout = 0;
  79         do {
  80                 printk_spew("+");
  81                 udelay(100);
  82                 send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
  83         } while (send_status && (timeout++ < 1000));
  84         if (timeout >= 1000) {
  85                 printk_err("CPU %d: First apic write timed out. Disabling\n",
  86                          apicid);
  87                 // too bad.
  88                 printk_err("ESR is 0x%x\n", lapic_read(LAPIC_ESR));
  89                 if (lapic_read(LAPIC_ESR)) {
  90                         printk_err("Try to reset ESR\n");
  91                         lapic_write_around(LAPIC_ESR, 0);
  92                         printk_err("ESR is 0x%x\n", lapic_read(LAPIC_ESR));
  93                 }
  94                 return 0;
  95         }
  96         mdelay(10);
  97
  98         printk_spew("Deasserting INIT.\n");
  99
 100         /* Target chip */
 101         lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
 102
 103         /* Send IPI */
 104         lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT);
 105
 106         printk_spew("Waiting for send to finish...\n");
 107         timeout = 0;
 108         do {
 109                 printk_spew("+");
 110                 udelay(100);
 111                 send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
 112         } while (send_status && (timeout++ < 1000));
 113         if (timeout >= 1000) {
 114                 printk_err("CPU %d: Second apic write timed out. Disabling\n",
 115                          apicid);
 116                 // too bad.
 117                 return 0;
 118         }
 119
 120         start_eip = get_valid_start_eip((unsigned long)_secondary_start);
 121         printk_debug("start_eip=0x%08lx\n", start_eip);
 122
 123         num_starts = 2;
 124
 125         /*
 126          * Run STARTUP IPI loop.
 127          */
 128         printk_spew("#startup loops: %d.\n", num_starts);
 129
 130         maxlvt = 4;
 131
 132         for (j = 1; j <= num_starts; j++) {
 133                 printk_spew("Sending STARTUP #%d to %u.\n", j, apicid);
 134                 lapic_read_around(LAPIC_SPIV);
 135                 lapic_write(LAPIC_ESR, 0);
 136                 lapic_read(LAPIC_ESR);
 137                 printk_spew("After apic_write.\n");
 138
 139                 /*
 140                  * STARTUP IPI
 141                  */
 142
 143                 /* Target chip */
 144                 lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
 145
 146                 /* Boot on the stack */
 147                 /* Kick the second */
 148                 lapic_write_around(LAPIC_ICR, LAPIC_DM_STARTUP
 149                                         | (start_eip >> 12));
 150
 151                 /*
 152                  * Give the other CPU some time to accept the IPI.
 153                  */
 154                 udelay(300);
 155
 156                 printk_spew("Startup point 1.\n");
 157
 158                 printk_spew("Waiting for send to finish...\n");
 159                 timeout = 0;
 160                 do {
 161                         printk_spew("+");
 162                         udelay(100);
 163                         send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
 164                 } while (send_status && (timeout++ < 1000));
 165
 166                 /*
 167                  * Give the other CPU some time to accept the IPI.
 168                  */
 169                 udelay(200);
 170                 /*
 171                  * Due to the Pentium erratum 3AP.
 172                  */
 173                 if (maxlvt > 3) {
 174                         lapic_read_around(LAPIC_SPIV);
 175                         lapic_write(LAPIC_ESR, 0);
 176                 }
 177                 accept_status = (lapic_read(LAPIC_ESR) & 0xEF);
 178                 if (send_status || accept_status)
 179                         break;
 180         }
 181         printk_spew("After Startup.\n");
 182         if (send_status)
 183                 printk_warning("APIC never delivered???\n");
 184         if (accept_status)
 185                 printk_warning("APIC delivery error (%lx).\n", accept_status);
 186         if (send_status || accept_status)
 187                 return 0;
 188         return 1;
 189 }
 190
 191 /* Number of cpus that are currently running in linuxbios */
 192 static atomic_t active_cpus = ATOMIC_INIT(1);
 193
 194 /* start_cpu_lock covers last_cpu_index and secondary_stack.
 195  * Only starting one cpu at a time let's me remove the logic
 196  * for select the stack from assembly language.
 197  *
 198  * In addition communicating by variables to the cpu I
 199  * am starting allows me to veryify it has started before
 200  * start_cpu returns.
 201  */
 202
 203 static spinlock_t start_cpu_lock = SPIN_LOCK_UNLOCKED;
 204 static unsigned last_cpu_index = 0;
 205 volatile unsigned long secondary_stack;
 206
 207 int start_cpu(device_t cpu)
 208 {
 209         extern unsigned char _estack[];
 210         struct cpu_info *info;
 211         unsigned long stack_end;
 212         unsigned long apicid;
 213         unsigned long index;
 214         unsigned long count;
 215         int result;
 216
 217         spin_lock(&start_cpu_lock);
 218
 219         /* Get the cpu's apicid */
 220         apicid = cpu->path.u.apic.apic_id;
 221
 222         /* Get an index for the new processor */
 223         index = ++last_cpu_index;
 224
 225         /* Find end of the new processors stack */
 226 #if (CONFIG_LB_MEM_TOPK>1024) && (_RAMBASE < 0x100000) && ((CONFIG_CONSOLE_VGA==1) || (CONFIG_PCI_ROM_RUN == 1))
 227         if(index<1) { // only keep bsp on low
 228                 stack_end = ((unsigned long)_estack) - (STACK_SIZE*index) - sizeof(struct cpu_info);
 229         } else {
 230                 // for all APs, let use stack after pgtbl, 20480 is the pgtbl size for every cpu
 231                 stack_end = 0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPUS - (STACK_SIZE*index);
 232 #if (0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPU) > (CONFIG_LB_MEM_TOPK<<10)
 233                 #warning "We may need to increase CONFIG_LB_MEM_TOPK, it need to be more than (0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPU)\n"
 234 #endif
 235                 if(stack_end > (CONFIG_LB_MEM_TOPK<<10)) {
 236                         printk_debug("start_cpu: Please increase the CONFIG_LB_MEM_TOPK more than %dK\n", stack_end>>10);
 237                         die("Can not go on\n");
 238                 }
 239                 stack_end -= sizeof(struct cpu_info);
 240         }
 241 #else
 242         stack_end = ((unsigned long)_estack) - (STACK_SIZE*index) - sizeof(struct cpu_info);
 243 #endif
 244
 245
 246         /* Record the index and which cpu structure we are using */
 247         info = (struct cpu_info *)stack_end;
 248         info->index = index;
 249         info->cpu   = cpu;
 250
 251         /* Advertise the new stack to start_cpu */
 252         secondary_stack = stack_end;
 253
 254         /* Until the cpu starts up report the cpu is not enabled */
 255         cpu->enabled = 0;
 256         cpu->initialized = 0;
 257
 258         /* Start the cpu */
 259         result = lapic_start_cpu(apicid);
 260
 261         if (result) {
 262                 result = 0;
 263                 /* Wait 1s or until the new the new cpu calls in */
 264                 for(count = 0; count < 100000 ; count++) {
 265                         if (secondary_stack == 0) {
 266                                 result = 1;
 267                                 break;
 268                         }
 269                         udelay(10);
 270                 }
 271         }
 272         secondary_stack = 0;
 273         spin_unlock(&start_cpu_lock);
 274         return result;
 275 }
 276
 277 /* C entry point of secondary cpus */
 278 void secondary_cpu_init(void)
 279 {
 280         atomic_inc(&active_cpus);
 281 #if SERIAL_CPU_INIT == 1
 282   #if CONFIG_MAX_CPUS>2
 283         spin_lock(&start_cpu_lock);
 284   #endif
 285 #endif
 286         cpu_initialize();
 287 #if SERIAL_CPU_INIT == 1
 288   #if CONFIG_MAX_CPUS>2
 289         spin_unlock(&start_cpu_lock);
 290   #endif
 291 #endif
 292
 293         atomic_dec(&active_cpus);
 294         stop_this_cpu();
 295 }
 296
 297 static void initialize_other_cpus(struct bus *cpu_bus)
 298 {
 299         int old_active_count, active_count;
 300         device_t cpu;
 301         /* Loop through the cpus once getting them started */
 302
 303         for(cpu = cpu_bus->children; cpu ; cpu = cpu->sibling) {
 304                 if (cpu->path.type != DEVICE_PATH_APIC) {
 305                         continue;
 306                 }
 307
 308                 if (!cpu->enabled) {
 309                         continue;
 310                 }
 311
 312                 if (cpu->initialized) {
 313                         continue;
 314                 }
 315
 316                 if (!start_cpu(cpu)) {
 317                         /* Record the error in cpu? */
 318                         printk_err("CPU  %u would not start!\n",
 319                                 cpu->path.u.apic.apic_id);
 320                 }
 321 #if SERIAL_CPU_INIT == 1
 322   #if CONFIG_MAX_CPUS>2
 323                 udelay(10);
 324   #endif
 325 #endif
 326         }
 327
 328         /* Now loop until the other cpus have finished initializing */
 329         old_active_count = 1;
 330         active_count = atomic_read(&active_cpus);
 331         while(active_count > 1) {
 332                 if (active_count != old_active_count) {
 333                         printk_info("Waiting for %d CPUS to stop\n", active_count - 1);
 334                         old_active_count = active_count;
 335                 }
 336                 udelay(10);
 337                 active_count = atomic_read(&active_cpus);
 338         }
 339         for(cpu = cpu_bus->children; cpu; cpu = cpu->sibling) {
 340                 if (cpu->path.type != DEVICE_PATH_APIC) {
 341                         continue;
 342                 }
 343                 if (!cpu->initialized) {
 344                         printk_err("CPU %u did not initialize!\n",
 345                                 cpu->path.u.apic.apic_id);
 346 #warning "FIXME do I need a mainboard_cpu_fixup function?"
 347                 }
 348         }
 349         printk_debug("All AP CPUs stopped\n");
 350 }
 351
 352 #else /* CONFIG_SMP */
 353 #define initialize_other_cpus(root) do {} while(0)
 354 #endif /* CONFIG_SMP */
 355
 356 void initialize_cpus(struct bus *cpu_bus)
 357 {
 358         struct device_path cpu_path;
 359         struct cpu_info *info;
 360
 361         /* Find the info struct for this cpu */
 362         info = cpu_info();
 363
 364 #if NEED_LAPIC == 1
 365         /* Ensure the local apic is enabled */
 366         enable_lapic();
 367
 368         /* Get the device path of the boot cpu */
 369         cpu_path.type           = DEVICE_PATH_APIC;
 370         cpu_path.u.apic.apic_id = lapicid();
 371 #else
 372         /* Get the device path of the boot cpu */
 373         cpu_path.type           = DEVICE_PATH_CPU;
 374         cpu_path.u.cpu.id       = 0;
 375 #endif
 376
 377         /* Find the device structure for the boot cpu */
 378         info->cpu = alloc_find_dev(cpu_bus, &cpu_path);
 379
 380         copy_secondary_start_to_1m_below(); // why here? In case some day we can start core1 in amd_sibling_init
 381
 382         /* Initialize the bootstrap processor */
 383         cpu_initialize();
 384
 385         /* Now initialize the rest of the cpus */
 386         initialize_other_cpus(cpu_bus);
 387 }
 388