src/cpu/x86/lapic/lapic_cpu_init.c

   1 /*
   2         2005.12 yhlu add coreboot_ram cross the vga font buffer handling
   3         2005.12 yhlu add _RAMBASE above 1M support for SMP
   4         2008.05 stepan add support for going back to sipi wait state
   5 */
   6
   7 #include <cpu/x86/lapic.h>
   8 #include <delay.h>
   9 #include <string.h>
  10 #include <console/console.h>
  11 #include <arch/hlt.h>
  12 #include <device/device.h>
  13 #include <device/path.h>
  14 #include <smp/atomic.h>
  15 #include <smp/spinlock.h>
  16 #include <cpu/cpu.h>
  17
  18 #if CONFIG_SMP == 1
  19
  20 #if _RAMBASE >= 0x100000
  21 /* This is a lot more paranoid now, since Linux can NOT handle
  22  * being told there is a CPU when none exists. So any errors
  23  * will return 0, meaning no CPU.
  24  *
  25  * We actually handling that case by noting which cpus startup
  26  * and not telling anyone about the ones that dont.
  27  */
  28 static unsigned long get_valid_start_eip(unsigned long orig_start_eip)
  29 {
  30         return (unsigned long)orig_start_eip & 0xffff; // 16 bit to avoid 0xa0000
  31 }
  32 #endif
  33
  34 static void copy_secondary_start_to_1m_below(void)
  35 {
  36 #if _RAMBASE >= 0x100000
  37         extern char _secondary_start[];
  38         extern char _secondary_start_end[];
  39         unsigned long code_size;
  40         unsigned long start_eip;
  41
  42         /* _secondary_start need to be masked 20 above bit, because 16 bit code in secondary.S
  43                 Also We need to copy the _secondary_start to the below 1M region
  44         */
  45         start_eip = get_valid_start_eip((unsigned long)_secondary_start);
  46         code_size = (unsigned long)_secondary_start_end - (unsigned long)_secondary_start;
  47
  48         /* copy the _secondary_start to the ram below 1M*/
  49         memcpy((unsigned char *)start_eip, (unsigned char *)_secondary_start, code_size);
  50
  51         printk_debug("start_eip=0x%08lx, offset=0x%08lx, code_size=0x%08lx\n", start_eip, ((unsigned long)_secondary_start - start_eip), code_size);
  52 #endif
  53 }
  54
  55 static int lapic_start_cpu(unsigned long apicid)
  56 {
  57         int timeout;
  58         unsigned long send_status, accept_status, start_eip;
  59         int j, num_starts, maxlvt;
  60         extern char _secondary_start[];
  61
  62         /*
  63          * Starting actual IPI sequence...
  64          */
  65
  66         printk_spew("Asserting INIT.\n");
  67
  68         /*
  69          * Turn INIT on target chip
  70          */
  71         lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
  72
  73         /*
  74          * Send IPI
  75          */
  76
  77         lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT
  78                                 | LAPIC_DM_INIT);
  79
  80         printk_spew("Waiting for send to finish...\n");
  81         timeout = 0;
  82         do {
  83                 printk_spew("+");
  84                 udelay(100);
  85                 send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
  86         } while (send_status && (timeout++ < 1000));
  87         if (timeout >= 1000) {
  88                 printk_err("CPU %ld: First apic write timed out. Disabling\n",
  89                          apicid);
  90                 // too bad.
  91                 printk_err("ESR is 0x%lx\n", lapic_read(LAPIC_ESR));
  92                 if (lapic_read(LAPIC_ESR)) {
  93                         printk_err("Try to reset ESR\n");
  94                         lapic_write_around(LAPIC_ESR, 0);
  95                         printk_err("ESR is 0x%lx\n", lapic_read(LAPIC_ESR));
  96                 }
  97                 return 0;
  98         }
  99         mdelay(10);
 100
 101         printk_spew("Deasserting INIT.\n");
 102
 103         /* Target chip */
 104         lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
 105
 106         /* Send IPI */
 107         lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT);
 108
 109         printk_spew("Waiting for send to finish...\n");
 110         timeout = 0;
 111         do {
 112                 printk_spew("+");
 113                 udelay(100);
 114                 send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
 115         } while (send_status && (timeout++ < 1000));
 116         if (timeout >= 1000) {
 117                 printk_err("CPU %ld: Second apic write timed out. Disabling\n",
 118                          apicid);
 119                 // too bad.
 120                 return 0;
 121         }
 122
 123 #if _RAMBASE >= 0x100000
 124         start_eip = get_valid_start_eip((unsigned long)_secondary_start);
 125 #else
 126         start_eip = (unsigned long)_secondary_start;
 127 #endif
 128
 129         num_starts = 2;
 130
 131         /*
 132          * Run STARTUP IPI loop.
 133          */
 134         printk_spew("#startup loops: %d.\n", num_starts);
 135
 136         maxlvt = 4;
 137
 138         for (j = 1; j <= num_starts; j++) {
 139                 printk_spew("Sending STARTUP #%d to %lu.\n", j, apicid);
 140                 lapic_read_around(LAPIC_SPIV);
 141                 lapic_write(LAPIC_ESR, 0);
 142                 lapic_read(LAPIC_ESR);
 143                 printk_spew("After apic_write.\n");
 144
 145                 /*
 146                  * STARTUP IPI
 147                  */
 148
 149                 /* Target chip */
 150                 lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
 151
 152                 /* Boot on the stack */
 153                 /* Kick the second */
 154                 lapic_write_around(LAPIC_ICR, LAPIC_DM_STARTUP
 155                                         | (start_eip >> 12));
 156
 157                 /*
 158                  * Give the other CPU some time to accept the IPI.
 159                  */
 160                 udelay(300);
 161
 162                 printk_spew("Startup point 1.\n");
 163
 164                 printk_spew("Waiting for send to finish...\n");
 165                 timeout = 0;
 166                 do {
 167                         printk_spew("+");
 168                         udelay(100);
 169                         send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
 170                 } while (send_status && (timeout++ < 1000));
 171
 172                 /*
 173                  * Give the other CPU some time to accept the IPI.
 174                  */
 175                 udelay(200);
 176                 /*
 177                  * Due to the Pentium erratum 3AP.
 178                  */
 179                 if (maxlvt > 3) {
 180                         lapic_read_around(LAPIC_SPIV);
 181                         lapic_write(LAPIC_ESR, 0);
 182                 }
 183                 accept_status = (lapic_read(LAPIC_ESR) & 0xEF);
 184                 if (send_status || accept_status)
 185                         break;
 186         }
 187         printk_spew("After Startup.\n");
 188         if (send_status)
 189                 printk_warning("APIC never delivered???\n");
 190         if (accept_status)
 191                 printk_warning("APIC delivery error (%lx).\n", accept_status);
 192         if (send_status || accept_status)
 193                 return 0;
 194         return 1;
 195 }
 196
 197 /* Number of cpus that are currently running in coreboot */
 198 static atomic_t active_cpus = ATOMIC_INIT(1);
 199
 200 /* start_cpu_lock covers last_cpu_index and secondary_stack.
 201  * Only starting one cpu at a time let's me remove the logic
 202  * for select the stack from assembly language.
 203  *
 204  * In addition communicating by variables to the cpu I
 205  * am starting allows me to veryify it has started before
 206  * start_cpu returns.
 207  */
 208
 209 static spinlock_t start_cpu_lock = SPIN_LOCK_UNLOCKED;
 210 static unsigned last_cpu_index = 0;
 211 volatile unsigned long secondary_stack;
 212
 213 int start_cpu(device_t cpu)
 214 {
 215         extern unsigned char _estack[];
 216         struct cpu_info *info;
 217         unsigned long stack_end;
 218         unsigned long apicid;
 219         unsigned long index;
 220         unsigned long count;
 221         int result;
 222
 223         spin_lock(&start_cpu_lock);
 224
 225         /* Get the cpu's apicid */
 226         apicid = cpu->path.apic.apic_id;
 227
 228         /* Get an index for the new processor */
 229         index = ++last_cpu_index;
 230
 231         /* Find end of the new processors stack */
 232 #if (CONFIG_LB_MEM_TOPK>1024) && (_RAMBASE < 0x100000) && ((CONFIG_CONSOLE_VGA==1) || (CONFIG_PCI_ROM_RUN == 1))
 233         if(index<1) { // only keep bsp on low
 234                 stack_end = ((unsigned long)_estack) - (STACK_SIZE*index) - sizeof(struct cpu_info);
 235         } else {
 236                 // for all APs, let use stack after pgtbl, 20480 is the pgtbl size for every cpu
 237                 stack_end = 0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPUS - (STACK_SIZE*index);
 238 #if (0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPU) > (CONFIG_LB_MEM_TOPK<<10)
 239                 #warning "We may need to increase CONFIG_LB_MEM_TOPK, it need to be more than (0x100000+(20480 + STACK_SIZE)*CONFIG_MAX_CPU)\n"
 240 #endif
 241                 if(stack_end > (CONFIG_LB_MEM_TOPK<<10)) {
 242                         printk_debug("start_cpu: Please increase the CONFIG_LB_MEM_TOPK more than %luK\n", stack_end>>10);
 243                         die("Can not go on\n");
 244                 }
 245                 stack_end -= sizeof(struct cpu_info);
 246         }
 247 #else
 248         stack_end = ((unsigned long)_estack) - (STACK_SIZE*index) - sizeof(struct cpu_info);
 249 #endif
 250
 251
 252         /* Record the index and which cpu structure we are using */
 253         info = (struct cpu_info *)stack_end;
 254         info->index = index;
 255         info->cpu   = cpu;
 256
 257         /* Advertise the new stack to start_cpu */
 258         secondary_stack = stack_end;
 259
 260         /* Until the cpu starts up report the cpu is not enabled */
 261         cpu->enabled = 0;
 262         cpu->initialized = 0;
 263
 264         /* Start the cpu */
 265         result = lapic_start_cpu(apicid);
 266
 267         if (result) {
 268                 result = 0;
 269                 /* Wait 1s or until the new the new cpu calls in */
 270                 for(count = 0; count < 100000 ; count++) {
 271                         if (secondary_stack == 0) {
 272                                 result = 1;
 273                                 break;
 274                         }
 275                         udelay(10);
 276                 }
 277         }
 278         secondary_stack = 0;
 279         spin_unlock(&start_cpu_lock);
 280         return result;
 281 }
 282
 283 #if CONFIG_AP_IN_SIPI_WAIT == 1
 284 /**
 285  * Normally this function is defined in lapic.h as an always inline function
 286  * that just keeps the CPU in a hlt() loop. This does not work on all CPUs.
 287  * I think all hyperthreading CPUs might need this version, but I could only
 288  * verify this on the Intel Core Duo
 289  */
 290 void stop_this_cpu(void)
 291 {
 292         int timeout;
 293         unsigned long send_status;
 294         unsigned long id;
 295
 296         id = lapic_read(LAPIC_ID) >> 24;
 297
 298         printk_debug("CPU %ld going down...\n", id);
 299
 300         /* send an LAPIC INIT to myself */
 301         lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(id));
 302         lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT | LAPIC_DM_INIT);
 303
 304         /* wait for the ipi send to finish */
 305 #if 0
 306         // When these two printk_spew calls are not removed, the
 307         // machine will hang when log level is SPEW. Why?
 308         printk_spew("Waiting for send to finish...\n");
 309 #endif
 310         timeout = 0;
 311         do {
 312 #if 0
 313                 printk_spew("+");
 314 #endif
 315                 udelay(100);
 316                 send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
 317         } while (send_status && (timeout++ < 1000));
 318         if (timeout >= 1000) {
 319                 printk_err("timed out\n");
 320         }
 321         mdelay(10);
 322
 323         printk_spew("Deasserting INIT.\n");
 324         /* Deassert the LAPIC INIT */
 325         lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(id));
 326         lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT);
 327
 328         printk_spew("Waiting for send to finish...\n");
 329         timeout = 0;
 330         do {
 331                 printk_spew("+");
 332                 udelay(100);
 333                 send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
 334         } while (send_status && (timeout++ < 1000));
 335         if (timeout >= 1000) {
 336                 printk_err("timed out\n");
 337         }
 338
 339         while(1) {
 340                 hlt();
 341         }
 342 }
 343 #endif
 344
 345 /* C entry point of secondary cpus */
 346 void secondary_cpu_init(void)
 347 {
 348         atomic_inc(&active_cpus);
 349 #if SERIAL_CPU_INIT == 1
 350   #if CONFIG_MAX_CPUS>2
 351         spin_lock(&start_cpu_lock);
 352   #endif
 353 #endif
 354         cpu_initialize();
 355 #if SERIAL_CPU_INIT == 1
 356   #if CONFIG_MAX_CPUS>2
 357         spin_unlock(&start_cpu_lock);
 358   #endif
 359 #endif
 360
 361         atomic_dec(&active_cpus);
 362
 363         stop_this_cpu();
 364 }
 365
 366 static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu)
 367 {
 368         device_t cpu;
 369         /* Loop through the cpus once getting them started */
 370
 371         for(cpu = cpu_bus->children; cpu ; cpu = cpu->sibling) {
 372                 if (cpu->path.type != DEVICE_PATH_APIC) {
 373                         continue;
 374                 }
 375         #if SERIAL_CPU_INIT == 0
 376                 if(cpu==bsp_cpu) {
 377                         continue;
 378                 }
 379         #endif
 380
 381                 if (!cpu->enabled) {
 382                         continue;
 383                 }
 384
 385                 if (cpu->initialized) {
 386                         continue;
 387                 }
 388
 389                 if (!start_cpu(cpu)) {
 390                         /* Record the error in cpu? */
 391                         printk_err("CPU 0x%02x would not start!\n",
 392                                 cpu->path.apic.apic_id);
 393                 }
 394 #if SERIAL_CPU_INIT == 1
 395   #if CONFIG_MAX_CPUS>2
 396                 udelay(10);
 397   #endif
 398 #endif
 399         }
 400
 401 }
 402
 403 static void wait_other_cpus_stop(struct bus *cpu_bus)
 404 {
 405         device_t cpu;
 406         int old_active_count, active_count;
 407         /* Now loop until the other cpus have finished initializing */
 408         old_active_count = 1;
 409         active_count = atomic_read(&active_cpus);
 410         while(active_count > 1) {
 411                 if (active_count != old_active_count) {
 412                         printk_info("Waiting for %d CPUS to stop\n", active_count - 1);
 413                         old_active_count = active_count;
 414                 }
 415                 udelay(10);
 416                 active_count = atomic_read(&active_cpus);
 417         }
 418         for(cpu = cpu_bus->children; cpu; cpu = cpu->sibling) {
 419                 if (cpu->path.type != DEVICE_PATH_APIC) {
 420                         continue;
 421                 }
 422                 if (!cpu->initialized) {
 423                         printk_err("CPU 0x%02x did not initialize!\n",
 424                                 cpu->path.apic.apic_id);
 425                 }
 426         }
 427         printk_debug("All AP CPUs stopped\n");
 428 }
 429
 430 #else /* CONFIG_SMP */
 431 #define initialize_other_cpus(root) do {} while(0)
 432 #endif /* CONFIG_SMP */
 433
 434 #if WAIT_BEFORE_CPUS_INIT==0
 435         #define cpus_ready_for_init() do {} while(0)
 436 #else
 437         void cpus_ready_for_init(void);
 438 #endif
 439
 440 #if HAVE_SMI_HANDLER
 441 void smm_init(void);
 442 #endif
 443
 444 void initialize_cpus(struct bus *cpu_bus)
 445 {
 446         struct device_path cpu_path;
 447         struct cpu_info *info;
 448
 449         /* Find the info struct for this cpu */
 450         info = cpu_info();
 451
 452 #if NEED_LAPIC == 1
 453         /* Ensure the local apic is enabled */
 454         enable_lapic();
 455
 456         /* Get the device path of the boot cpu */
 457         cpu_path.type           = DEVICE_PATH_APIC;
 458         cpu_path.apic.apic_id = lapicid();
 459 #else
 460         /* Get the device path of the boot cpu */
 461         cpu_path.type           = DEVICE_PATH_CPU;
 462         cpu_path.cpu.id       = 0;
 463 #endif
 464
 465         /* Find the device structure for the boot cpu */
 466         info->cpu = alloc_find_dev(cpu_bus, &cpu_path);
 467
 468 #if CONFIG_SMP == 1
 469         copy_secondary_start_to_1m_below(); // why here? In case some day we can start core1 in amd_sibling_init
 470 #endif
 471
 472 #if HAVE_SMI_HANDLER
 473         smm_init();
 474 #endif
 475
 476         cpus_ready_for_init();
 477
 478 #if CONFIG_SMP == 1
 479         #if SERIAL_CPU_INIT == 0
 480         /* start all aps at first, so we can init ECC all together */
 481         start_other_cpus(cpu_bus, info->cpu);
 482         #endif
 483 #endif
 484
 485         /* Initialize the bootstrap processor */
 486         cpu_initialize();
 487
 488 #if CONFIG_SMP == 1
 489         #if SERIAL_CPU_INIT == 1
 490         start_other_cpus(cpu_bus, info->cpu);
 491         #endif
 492
 493         /* Now wait the rest of the cpus stop*/
 494         wait_other_cpus_stop(cpu_bus);
 495 #endif
 496 }
 497