src/cpu/x86/lapic/lapic_cpu_init.c

   1 /*
   2         2005.12 yhlu add coreboot_ram cross the vga font buffer handling
   3         2005.12 yhlu add CONFIG_RAMBASE above 1M support for SMP
   4         2008.05 stepan add support for going back to sipi wait state
   5 */
   6
   7 #include <cpu/x86/lapic.h>
   8 #include <delay.h>
   9 #include <string.h>
  10 #include <console/console.h>
  11 #include <arch/hlt.h>
  12 #include <device/device.h>
  13 #include <device/path.h>
  14 #include <smp/atomic.h>
  15 #include <smp/spinlock.h>
  16 #include <cpu/cpu.h>
  17
  18 #if CONFIG_SMP == 1
  19
  20 #if CONFIG_RAMBASE >= 0x100000
  21 /* This is a lot more paranoid now, since Linux can NOT handle
  22  * being told there is a CPU when none exists. So any errors
  23  * will return 0, meaning no CPU.
  24  *
  25  * We actually handling that case by noting which cpus startup
  26  * and not telling anyone about the ones that dont.
  27  */
  28 static unsigned long get_valid_start_eip(unsigned long orig_start_eip)
  29 {
  30         return (unsigned long)orig_start_eip & 0xffff; // 16 bit to avoid 0xa0000
  31 }
  32 #endif
  33
  34 #if CONFIG_HAVE_ACPI_RESUME == 1
  35 char *lowmem_backup;
  36 char *lowmem_backup_ptr;
  37 int  lowmem_backup_size;
  38 #endif
  39
  40 extern char _secondary_start[];
  41
  42 static void copy_secondary_start_to_1m_below(void)
  43 {
  44 #if CONFIG_RAMBASE >= 0x100000
  45         extern char _secondary_start_end[];
  46         unsigned long code_size;
  47         unsigned long start_eip;
  48
  49         /* _secondary_start need to be masked 20 above bit, because 16 bit code in secondary.S
  50            Also We need to copy the _secondary_start to the below 1M region
  51         */
  52         start_eip = get_valid_start_eip((unsigned long)_secondary_start);
  53         code_size = (unsigned long)_secondary_start_end - (unsigned long)_secondary_start;
  54
  55 #if CONFIG_HAVE_ACPI_RESUME == 1
  56         /* need to save it for RAM resume */
  57         lowmem_backup_size = code_size;
  58         lowmem_backup = malloc(code_size);
  59         lowmem_backup_ptr = (char *)start_eip;
  60
  61         if (lowmem_backup == NULL)
  62                 die("Out of backup memory\n");
  63
  64         memcpy(lowmem_backup, lowmem_backup_ptr, lowmem_backup_size);
  65 #endif
  66         /* copy the _secondary_start to the ram below 1M*/
  67         memcpy((unsigned char *)start_eip, (unsigned char *)_secondary_start, code_size);
  68
  69         printk(BIOS_DEBUG, "start_eip=0x%08lx, offset=0x%08lx, code_size=0x%08lx\n", start_eip, ((unsigned long)_secondary_start - start_eip), code_size);
  70 #endif
  71 }
  72
  73 static int lapic_start_cpu(unsigned long apicid)
  74 {
  75         int timeout;
  76         unsigned long send_status, accept_status, start_eip;
  77         int j, num_starts, maxlvt;
  78
  79         /*
  80          * Starting actual IPI sequence...
  81          */
  82
  83         printk(BIOS_SPEW, "Asserting INIT.\n");
  84
  85         /*
  86          * Turn INIT on target chip
  87          */
  88         lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
  89
  90         /*
  91          * Send IPI
  92          */
  93
  94         lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT
  95                                 | LAPIC_DM_INIT);
  96
  97         printk(BIOS_SPEW, "Waiting for send to finish...\n");
  98         timeout = 0;
  99         do {
 100                 printk(BIOS_SPEW, "+");
 101                 udelay(100);
 102                 send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
 103         } while (send_status && (timeout++ < 1000));
 104         if (timeout >= 1000) {
 105                 printk(BIOS_ERR, "CPU %ld: First apic write timed out. Disabling\n",
 106                          apicid);
 107                 // too bad.
 108                 printk(BIOS_ERR, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR));
 109                 if (lapic_read(LAPIC_ESR)) {
 110                         printk(BIOS_ERR, "Try to reset ESR\n");
 111                         lapic_write_around(LAPIC_ESR, 0);
 112                         printk(BIOS_ERR, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR));
 113                 }
 114                 return 0;
 115         }
 116 #if !defined (CONFIG_CPU_AMD_MODEL_10XXX) && !defined (CONFIG_CPU_AMD_MODEL_14XXX)
 117         mdelay(10);
 118 #endif
 119
 120         printk(BIOS_SPEW, "Deasserting INIT.\n");
 121
 122         /* Target chip */
 123         lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
 124
 125         /* Send IPI */
 126         lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT);
 127
 128         printk(BIOS_SPEW, "Waiting for send to finish...\n");
 129         timeout = 0;
 130         do {
 131                 printk(BIOS_SPEW, "+");
 132                 udelay(100);
 133                 send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
 134         } while (send_status && (timeout++ < 1000));
 135         if (timeout >= 1000) {
 136                 printk(BIOS_ERR, "CPU %ld: Second apic write timed out. Disabling\n",
 137                          apicid);
 138                 // too bad.
 139                 return 0;
 140         }
 141
 142 #if CONFIG_RAMBASE >= 0x100000
 143         start_eip = get_valid_start_eip((unsigned long)_secondary_start);
 144 #else
 145         start_eip = (unsigned long)_secondary_start;
 146 #endif
 147
 148 #if !defined (CONFIG_CPU_AMD_MODEL_10XXX) && !defined (CONFIG_CPU_AMD_MODEL_14XXX)
 149         num_starts = 2;
 150 #else
 151         num_starts = 1;
 152 #endif
 153
 154         /*
 155          * Run STARTUP IPI loop.
 156          */
 157         printk(BIOS_SPEW, "#startup loops: %d.\n", num_starts);
 158
 159         maxlvt = 4;
 160
 161         for (j = 1; j <= num_starts; j++) {
 162                 printk(BIOS_SPEW, "Sending STARTUP #%d to %lu.\n", j, apicid);
 163                 lapic_read_around(LAPIC_SPIV);
 164                 lapic_write(LAPIC_ESR, 0);
 165                 lapic_read(LAPIC_ESR);
 166                 printk(BIOS_SPEW, "After apic_write.\n");
 167
 168                 /*
 169                  * STARTUP IPI
 170                  */
 171
 172                 /* Target chip */
 173                 lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
 174
 175                 /* Boot on the stack */
 176                 /* Kick the second */
 177                 lapic_write_around(LAPIC_ICR, LAPIC_DM_STARTUP
 178                                         | (start_eip >> 12));
 179
 180                 /*
 181                  * Give the other CPU some time to accept the IPI.
 182                  */
 183                 udelay(300);
 184
 185                 printk(BIOS_SPEW, "Startup point 1.\n");
 186
 187                 printk(BIOS_SPEW, "Waiting for send to finish...\n");
 188                 timeout = 0;
 189                 do {
 190                         printk(BIOS_SPEW, "+");
 191                         udelay(100);
 192                         send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
 193                 } while (send_status && (timeout++ < 1000));
 194
 195                 /*
 196                  * Give the other CPU some time to accept the IPI.
 197                  */
 198                 udelay(200);
 199                 /*
 200                  * Due to the Pentium erratum 3AP.
 201                  */
 202                 if (maxlvt > 3) {
 203                         lapic_read_around(LAPIC_SPIV);
 204                         lapic_write(LAPIC_ESR, 0);
 205                 }
 206                 accept_status = (lapic_read(LAPIC_ESR) & 0xEF);
 207                 if (send_status || accept_status)
 208                         break;
 209         }
 210         printk(BIOS_SPEW, "After Startup.\n");
 211         if (send_status)
 212                 printk(BIOS_WARNING, "APIC never delivered???\n");
 213         if (accept_status)
 214                 printk(BIOS_WARNING, "APIC delivery error (%lx).\n", accept_status);
 215         if (send_status || accept_status)
 216                 return 0;
 217         return 1;
 218 }
 219
 220 /* Number of cpus that are currently running in coreboot */
 221 static atomic_t active_cpus = ATOMIC_INIT(1);
 222
 223 /* start_cpu_lock covers last_cpu_index and secondary_stack.
 224  * Only starting one cpu at a time let's me remove the logic
 225  * for select the stack from assembly language.
 226  *
 227  * In addition communicating by variables to the cpu I
 228  * am starting allows me to veryify it has started before
 229  * start_cpu returns.
 230  */
 231
 232 static spinlock_t start_cpu_lock = SPIN_LOCK_UNLOCKED;
 233 static unsigned last_cpu_index = 0;
 234 volatile unsigned long secondary_stack;
 235
 236 int start_cpu(device_t cpu)
 237 {
 238         extern unsigned char _estack[];
 239         struct cpu_info *info;
 240         unsigned long stack_end;
 241         unsigned long apicid;
 242         unsigned long index;
 243         unsigned long count;
 244         int result;
 245
 246         spin_lock(&start_cpu_lock);
 247
 248         /* Get the cpu's apicid */
 249         apicid = cpu->path.apic.apic_id;
 250
 251         /* Get an index for the new processor */
 252         index = ++last_cpu_index;
 253
 254         /* Find end of the new processors stack */
 255         stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - sizeof(struct cpu_info);
 256
 257         /* Record the index and which cpu structure we are using */
 258         info = (struct cpu_info *)stack_end;
 259         info->index = index;
 260         info->cpu   = cpu;
 261
 262         /* Advertise the new stack to start_cpu */
 263         secondary_stack = stack_end;
 264
 265         /* Until the cpu starts up report the cpu is not enabled */
 266         cpu->enabled = 0;
 267         cpu->initialized = 0;
 268
 269         /* Start the cpu */
 270         result = lapic_start_cpu(apicid);
 271
 272         if (result) {
 273                 result = 0;
 274                 /* Wait 1s or until the new the new cpu calls in */
 275                 for(count = 0; count < 100000 ; count++) {
 276                         if (secondary_stack == 0) {
 277                                 result = 1;
 278                                 break;
 279                         }
 280                         udelay(10);
 281                 }
 282         }
 283         secondary_stack = 0;
 284         spin_unlock(&start_cpu_lock);
 285         return result;
 286 }
 287
 288 #if CONFIG_AP_IN_SIPI_WAIT == 1
 289 /**
 290  * Normally this function is defined in lapic.h as an always inline function
 291  * that just keeps the CPU in a hlt() loop. This does not work on all CPUs.
 292  * I think all hyperthreading CPUs might need this version, but I could only
 293  * verify this on the Intel Core Duo
 294  */
 295 void stop_this_cpu(void)
 296 {
 297         int timeout;
 298         unsigned long send_status;
 299         unsigned long id;
 300
 301         id = lapic_read(LAPIC_ID) >> 24;
 302
 303         printk(BIOS_DEBUG, "CPU %ld going down...\n", id);
 304
 305         /* send an LAPIC INIT to myself */
 306         lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(id));
 307         lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT | LAPIC_DM_INIT);
 308
 309         /* wait for the ipi send to finish */
 310 #if 0
 311         // When these two printk(BIOS_SPEW, ...) calls are not removed, the
 312         // machine will hang when log level is SPEW. Why?
 313         printk(BIOS_SPEW, "Waiting for send to finish...\n");
 314 #endif
 315         timeout = 0;
 316         do {
 317 #if 0
 318                 printk(BIOS_SPEW, "+");
 319 #endif
 320                 udelay(100);
 321                 send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
 322         } while (send_status && (timeout++ < 1000));
 323         if (timeout >= 1000) {
 324                 printk(BIOS_ERR, "timed out\n");
 325         }
 326         mdelay(10);
 327
 328         printk(BIOS_SPEW, "Deasserting INIT.\n");
 329         /* Deassert the LAPIC INIT */
 330         lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(id));
 331         lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT);
 332
 333         printk(BIOS_SPEW, "Waiting for send to finish...\n");
 334         timeout = 0;
 335         do {
 336                 printk(BIOS_SPEW, "+");
 337                 udelay(100);
 338                 send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
 339         } while (send_status && (timeout++ < 1000));
 340         if (timeout >= 1000) {
 341                 printk(BIOS_ERR, "timed out\n");
 342         }
 343
 344         while(1) {
 345                 hlt();
 346         }
 347 }
 348 #endif
 349
 350 /* C entry point of secondary cpus */
 351 void secondary_cpu_init(void)
 352 {
 353         atomic_inc(&active_cpus);
 354 #if CONFIG_SERIAL_CPU_INIT == 1
 355   #if CONFIG_MAX_CPUS>2
 356         spin_lock(&start_cpu_lock);
 357   #endif
 358 #endif
 359         cpu_initialize();
 360 #if CONFIG_SERIAL_CPU_INIT == 1
 361   #if CONFIG_MAX_CPUS>2
 362         spin_unlock(&start_cpu_lock);
 363   #endif
 364 #endif
 365
 366         atomic_dec(&active_cpus);
 367
 368         stop_this_cpu();
 369 }
 370
 371 static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu)
 372 {
 373         device_t cpu;
 374         /* Loop through the cpus once getting them started */
 375
 376         for(cpu = cpu_bus->children; cpu ; cpu = cpu->sibling) {
 377                 if (cpu->path.type != DEVICE_PATH_APIC) {
 378                         continue;
 379                 }
 380         #if CONFIG_SERIAL_CPU_INIT == 0
 381                 if(cpu==bsp_cpu) {
 382                         continue;
 383                 }
 384         #endif
 385
 386                 if (!cpu->enabled) {
 387                         continue;
 388                 }
 389
 390                 if (cpu->initialized) {
 391                         continue;
 392                 }
 393
 394                 if (!start_cpu(cpu)) {
 395                         /* Record the error in cpu? */
 396                         printk(BIOS_ERR, "CPU 0x%02x would not start!\n",
 397                                 cpu->path.apic.apic_id);
 398                 }
 399 #if CONFIG_SERIAL_CPU_INIT == 1
 400   #if CONFIG_MAX_CPUS>2
 401                 udelay(10);
 402   #endif
 403 #endif
 404         }
 405
 406 }
 407
 408 static void wait_other_cpus_stop(struct bus *cpu_bus)
 409 {
 410         device_t cpu;
 411         int old_active_count, active_count;
 412         /* Now loop until the other cpus have finished initializing */
 413         old_active_count = 1;
 414         active_count = atomic_read(&active_cpus);
 415         while(active_count > 1) {
 416                 if (active_count != old_active_count) {
 417                         printk(BIOS_INFO, "Waiting for %d CPUS to stop\n", active_count - 1);
 418                         old_active_count = active_count;
 419                 }
 420                 udelay(10);
 421                 active_count = atomic_read(&active_cpus);
 422         }
 423         for(cpu = cpu_bus->children; cpu; cpu = cpu->sibling) {
 424                 if (cpu->path.type != DEVICE_PATH_APIC) {
 425                         continue;
 426                 }
 427                 if (!cpu->initialized) {
 428                         printk(BIOS_ERR, "CPU 0x%02x did not initialize!\n",
 429                                 cpu->path.apic.apic_id);
 430                 }
 431         }
 432         printk(BIOS_DEBUG, "All AP CPUs stopped\n");
 433 }
 434
 435 #else /* CONFIG_SMP */
 436 #define initialize_other_cpus(root) do {} while(0)
 437 #endif /* CONFIG_SMP */
 438
 439 void initialize_cpus(struct bus *cpu_bus)
 440 {
 441         struct device_path cpu_path;
 442         struct cpu_info *info;
 443
 444         /* Find the info struct for this cpu */
 445         info = cpu_info();
 446
 447 #if NEED_LAPIC == 1
 448         /* Ensure the local apic is enabled */
 449         enable_lapic();
 450
 451         /* Get the device path of the boot cpu */
 452         cpu_path.type           = DEVICE_PATH_APIC;
 453         cpu_path.apic.apic_id = lapicid();
 454 #else
 455         /* Get the device path of the boot cpu */
 456         cpu_path.type           = DEVICE_PATH_CPU;
 457         cpu_path.cpu.id       = 0;
 458 #endif
 459
 460         /* Find the device structure for the boot cpu */
 461         info->cpu = alloc_find_dev(cpu_bus, &cpu_path);
 462
 463 #if CONFIG_SMP == 1
 464         copy_secondary_start_to_1m_below(); // why here? In case some day we can start core1 in amd_sibling_init
 465 #endif
 466
 467 #if CONFIG_HAVE_SMI_HANDLER
 468         smm_init();
 469 #endif
 470
 471         cpus_ready_for_init();
 472
 473 #if CONFIG_SMP == 1
 474         #if CONFIG_SERIAL_CPU_INIT == 0
 475         /* start all aps at first, so we can init ECC all together */
 476         start_other_cpus(cpu_bus, info->cpu);
 477         #endif
 478 #endif
 479
 480         /* Initialize the bootstrap processor */
 481         cpu_initialize();
 482
 483 #if CONFIG_SMP == 1
 484         #if CONFIG_SERIAL_CPU_INIT == 1
 485         start_other_cpus(cpu_bus, info->cpu);
 486         #endif
 487
 488         /* Now wait the rest of the cpus stop*/
 489         wait_other_cpus_stop(cpu_bus);
 490 #endif
 491 }
 492