src/cpu/x86/lapic/lapic_cpu_init.c

   1 /*
   2         2005.12 yhlu add coreboot_ram cross the vga font buffer handling
   3         2005.12 yhlu add CONFIG_RAMBASE above 1M support for SMP
   4         2008.05 stepan add support for going back to sipi wait state
   5 */
   6
   7 #include <cpu/x86/lapic.h>
   8 #include <delay.h>
   9 #include <string.h>
  10 #include <console/console.h>
  11 #include <arch/hlt.h>
  12 #include <device/device.h>
  13 #include <device/path.h>
  14 #include <smp/atomic.h>
  15 #include <smp/spinlock.h>
  16 #include <cpu/cpu.h>
  17
  18 #if CONFIG_SMP == 1
  19 /* This is a lot more paranoid now, since Linux can NOT handle
  20  * being told there is a CPU when none exists. So any errors
  21  * will return 0, meaning no CPU.
  22  *
  23  * We actually handling that case by noting which cpus startup
  24  * and not telling anyone about the ones that dont.
  25  */
  26 static unsigned long get_valid_start_eip(unsigned long orig_start_eip)
  27 {
  28         return (unsigned long)orig_start_eip & 0xffff; // 16 bit to avoid 0xa0000
  29 }
  30
  31 #if CONFIG_HAVE_ACPI_RESUME == 1
  32 char *lowmem_backup;
  33 char *lowmem_backup_ptr;
  34 int  lowmem_backup_size;
  35 #endif
  36
  37 extern char _secondary_start[];
  38
  39 static void copy_secondary_start_to_1m_below(void)
  40 {
  41         extern char _secondary_start_end[];
  42         unsigned long code_size;
  43         unsigned long start_eip;
  44
  45         /* _secondary_start need to be masked 20 above bit, because 16 bit code in secondary.S
  46            Also We need to copy the _secondary_start to the below 1M region
  47         */
  48         start_eip = get_valid_start_eip((unsigned long)_secondary_start);
  49         code_size = (unsigned long)_secondary_start_end - (unsigned long)_secondary_start;
  50
  51 #if CONFIG_HAVE_ACPI_RESUME == 1
  52         /* need to save it for RAM resume */
  53         lowmem_backup_size = code_size;
  54         lowmem_backup = malloc(code_size);
  55         lowmem_backup_ptr = (char *)start_eip;
  56
  57         if (lowmem_backup == NULL)
  58                 die("Out of backup memory\n");
  59
  60         memcpy(lowmem_backup, lowmem_backup_ptr, lowmem_backup_size);
  61 #endif
  62         /* copy the _secondary_start to the ram below 1M*/
  63         memcpy((unsigned char *)start_eip, (unsigned char *)_secondary_start, code_size);
  64
  65         printk(BIOS_DEBUG, "start_eip=0x%08lx, offset=0x%08lx, code_size=0x%08lx\n", start_eip, ((unsigned long)_secondary_start - start_eip), code_size);
  66 }
  67
  68 static int lapic_start_cpu(unsigned long apicid)
  69 {
  70         int timeout;
  71         unsigned long send_status, accept_status, start_eip;
  72         int j, num_starts, maxlvt;
  73
  74         /*
  75          * Starting actual IPI sequence...
  76          */
  77
  78         printk(BIOS_SPEW, "Asserting INIT.\n");
  79
  80         /*
  81          * Turn INIT on target chip
  82          */
  83         lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
  84
  85         /*
  86          * Send IPI
  87          */
  88
  89         lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT
  90                                 | LAPIC_DM_INIT);
  91
  92         printk(BIOS_SPEW, "Waiting for send to finish...\n");
  93         timeout = 0;
  94         do {
  95                 printk(BIOS_SPEW, "+");
  96                 udelay(100);
  97                 send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
  98         } while (send_status && (timeout++ < 1000));
  99         if (timeout >= 1000) {
 100                 printk(BIOS_ERR, "CPU %ld: First apic write timed out. Disabling\n",
 101                          apicid);
 102                 // too bad.
 103                 printk(BIOS_ERR, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR));
 104                 if (lapic_read(LAPIC_ESR)) {
 105                         printk(BIOS_ERR, "Try to reset ESR\n");
 106                         lapic_write_around(LAPIC_ESR, 0);
 107                         printk(BIOS_ERR, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR));
 108                 }
 109                 return 0;
 110         }
 111 #if !defined (CONFIG_CPU_AMD_MODEL_10XXX) && !defined (CONFIG_CPU_AMD_MODEL_14XXX)
 112         mdelay(10);
 113 #endif
 114
 115         printk(BIOS_SPEW, "Deasserting INIT.\n");
 116
 117         /* Target chip */
 118         lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
 119
 120         /* Send IPI */
 121         lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT);
 122
 123         printk(BIOS_SPEW, "Waiting for send to finish...\n");
 124         timeout = 0;
 125         do {
 126                 printk(BIOS_SPEW, "+");
 127                 udelay(100);
 128                 send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
 129         } while (send_status && (timeout++ < 1000));
 130         if (timeout >= 1000) {
 131                 printk(BIOS_ERR, "CPU %ld: Second apic write timed out. Disabling\n",
 132                          apicid);
 133                 // too bad.
 134                 return 0;
 135         }
 136
 137         start_eip = get_valid_start_eip((unsigned long)_secondary_start);
 138
 139 #if !defined (CONFIG_CPU_AMD_MODEL_10XXX) && !defined (CONFIG_CPU_AMD_MODEL_14XXX)
 140         num_starts = 2;
 141 #else
 142         num_starts = 1;
 143 #endif
 144
 145         /*
 146          * Run STARTUP IPI loop.
 147          */
 148         printk(BIOS_SPEW, "#startup loops: %d.\n", num_starts);
 149
 150         maxlvt = 4;
 151
 152         for (j = 1; j <= num_starts; j++) {
 153                 printk(BIOS_SPEW, "Sending STARTUP #%d to %lu.\n", j, apicid);
 154                 lapic_read_around(LAPIC_SPIV);
 155                 lapic_write(LAPIC_ESR, 0);
 156                 lapic_read(LAPIC_ESR);
 157                 printk(BIOS_SPEW, "After apic_write.\n");
 158
 159                 /*
 160                  * STARTUP IPI
 161                  */
 162
 163                 /* Target chip */
 164                 lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
 165
 166                 /* Boot on the stack */
 167                 /* Kick the second */
 168                 lapic_write_around(LAPIC_ICR, LAPIC_DM_STARTUP
 169                                         | (start_eip >> 12));
 170
 171                 /*
 172                  * Give the other CPU some time to accept the IPI.
 173                  */
 174                 udelay(300);
 175
 176                 printk(BIOS_SPEW, "Startup point 1.\n");
 177
 178                 printk(BIOS_SPEW, "Waiting for send to finish...\n");
 179                 timeout = 0;
 180                 do {
 181                         printk(BIOS_SPEW, "+");
 182                         udelay(100);
 183                         send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
 184                 } while (send_status && (timeout++ < 1000));
 185
 186                 /*
 187                  * Give the other CPU some time to accept the IPI.
 188                  */
 189                 udelay(200);
 190                 /*
 191                  * Due to the Pentium erratum 3AP.
 192                  */
 193                 if (maxlvt > 3) {
 194                         lapic_read_around(LAPIC_SPIV);
 195                         lapic_write(LAPIC_ESR, 0);
 196                 }
 197                 accept_status = (lapic_read(LAPIC_ESR) & 0xEF);
 198                 if (send_status || accept_status)
 199                         break;
 200         }
 201         printk(BIOS_SPEW, "After Startup.\n");
 202         if (send_status)
 203                 printk(BIOS_WARNING, "APIC never delivered???\n");
 204         if (accept_status)
 205                 printk(BIOS_WARNING, "APIC delivery error (%lx).\n", accept_status);
 206         if (send_status || accept_status)
 207                 return 0;
 208         return 1;
 209 }
 210
 211 /* Number of cpus that are currently running in coreboot */
 212 static atomic_t active_cpus = ATOMIC_INIT(1);
 213
 214 /* start_cpu_lock covers last_cpu_index and secondary_stack.
 215  * Only starting one cpu at a time let's me remove the logic
 216  * for select the stack from assembly language.
 217  *
 218  * In addition communicating by variables to the cpu I
 219  * am starting allows me to veryify it has started before
 220  * start_cpu returns.
 221  */
 222
 223 static spinlock_t start_cpu_lock = SPIN_LOCK_UNLOCKED;
 224 static unsigned last_cpu_index = 0;
 225 volatile unsigned long secondary_stack;
 226
 227 int start_cpu(device_t cpu)
 228 {
 229         extern unsigned char _estack[];
 230         struct cpu_info *info;
 231         unsigned long stack_end;
 232         unsigned long apicid;
 233         unsigned long index;
 234         unsigned long count;
 235         int result;
 236
 237         spin_lock(&start_cpu_lock);
 238
 239         /* Get the cpu's apicid */
 240         apicid = cpu->path.apic.apic_id;
 241
 242         /* Get an index for the new processor */
 243         index = ++last_cpu_index;
 244
 245         /* Find end of the new processors stack */
 246         stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - sizeof(struct cpu_info);
 247
 248         /* Record the index and which cpu structure we are using */
 249         info = (struct cpu_info *)stack_end;
 250         info->index = index;
 251         info->cpu   = cpu;
 252
 253         /* Advertise the new stack to start_cpu */
 254         secondary_stack = stack_end;
 255
 256         /* Until the cpu starts up report the cpu is not enabled */
 257         cpu->enabled = 0;
 258         cpu->initialized = 0;
 259
 260         /* Start the cpu */
 261         result = lapic_start_cpu(apicid);
 262
 263         if (result) {
 264                 result = 0;
 265                 /* Wait 1s or until the new cpu calls in */
 266                 for(count = 0; count < 100000 ; count++) {
 267                         if (secondary_stack == 0) {
 268                                 result = 1;
 269                                 break;
 270                         }
 271                         udelay(10);
 272                 }
 273         }
 274         secondary_stack = 0;
 275         spin_unlock(&start_cpu_lock);
 276         return result;
 277 }
 278
 279 #if CONFIG_AP_IN_SIPI_WAIT == 1
 280
 281 /**
 282  * Sending INIT IPI to self is equivalent of asserting #INIT with a bit of delay.
 283  * An undefined number of instruction cycles will complete. All global locks
 284  * must be released before INIT IPI and no printk is allowed after this.
 285  * De-asserting INIT IPI is a no-op on later Intel CPUs.
 286  *
 287  * If you set DEBUG_HALT_SELF to 1, printk's after INIT IPI are enabled
 288  * but running thread may halt without releasing the lock and effectively
 289  * deadlock other CPUs.
 290  */
 291 #define DEBUG_HALT_SELF 0
 292
 293 /**
 294  * Normally this function is defined in lapic.h as an always inline function
 295  * that just keeps the CPU in a hlt() loop. This does not work on all CPUs.
 296  * I think all hyperthreading CPUs might need this version, but I could only
 297  * verify this on the Intel Core Duo
 298  */
 299 void stop_this_cpu(void)
 300 {
 301         int timeout;
 302         unsigned long send_status;
 303         unsigned long id;
 304
 305         id = lapic_read(LAPIC_ID) >> 24;
 306
 307         printk(BIOS_DEBUG, "CPU %ld going down...\n", id);
 308
 309         /* send an LAPIC INIT to myself */
 310         lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(id));
 311         lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT | LAPIC_DM_INIT);
 312
 313         /* wait for the ipi send to finish */
 314 #if DEBUG_HALT_SELF
 315         printk(BIOS_SPEW, "Waiting for send to finish...\n");
 316 #endif
 317         timeout = 0;
 318         do {
 319 #if DEBUG_HALT_SELF
 320                 printk(BIOS_SPEW, "+");
 321 #endif
 322                 udelay(100);
 323                 send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
 324         } while (send_status && (timeout++ < 1000));
 325         if (timeout >= 1000) {
 326 #if DEBUG_HALT_SELF
 327                 printk(BIOS_ERR, "timed out\n");
 328 #endif
 329         }
 330         mdelay(10);
 331
 332 #if DEBUG_HALT_SELF
 333         printk(BIOS_SPEW, "Deasserting INIT.\n");
 334 #endif
 335         /* Deassert the LAPIC INIT */
 336         lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(id));
 337         lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT);
 338
 339 #if DEBUG_HALT_SELF
 340         printk(BIOS_SPEW, "Waiting for send to finish...\n");
 341 #endif
 342         timeout = 0;
 343         do {
 344 #if DEBUG_HALT_SELF
 345                 printk(BIOS_SPEW, "+");
 346 #endif
 347                 udelay(100);
 348                 send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
 349         } while (send_status && (timeout++ < 1000));
 350         if (timeout >= 1000) {
 351 #if DEBUG_HALT_SELF
 352                 printk(BIOS_ERR, "timed out\n");
 353 #endif
 354         }
 355
 356         while(1) {
 357                 hlt();
 358         }
 359 }
 360 #endif
 361
 362 #ifdef __SSE3__
 363 static __inline__ __attribute__((always_inline)) unsigned long readcr4(void)
 364 {
 365         unsigned long value;
 366         __asm__ __volatile__ (
 367                         "mov %%cr4, %[value]"
 368                         : [value] "=a" (value));
 369         return value;
 370 }
 371
 372 static __inline__ __attribute__((always_inline)) void writecr4(unsigned long Data)
 373 {
 374         __asm__ __volatile__ (
 375                         "mov %%eax, %%cr4"
 376                         :
 377                         : "a" (Data)
 378                         );
 379 }
 380 #endif
 381
 382 /* C entry point of secondary cpus */
 383 void secondary_cpu_init(void)
 384 {
 385         atomic_inc(&active_cpus);
 386 #if CONFIG_SERIAL_CPU_INIT == 1
 387   #if CONFIG_MAX_CPUS>2
 388         spin_lock(&start_cpu_lock);
 389   #endif
 390 #endif
 391
 392 #ifdef __SSE3__
 393         /*
 394          * Seems that CR4 was cleared when AP start via lapic_start_cpu()
 395          * Turn on CR4.OSFXSR and CR4.OSXMMEXCPT when SSE options enabled
 396          */
 397         u32 cr4_val;
 398         cr4_val = readcr4();
 399         cr4_val |= (1 << 9 | 1 << 10);
 400         writecr4(cr4_val);
 401 #endif
 402         cpu_initialize();
 403 #if CONFIG_SERIAL_CPU_INIT == 1
 404   #if CONFIG_MAX_CPUS>2
 405         spin_unlock(&start_cpu_lock);
 406   #endif
 407 #endif
 408
 409         atomic_dec(&active_cpus);
 410
 411         stop_this_cpu();
 412 }
 413
 414 static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu)
 415 {
 416         device_t cpu;
 417         /* Loop through the cpus once getting them started */
 418
 419         for(cpu = cpu_bus->children; cpu ; cpu = cpu->sibling) {
 420                 if (cpu->path.type != DEVICE_PATH_APIC) {
 421                         continue;
 422                 }
 423         #if CONFIG_SERIAL_CPU_INIT == 0
 424                 if(cpu==bsp_cpu) {
 425                         continue;
 426                 }
 427         #endif
 428
 429                 if (!cpu->enabled) {
 430                         continue;
 431                 }
 432
 433                 if (cpu->initialized) {
 434                         continue;
 435                 }
 436
 437                 if (!start_cpu(cpu)) {
 438                         /* Record the error in cpu? */
 439                         printk(BIOS_ERR, "CPU 0x%02x would not start!\n",
 440                                 cpu->path.apic.apic_id);
 441                 }
 442 #if CONFIG_SERIAL_CPU_INIT == 1
 443   #if CONFIG_MAX_CPUS>2
 444                 udelay(10);
 445   #endif
 446 #endif
 447         }
 448
 449 }
 450
 451 static void wait_other_cpus_stop(struct bus *cpu_bus)
 452 {
 453         device_t cpu;
 454         int old_active_count, active_count;
 455         /* Now loop until the other cpus have finished initializing */
 456         old_active_count = 1;
 457         active_count = atomic_read(&active_cpus);
 458         while(active_count > 1) {
 459                 if (active_count != old_active_count) {
 460                         printk(BIOS_INFO, "Waiting for %d CPUS to stop\n", active_count - 1);
 461                         old_active_count = active_count;
 462                 }
 463                 udelay(10);
 464                 active_count = atomic_read(&active_cpus);
 465         }
 466         for(cpu = cpu_bus->children; cpu; cpu = cpu->sibling) {
 467                 if (cpu->path.type != DEVICE_PATH_APIC) {
 468                         continue;
 469                 }
 470                 if (!cpu->initialized) {
 471                         printk(BIOS_ERR, "CPU 0x%02x did not initialize!\n",
 472                                 cpu->path.apic.apic_id);
 473                 }
 474         }
 475         printk(BIOS_DEBUG, "All AP CPUs stopped\n");
 476 }
 477
 478 #else /* CONFIG_SMP */
 479 #define initialize_other_cpus(root) do {} while(0)
 480 #endif /* CONFIG_SMP */
 481
 482 void initialize_cpus(struct bus *cpu_bus)
 483 {
 484         struct device_path cpu_path;
 485         struct cpu_info *info;
 486
 487         /* Find the info struct for this cpu */
 488         info = cpu_info();
 489
 490 #if NEED_LAPIC == 1
 491         /* Ensure the local apic is enabled */
 492         enable_lapic();
 493
 494         /* Get the device path of the boot cpu */
 495         cpu_path.type           = DEVICE_PATH_APIC;
 496         cpu_path.apic.apic_id = lapicid();
 497 #else
 498         /* Get the device path of the boot cpu */
 499         cpu_path.type           = DEVICE_PATH_CPU;
 500         cpu_path.cpu.id       = 0;
 501 #endif
 502
 503         /* Find the device structure for the boot cpu */
 504         info->cpu = alloc_find_dev(cpu_bus, &cpu_path);
 505
 506 #if CONFIG_SMP == 1
 507         copy_secondary_start_to_1m_below(); // why here? In case some day we can start core1 in amd_sibling_init
 508 #endif
 509
 510 #if CONFIG_HAVE_SMI_HANDLER
 511         smm_init();
 512 #endif
 513
 514         cpus_ready_for_init();
 515
 516 #if CONFIG_SMP == 1
 517         #if CONFIG_SERIAL_CPU_INIT == 0
 518         /* start all aps at first, so we can init ECC all together */
 519         start_other_cpus(cpu_bus, info->cpu);
 520         #endif
 521 #endif
 522
 523         /* Initialize the bootstrap processor */
 524         cpu_initialize();
 525
 526 #if CONFIG_SMP == 1
 527         #if CONFIG_SERIAL_CPU_INIT == 1
 528         start_other_cpus(cpu_bus, info->cpu);
 529         #endif
 530
 531         /* Now wait the rest of the cpus stop*/
 532         wait_other_cpus_stop(cpu_bus);
 533 #endif
 534 }
 535