2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
5 * Copyright (C) 2009 coresystems GmbH
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
24 #include <cpu/x86/msr.h>
25 #include <cpu/x86/lapic.h>
27 /* NOTE: This code uses global variables, so it can not be used during
31 static u32 timer_fsb = 0;
33 static int set_timer_fsb(void)
36 int core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 };
37 int core2_fsb[8] = { 266, 133, 200, 166, -1, 100, -1, -1 };
39 get_fms(&c, cpuid_eax(1));
43 switch (c.x86_model) {
44 case 0xe: /* Core Solo/Duo */
46 timer_fsb = core_fsb[rdmsr(0xcd).lo & 7];
49 case 0x17: /* Enhanced Core */
50 timer_fsb = core2_fsb[rdmsr(0xcd).lo & 7];
52 case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/
65 /* Set the apic timer to no interrupts and periodic mode */
66 lapic_write(LAPIC_LVTT, (LAPIC_LVT_TIMER_PERIODIC | LAPIC_LVT_MASKED));
68 /* Set the divider to 1, no divider */
69 lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1);
71 /* Set the initial counter to 0xffffffff */
72 lapic_write(LAPIC_TMICT, 0xffffffff);
74 /* Set FSB frequency to a reasonable value */
78 void udelay(u32 usecs)
80 u32 start, value, ticks;
85 /* Calculate the number of ticks to run, our FSB runs at timer_fsb Mhz */
86 ticks = usecs * timer_fsb;
87 start = lapic_read(LAPIC_TMCCT);
89 value = lapic_read(LAPIC_TMCCT);
90 } while((start - value) < ticks);