2 * This file is part of the coreboot project.
4 * (C) 2007-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 #include <device/device.h>
23 #include <console/console.h>
27 #include <cpu/x86/mtrr.h>
28 #include <cpu/x86/msr.h>
29 #include <cpu/x86/lapic.h>
30 #include <cpu/x86/cache.h>
32 #define MSR_IA32_PERF_STATUS 0x00000198
33 #define MSR_IA32_PERF_CTL 0x00000199
34 #define MSR_IA32_MISC_ENABLE 0x000001a0
36 static int c7a_speed_translation[] = {
38 0x0409, 0x0f13, // 400MHz, 844mV --> 1500MHz, 1.004V C7-M
39 0x0409, 0x1018, // 400MHz, 844mV --> 1600MHz, 1.084V
40 0x0409, 0x0c18, // 533MHz, 844mV --> 1600MHz, 1.084V
41 0x0409, 0x121c, // 400MHz, 844mV --> 1800MHz, 1.148V
42 0x0409, 0x0e1c, // 533MHz, 844mV --> 1860MHz, 1.148V
43 0x0409, 0x141f, // 400MHz, 844mV --> 2000MHz, 1.196V
44 0x0409, 0x0f1f, // 533MHz, 844mV --> 2000MHz, 1.196V
45 0x0406, 0x0a06, // 400MHz, 796mV --> 1000MHz, 796mV C7-M ULV
46 0x0406, 0x0a09, // 400MHz, 796mV --> 1000MHz, 844mV
47 0x0406, 0x0c09, // 400MHz, 796mV --> 1200MHz, 844mV
48 0x0406, 0x0f10, // 400MHz, 796mV --> 1500MHz, 956mV
51 static int c7d_speed_translation[] = {
53 0x0409, 0x1018, // 400MHz, 844mV --> 1600MHz, 1.084V C7-M
54 0x0409, 0x121f, // 400MHz, 844mV --> 1800MHz, 1.196V
55 0x0809, 0x121f, // 800MHz, 844mV --> 1800MHz, 1.196V
56 0x0409, 0x141f, // 400MHz, 844mV --> 2000MHz, 1.196V
57 0x0809, 0x141f, // 800MHz, 844mV --> 2000MHz, 1.196V
58 0x0406, 0x0806, // 400MHz, 796mV --> 800MHz, 796mV C7-M ULV
59 0x0406, 0x0a06, // 400MHz, 796mV --> 1000MHz, 796mV
60 0x0406, 0x0c09, // 400MHz, 796mV --> 1200MHz, 844mV
61 0x0806, 0x0c09, // 800MHz, 796mV --> 1200MHz, 844mV
62 0x0406, 0x0f10, // 400MHz, 796mV --> 1500MHz, 956mV
63 0x0806, 0x1010, // 800MHz, 796mV --> 1600MHz, 956mV
66 static void set_c7_speed(int model) {
67 int cnt, current, new, i;
69 printk(BIOS_DEBUG, "Enabling improved C7 clock and voltage.\n");
72 msr = rdmsr(MSR_IA32_MISC_ENABLE);
74 wrmsr(MSR_IA32_MISC_ENABLE, msr);
76 msr = rdmsr(MSR_IA32_PERF_STATUS);
78 printk(BIOS_INFO, "Voltage: %dmV (min %dmV; max %dmV)\n",
79 ((int)(msr.lo & 0xff) * 16 + 700),
80 ((int)((msr.hi >> 16) & 0xff) * 16 + 700),
81 ((int)(msr.hi & 0xff) * 16 + 700));
83 printk(BIOS_INFO, "CPU multiplier: %dx (min %dx; max %dx)\n",
84 (int)((msr.lo >> 8) & 0xff),
85 (int)((msr.hi >> 24) & 0xff), (int)((msr.hi >> 8) & 0xff));
87 printk(BIOS_DEBUG, " msr.lo = %x\n", msr.lo);
89 /* Wait while CPU is busy */
91 while (msr.lo & ((1 << 16) | (1 << 17))) {
93 msr = rdmsr(MSR_IA32_PERF_STATUS);
96 printk(BIOS_WARNING, "Could not update multiplier and voltage.\n");
101 current = msr.lo & 0xffff;
103 // Start out with no change.
107 for (i = 0; i < ARRAY_SIZE(c7a_speed_translation); i += 2) {
108 if ((c7a_speed_translation[i] == current) &&
109 ((c7a_speed_translation[i + 1] & 0xff00) ==
110 (msr.hi & 0xff00))) {
111 new = c7a_speed_translation[i + 1];
116 for (i = 0; i < ARRAY_SIZE(c7d_speed_translation); i += 2) {
117 if ((c7d_speed_translation[i] == current) &&
118 ((c7d_speed_translation[i + 1] & 0xff00) ==
119 (msr.hi & 0xff00))) {
120 new = c7d_speed_translation[i + 1];
125 print_info("CPU type not known, multiplier unchanged.\n");
130 printk(BIOS_DEBUG, " new msr.lo = %x\n", msr.lo);
132 wrmsr(MSR_IA32_PERF_CTL, msr);
134 /* Wait until the power transition ends */
138 msr = rdmsr(MSR_IA32_PERF_STATUS);
141 printk(BIOS_WARNING, "Error while updating multiplier and voltage\n");
144 } while (msr.lo & ((1 << 16) | (1 << 17)));
146 printk(BIOS_INFO, "Current voltage: %dmV\n", ((int)(msr.lo & 0xff) * 16 + 700));
147 printk(BIOS_INFO, "Current CPU multiplier: %dx\n", (int)((msr.lo >> 8) & 0xff));
150 static void model_c7_init(device_t dev)
153 struct cpuinfo_x86 c;
156 get_fms(&c, dev->device);
158 printk(BIOS_INFO, "Detected VIA ");
160 switch (c.x86_model) {
163 brand = (((msr.lo >> 2) ^ msr.lo) >> 18) & 3;
164 printk(BIOS_INFO, "Model A ");
168 brand = (((msr.lo >> 4) ^ (msr.lo >> 2))) & 0x000000ff;
169 printk(BIOS_INFO, "Model D ");
172 printk(BIOS_INFO, "Model Unknown ");
178 printk(BIOS_INFO, "C7-M\n");
181 printk(BIOS_INFO, "C7\n");
184 printk(BIOS_INFO, "Eden\n");
187 printk(BIOS_INFO, "C7-D\n");
190 printk(BIOS_INFO, "%02x (please report)\n", brand);
194 set_c7_speed(c.x86_model);
204 /* Set up Memory Type Range Registers */
208 /* Enable the local cpu apics */
212 static struct device_operations cpu_dev_ops = {
213 .init = model_c7_init,
216 /* Look in arch/x86/lib/cpu.c:cpu_initialize. If there is no CPU with an exact
217 * ID, the cpu mask (stepping) is masked out and the check is repeated. This
218 * allows us to keep the table significantly smaller.
221 static struct cpu_device_id cpu_table[] = {
222 {X86_VENDOR_CENTAUR, 0x06A0}, // VIA C7 Esther
223 {X86_VENDOR_CENTAUR, 0x06A9}, // VIA C7 Esther
224 {X86_VENDOR_CENTAUR, 0x06D0}, // VIA C7-M
228 static const struct cpu_driver driver __cpu_driver = {
230 .id_table = cpu_table,