2 * This file is part of the coreboot project.
4 * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
5 * Copyright (C) 2005 Eswar Nallusamy, LANL
6 * Copyright (C) 2005 Tyan
7 * (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
8 * Copyright (C) 2007 coresystems GmbH
9 * (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
10 * Copyright (C) 2007,2008 Carl-Daniel Hailfinger
11 * Copyright (C) 2008 VIA Technologies, Inc.
12 * (Written by Jason Zhao <jasonzhao@viatech.com.cn> for VIA)
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; version 2 of the License.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 #define CacheSize CONFIG_DCACHE_RAM_SIZE
29 #define CacheBase CONFIG_DCACHE_RAM_BASE
32 #include <cpu/x86/mtrr.h>
34 /* Save the BIST result */
45 /* Set the default memory type and enable fixed and variable MTRRs */
46 movl $MTRRdefType_MSR, %ecx
48 /* Enable Variable and Fixed MTRRs */
49 movl $0x00000c00, %eax
54 movl $fixed_mtrr_msr, %esi
59 jz clear_fixed_var_mtrr_out
65 jmp clear_fixed_var_mtrr
68 .long 0x250, 0x258, 0x259
69 .long 0x268, 0x269, 0x26A
70 .long 0x26B, 0x26C, 0x26D
74 .long 0x200, 0x201, 0x202, 0x203
75 .long 0x204, 0x205, 0x206, 0x207
76 .long 0x208, 0x209, 0x20A, 0x20B
77 .long 0x20C, 0x20D, 0x20E, 0x20F
78 .long 0x000 /* NULL, end of table */
80 clear_fixed_var_mtrr_out:
84 movl $(CacheBase|MTRR_TYPE_WRBACK),%eax
89 /* This assumes we never access addresses above 2^36 in CAR. */
91 movl $(~(CacheSize-1)|0x800),%eax
94 /* enable write base caching so we can do execute in place
100 #if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
101 #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
103 #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
105 movl $REAL_XIP_ROM_BASE, %eax
106 orl $MTRR_TYPE_WRBACK, %eax
111 movl $0x0000000f, %edx
112 movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
115 movl $MTRRdefType_MSR, %ecx
117 /* Enable Variable and Fixed MTRRs */
118 movl $0x00000800, %eax
122 andl $0x9fffffff, %eax
125 /* Read the range with lodsl*/
127 movl $CacheBase, %esi
129 movl $(CacheSize>>2), %ecx
132 movl $CacheBase, %esi
134 movl $(CacheSize >> 2), %ecx
136 /* 0x5c5c5c5c is a memory test pattern.
137 * TODO: Check if everything works with the zero pattern as well. */
139 xorl $0x5c5c5c5c,%eax
142 movl CONFIG_XIP_ROM_BASE, %esi
144 movl $(CONFIG_XIP_ROM_SIZE>>2), %ecx
147 /* The key point of this CAR code is C7 cache does not turn into
148 * "no fill" mode, which is not compatible with general CAR code.
151 movl $(CacheBase + CacheSize - 4), %eax
155 testok: movb $0x40,%al
174 /* Restore the BIST result */
177 /* We need to set ebp ? No need */
179 pushl %eax /* bist */
183 * TODO: Backup stack in CACHE_AS_RAM into MMX and SSE and after we
184 * get STACK up, we restore that. It is only needed if we
188 /* We don't need cache as ram for now on */
195 /* Set the default memory type and disable fixed and enable variable MTRRs */
197 //movl $MTRRdefType_MSR, %ecx
200 /* Enable Variable and Disable Fixed MTRRs */
201 movl $0x00000800, %eax
204 /* enable caching for first 1M using variable mtrr */
208 //movl $(0 | MTRR_TYPE_WRBACK), %eax
211 /* enable cache for 0-7ffff, 80000-9ffff, e0000-fffff;
212 * If 1M cacheable, then when S3 resume, there is stange color on
213 * screen for 2 sec. suppose problem of a0000-dfffff and cache.
214 * And in x86_setup_fixed_mtrrs()(mtrr.c), 0-256M is set cacheable.
218 movl $0x0000000f, %edx /* AMD 40 bit 0xff*/
219 movl $((~(( 0 + 0x80000) - 1)) | 0x800), %eax
224 movl $(0x80000 | 6), %eax
229 movl $0x0000000f, %edx /* AMD 40 bit 0xff*/
230 movl $((~(( 0 + 0x20000) - 1)) | 0x800), %eax
235 movl $(0xc0000 | 6), %eax
240 movl $0x0000000f, %edx /* AMD 40 bit 0xff*/
241 movl $((~(( 0 + 0x40000) - 1)) | 0x800), %eax
244 /* cache CONFIG_XIP_ROM_BASE-SIZE to speedup coreboot code */
247 movl $CONFIG_XIP_ROM_BASE,%eax
253 movl $CONFIG_XIP_ROM_SIZE,%eax
256 orl $(0 | 0x800), %eax
261 andl $0x9fffffff,%eax
265 /* clear boot_complete flag */
269 cld /* clear direction flag */
273 /* FIXME: These values might have to change for suspend-to-ram.
274 * the 0x00400000 was chosen as this is a place in memory that
275 * should exist in all contemporary configurations (ie. large
276 * enough RAM), but doesn't collide with anything coreboot does.
277 * Other than that, it's arbitrary.
280 movl $0x4000000, %esp