2 * This file is part of the coreboot project.
4 * Copyright (C) 2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
23 #include <console/console.h>
24 #include <arch/acpi.h>
25 #include <arch/acpigen.h>
27 #include <cpu/x86/msr.h>
28 #include <device/device.h>
30 // XXX: PSS table values for power consumption are for Merom only
32 static int determine_total_number_of_cores(void)
36 for(cpu = all_devices; cpu; cpu = cpu->next) {
37 if ((cpu->path.type != DEVICE_PATH_APIC) ||
38 (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) {
49 static int get_fsb(void)
51 u32 fsbcode=(rdmsr(0xcd).lo >> 4) & 7;
59 printk(BIOS_DEBUG, "Warning: No supported FSB frequency. Assuming 200MHz\n");
63 void generate_cpu_entries(void)
66 int coreID, cpuID, pcontrol_blk=0x510, plen=6;
68 int totalcores = determine_total_number_of_cores();
69 int cores_per_package = (cpuid_ebx(1)>>16) & 0xff;
70 int numcpus = totalcores/cores_per_package; // this assumes that all CPUs share the same layout
71 printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", numcpus, cores_per_package);
73 for (cpuID=1; cpuID <=numcpus; cpuID++) {
74 for (coreID=1; coreID<=cores_per_package; coreID++) {
79 len_pr = acpigen_write_processor((cpuID-1)*cores_per_package+coreID-1, pcontrol_blk, plen);
80 len_pr += acpigen_write_empty_PCT();
81 len_pr += acpigen_write_PSD_package(cpuID-1,cores_per_package,SW_ANY);
82 len_pr += acpigen_write_name("_PSS");
86 #define IA32_PLATFORM_ID 0x017
87 #define IA32_PERF_STS 0x198
88 msr = rdmsr(IA32_PERF_STS);
89 int busratio_min=(msr.lo >> 24) & 0x1f;
90 int busratio_max=(msr.hi >> (40-32)) & 0x1f;
91 int vid_min=msr.lo & 0x3f;
92 msr = rdmsr(IA32_PLATFORM_ID);
93 int vid_max=msr.lo & 0x3f;
94 int clock_max=get_fsb()*busratio_max;
95 int clock_min=get_fsb()*busratio_min;
96 printk(BIOS_DEBUG, "clocks between %d and %d MHz.\n", clock_min, clock_max);
97 #define MEROM_MIN_POWER 16000
98 #define MEROM_MAX_POWER 35000
99 int power_max=MEROM_MAX_POWER;
100 int power_min=MEROM_MIN_POWER;
102 int num_states=(busratio_max-busratio_min)/busratio_step;
103 while (num_states > max_states-1) {
107 printk(BIOS_DEBUG, "adding %x P-States between busratio %x and %x, incl. P0\n", num_states+1, busratio_min, busratio_max);
108 int vid_step=(vid_max-vid_min)/num_states;
109 int power_step=(power_max-power_min)/num_states;
110 int clock_step=(clock_max-clock_min)/num_states;
111 len_ps = acpigen_write_package(num_states+1); // for Super LFM, this must be increases by another one
112 len_ps += acpigen_write_PSS_package(clock_max /*mhz*/, power_max /*mW*/, 0 /*lat1*/, 0 /*lat2*/, (busratio_max<<8)|(vid_max) /*control*/, (busratio_max<<8)|(vid_max) /*status*/);
113 int current_busratio=busratio_min+((num_states-1)*busratio_step);
114 int current_vid=vid_min+((num_states-1)*vid_step);
115 int current_power=power_min+((num_states-1)*power_step);
116 int current_clock=clock_min+((num_states-1)*clock_step);
118 for (i=0;i<num_states; i++) {
119 len_ps += acpigen_write_PSS_package(current_clock /*mhz*/, current_power /*mW*/, 0 /*lat1*/, 0 /*lat2*/, (current_busratio<<8)|(current_vid) /*control*/, (current_busratio<<8)|(current_vid) /*status*/);
120 current_busratio -= busratio_step;
121 current_vid -= vid_step;
122 current_power -= power_step;
123 current_clock -= clock_step;
126 acpigen_patch_len(len_ps);
127 len_pr += acpigen_write_PPC(0);
130 acpigen_patch_len(len_pr);