2 * This file is part of the coreboot project.
4 * Copyright (C) 2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
23 #include <console/console.h>
24 #include <arch/acpi.h>
25 #include <arch/acpigen.h>
27 #include <cpu/x86/msr.h>
28 #include <cpu/intel/acpi.h>
29 #include <cpu/intel/speedstep.h>
30 #include <device/device.h>
32 // XXX: PSS table values for power consumption are for Merom only
34 static int determine_total_number_of_cores(void)
38 for(cpu = all_devices; cpu; cpu = cpu->next) {
39 if ((cpu->path.type != DEVICE_PATH_APIC) ||
40 (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) {
51 static int get_fsb(void)
53 u32 fsbcode=(rdmsr(0xcd).lo >> 4) & 7;
61 printk(BIOS_DEBUG, "Warning: No supported FSB frequency. Assuming 200MHz\n");
65 int get_cst_entries(struct cst_entry **entries __attribute__((unused)))
70 void generate_cpu_entries(void)
73 int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6;
75 int totalcores = determine_total_number_of_cores();
76 int cores_per_package = (cpuid_ebx(1)>>16) & 0xff;
77 int numcpus = totalcores/cores_per_package; // this assumes that all CPUs share the same layout
79 struct cst_entry *cst_entries;
81 printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", numcpus, cores_per_package);
83 for (cpuID=1; cpuID <=numcpus; cpuID++) {
84 for (coreID=1; coreID<=cores_per_package; coreID++) {
89 len_pr = acpigen_write_processor((cpuID-1)*cores_per_package+coreID-1, pcontrol_blk, plen);
90 len_pr += acpigen_write_empty_PCT();
91 len_pr += acpigen_write_PSD_package(cpuID-1,cores_per_package,SW_ANY);
92 if ((count = get_cst_entries(&cst_entries)) > 0)
93 len_pr += acpigen_write_CST_package(cst_entries, count);
94 len_pr += acpigen_write_name("_PSS");
98 msr = rdmsr(IA32_PERF_STS);
99 int busratio_min=(msr.lo >> 24) & 0x1f;
100 int busratio_max=(msr.hi >> (40-32)) & 0x1f;
101 int vid_min=msr.lo & 0x3f;
102 msr = rdmsr(IA32_PLATFORM_ID);
103 int vid_max=msr.lo & 0x3f;
104 int clock_max=get_fsb()*busratio_max;
105 int clock_min=get_fsb()*busratio_min;
106 printk(BIOS_DEBUG, "clocks between %d and %d MHz.\n", clock_min, clock_max);
107 #define MEROM_MIN_POWER 16000
108 #define MEROM_MAX_POWER 35000
109 int power_max=MEROM_MAX_POWER;
110 int power_min=MEROM_MIN_POWER;
112 int num_states=(busratio_max-busratio_min)/busratio_step;
113 while (num_states > max_states-1) {
117 printk(BIOS_DEBUG, "adding %x P-States between busratio %x and %x, incl. P0\n", num_states+1, busratio_min, busratio_max);
118 int vid_step=(vid_max-vid_min)/num_states;
119 int power_step=(power_max-power_min)/num_states;
120 int clock_step=(clock_max-clock_min)/num_states;
121 len_ps = acpigen_write_package(num_states+1); // for Super LFM, this must be increases by another one
122 len_ps += acpigen_write_PSS_package(clock_max /*mhz*/, power_max /*mW*/, 0 /*lat1*/, 0 /*lat2*/, (busratio_max<<8)|(vid_max) /*control*/, (busratio_max<<8)|(vid_max) /*status*/);
123 int current_busratio=busratio_min+((num_states-1)*busratio_step);
124 int current_vid=vid_min+((num_states-1)*vid_step);
125 int current_power=power_min+((num_states-1)*power_step);
126 int current_clock=clock_min+((num_states-1)*clock_step);
128 for (i=0;i<num_states; i++) {
129 len_ps += acpigen_write_PSS_package(current_clock /*mhz*/, current_power /*mW*/, 0 /*lat1*/, 0 /*lat2*/, (current_busratio<<8)|(current_vid) /*control*/, (current_busratio<<8)|(current_vid) /*status*/);
130 current_busratio -= busratio_step;
131 current_vid -= vid_step;
132 current_power -= power_step;
133 current_clock -= clock_step;
136 acpigen_patch_len(len_ps);
137 len_pr += acpigen_write_PPC(0);
140 acpigen_patch_len(len_pr);