2 * This file is part of the coreboot project.
4 * Copyright (C) 2007-2009 coresystems GmbH
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 #include <console/console.h>
23 #include <device/device.h>
24 #include <device/pci.h>
27 #include <cpu/x86/mtrr.h>
28 #include <cpu/x86/msr.h>
29 #include <cpu/x86/lapic.h>
30 #include <cpu/intel/microcode.h>
31 #include <cpu/intel/speedstep.h>
32 #include <cpu/intel/acpi.h>
33 #include <cpu/intel/hyperthreading.h>
34 #include <cpu/x86/cache.h>
35 #include <cpu/x86/name.h>
38 static const uint32_t microcode_updates[] = {
39 #include "microcode-2129-m206f257.h"
40 #include "microcode-2334-m016fbB6.h"
41 #include "microcode-2336-m106fbB6.h"
42 #include "microcode-2337-m806fbB6.h"
43 #include "microcode-2346-m16fda3.h"
44 #include "microcode-2347-m206fda3.h"
45 #include "microcode-2348-m806fda3.h"
46 #include "microcode-2374-m16f6cb.h"
47 #include "microcode-2375-m206f6cc.h"
48 #include "microcode-2376-m46f6cd.h"
49 #include "microcode-2380-m106f768.h"
50 #include "microcode-2381-m406f769.h"
51 #include "microcode-2385-m806fa94.h"
52 #include "microcode-2389-m16f25a.h"
53 #include "microcode-2986-m086fbB8.h"
54 #include "microcode-2990-m046fbB9.h"
55 #include "microcode-2991-m406fbB9.h"
56 /* Dummy terminator */
63 #define IA32_FEATURE_CONTROL 0x003a
65 #define CPUID_VMX (1 << 5)
66 #define CPUID_SMX (1 << 6)
67 static void enable_vmx(void)
69 struct cpuid_result regs;
72 msr = rdmsr(IA32_FEATURE_CONTROL);
74 if (msr.lo & (1 << 0)) {
75 /* VMX locked. If we set it again we get an illegal
82 if (regs.ecx & CPUID_VMX) {
84 if (regs.ecx & CPUID_SMX)
88 wrmsr(IA32_FEATURE_CONTROL, msr);
90 msr.lo |= (1 << 0); /* Set lock bit */
92 wrmsr(IA32_FEATURE_CONTROL, msr);
95 #define PMG_CST_CONFIG_CONTROL 0xe2
96 #define PMG_IO_BASE_ADDR 0xe3
97 #define PMG_IO_CAPTURE_ADDR 0xe4
99 #define HIGHEST_CLEVEL 3
100 static void configure_c_states(void)
104 msr = rdmsr(PMG_CST_CONFIG_CONTROL);
106 msr.lo |= (1 << 15); // config lock until next reset
107 msr.lo |= (1 << 14); // Deeper Sleep
108 msr.lo |= (1 << 10); // Enable IO MWAIT redirection
109 msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk
110 msr.lo |= (1 << 3); // Dynamic L2
112 /* Number of supported C-States */
114 msr.lo |= HIGHEST_CLEVEL; // support at most C3
116 wrmsr(PMG_CST_CONFIG_CONTROL, msr);
118 /* Set Processor MWAIT IO BASE */
120 msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16);
121 wrmsr(PMG_IO_BASE_ADDR, msr);
123 /* Set C_LVL controls and IO Capture Address */
125 msr.lo = (PMB0_BASE + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because LVL0+1 aren't counted
126 wrmsr(PMG_IO_CAPTURE_ADDR, msr);
129 #define IA32_MISC_ENABLE 0x1a0
130 static void configure_misc(void)
134 msr = rdmsr(IA32_MISC_ENABLE);
135 msr.lo |= (1 << 3); /* TM1 enable */
136 msr.lo |= (1 << 13); /* TM2 enable */
137 msr.lo |= (1 << 17); /* Bidirectional PROCHOT# */
139 msr.lo |= (1 << 10); /* FERR# multiplexing */
141 // TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1
142 msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
148 /* TODO This should only be done on mobile CPUs, see cpuid 5 */
149 msr.hi |= (1 << (32 - 32)); // C4E
150 msr.hi |= (1 << (33 - 32)); // Hard C4E
153 /* NOTE: We leave the EMTTM_CR_TABLE0-5 at their default values */
154 msr.hi |= (1 << (36 - 32));
156 wrmsr(IA32_MISC_ENABLE, msr);
158 msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */
159 wrmsr(IA32_MISC_ENABLE, msr);
161 // set maximum CPU speed
162 msr = rdmsr(IA32_PERF_STS);
163 int busratio_max=(msr.hi >> (40-32)) & 0x1f;
165 msr = rdmsr(IA32_PLATFORM_ID);
166 int vid_max=msr.lo & 0x3f;
169 msr.lo |= busratio_max << 8;
172 wrmsr(IA32_PERF_CTL, msr);
175 #define PIC_SENS_CFG 0x1aa
176 static void configure_pic_thermal_sensors(void)
180 msr = rdmsr(PIC_SENS_CFG);
182 msr.lo |= (1 << 21); // inter-core lock TM1
183 msr.lo |= (1 << 4); // Enable bypass filter
185 wrmsr(PIC_SENS_CFG, msr);
189 static unsigned ehci_debug_addr;
192 static void model_6fx_init(device_t cpu)
194 char processor_name[49];
196 /* Turn on caching if we haven't already */
199 /* Update the microcode */
200 intel_update_microcode(microcode_updates);
202 /* Print processor name */
203 fill_processor_name(processor_name);
204 printk(BIOS_INFO, "CPU: %s.\n", processor_name);
207 // Is this caution really needed?
209 ehci_debug_addr = get_ehci_debug();
217 /* Setup Page Attribute Tables (PAT) */
221 set_ehci_debug(ehci_debug_addr);
224 /* Enable the local cpu apics */
227 /* Enable virtualization */
230 /* Configure C States */
231 configure_c_states();
233 /* Configure Enhanced SpeedStep and Thermal Sensors */
236 /* PIC thermal sensor control */
237 configure_pic_thermal_sensors();
239 /* Start up my cpu siblings */
240 intel_sibling_init(cpu);
243 static struct device_operations cpu_dev_ops = {
244 .init = model_6fx_init,
247 static struct cpu_device_id cpu_table[] = {
248 { X86_VENDOR_INTEL, 0x06f0 }, /* Intel Core 2 Solo/Core Duo */
249 { X86_VENDOR_INTEL, 0x06f2 }, /* Intel Core 2 Solo/Core Duo */
250 { X86_VENDOR_INTEL, 0x06f6 }, /* Intel Core 2 Solo/Core Duo */
251 { X86_VENDOR_INTEL, 0x06f7 }, /* Intel Core 2 Solo/Core Duo */
252 { X86_VENDOR_INTEL, 0x06fa }, /* Intel Core 2 Solo/Core Duo */
253 { X86_VENDOR_INTEL, 0x06fb }, /* Intel Core 2 Solo/Core Duo */
254 { X86_VENDOR_INTEL, 0x06fd }, /* Intel Core 2 Solo/Core Duo */
255 { X86_VENDOR_INTEL, 0x10676 }, /* Core2 Duo E8200 */
259 static const struct cpu_driver driver __cpu_driver = {
261 .id_table = cpu_table,