2 * This file is part of the coreboot project.
4 * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 #ifndef _CPU_INTEL_MODEL_206AX_H
23 #define _CPU_INTEL_MODEL_206AX_H
25 /* SandyBridge bus clock is fixed at 100MHz */
26 #define SANDYBRIDGE_BCLK 100
28 #define IA32_FEATURE_CONTROL 0x3a
29 #define CPUID_VMX (1 << 5)
30 #define CPUID_SMX (1 << 6)
31 #define MSR_FEATURE_CONFIG 0x13c
32 #define IA32_PLATFORM_DCA_CAP 0x1f8
33 #define IA32_MISC_ENABLE 0x1a0
34 #define IA32_PERF_CTL 0x199
35 #define IA32_THERM_INTERRUPT 0x19b
36 #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0
37 #define ENERGY_POLICY_PERFORMANCE 0
38 #define ENERGY_POLICY_NORMAL 6
39 #define ENERGY_POLICY_POWERSAVE 15
40 #define IA32_PACKAGE_THERM_INTERRUPT 0x1b2
41 #define MSR_LT_LOCK_MEMORY 0x2e7
42 #define IA32_MC0_STATUS 0x401
44 #define MSR_PIC_MSG_CONTROL 0x2e
45 #define MSR_PLATFORM_INFO 0xce
46 #define PLATFORM_INFO_SET_TDP (1 << 29)
47 #define MSR_PMG_CST_CONFIG_CONTROL 0xe2
48 #define MSR_PMG_IO_CAPTURE_BASE 0xe4
50 #define MSR_MISC_PWR_MGMT 0x1aa
51 #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)
52 #define MSR_TURBO_RATIO_LIMIT 0x1ad
53 #define MSR_POWER_CTL 0x1fc
55 #define MSR_PKGC3_IRTL 0x60a
56 #define MSR_PKGC6_IRTL 0x60b
57 #define MSR_PKGC7_IRTL 0x60c
58 #define IRTL_VALID (1 << 15)
59 #define IRTL_1_NS (0 << 10)
60 #define IRTL_32_NS (1 << 10)
61 #define IRTL_1024_NS (2 << 10)
62 #define IRTL_32768_NS (3 << 10)
63 #define IRTL_1048576_NS (4 << 10)
64 #define IRTL_33554432_NS (5 << 10)
65 #define IRTL_RESPONSE_MASK (0x3ff)
67 /* long duration in low dword, short duration in high dword */
68 #define MSR_PKG_POWER_LIMIT 0x610
69 #define PKG_POWER_LIMIT_MASK 0x7fff
70 #define PKG_POWER_LIMIT_EN (1 << 15)
71 #define PKG_POWER_LIMIT_CLAMP (1 << 16)
72 #define PKG_POWER_LIMIT_TIME_SHIFT 17
73 #define PKG_POWER_LIMIT_TIME_MASK 0x7f
75 #define MSR_PP0_CURRENT_CONFIG 0x601
76 #define PP0_CURRENT_LIMIT (112 << 3) /* 112 A */
77 #define MSR_PP1_CURRENT_CONFIG 0x602
78 #define PP1_CURRENT_LIMIT (35 << 3) /* 35 A */
79 #define MSR_PKG_POWER_SKU_UNIT 0x606
80 #define MSR_PKG_POWER_SKU 0x614
81 #define MSR_PP0_POWER_LIMIT 0x638
82 #define MSR_PP1_POWER_LIMIT 0x640
84 /* P-state configuration */
85 #define PSS_MAX_ENTRIES 8
86 #define PSS_RATIO_STEP 2
87 #define PSS_LATENCY_TRANSITION 10
88 #define PSS_LATENCY_BUSMASTER 10
92 void intel_model_206ax_finalize_smm(void);
94 /* Configure power limits for turbo mode */
95 void set_power_limits(u8 power_limit_1_time);