1 /* microcode.c: Microcode update for PIII and later CPUS
5 #include <console/console.h>
7 #include <cpu/x86/msr.h>
8 #include <cpu/intel/microcode.h>
28 static inline uint32_t read_microcode_rev(void)
30 /* Some Intel Cpus can be very finicky about the
31 * cpuid sequence used. So this is implemented in
32 * assembly so that it works reliably.
37 "xorl %%eax, %%eax\n\t"
38 "xorl %%edx, %%edx\n\t"
39 "movl $0x8b, %%ecx\n\t"
41 "movl $0x01, %%eax\n\t"
43 "movl $0x08b, %%ecx\n\t"
46 "=a" (msr.lo), "=d" (msr.hi)
54 void intel_update_microcode(void *microcode_updates)
57 unsigned int pf, rev, sig;
58 unsigned int x86_model, x86_family;
63 /* cpuid sets msr 0x8B iff a microcode update has been loaded. */
70 x86_model = (eax >>4) & 0x0f;
71 x86_family = (eax >>8) & 0x0f;
75 if ((x86_model >= 5)||(x86_family>6)) {
77 pf = 1 << ((msr.hi >> 18) & 7);
79 print_debug("microcode_info: sig = 0x");
80 print_debug_hex32(sig);
81 print_debug(" pf=0x");
82 print_debug_hex32(pf);
83 print_debug(" rev = 0x");
84 print_debug_hex32(rev);
87 m = microcode_updates;
88 for(c = microcode_updates; m->hdrver; m = (struct microcode *)c) {
89 if ((m->sig == sig) && (m->pf & pf)) {
91 msr.lo = (unsigned long)(&m->bits) & 0xffffffff;
95 /* Read back the new microcode version */
96 new_rev = read_microcode_rev();
98 print_debug("microcode updated to revision: ");
99 print_debug_hex32(new_rev);
100 print_debug(" from revision ");
101 print_debug_hex32(rev);