Move "select CACHE_AS_RAM" lines from boards into CPU socket.
[coreboot.git] / src / cpu / amd / socket_S1G1 / Kconfig
1 config CPU_AMD_SOCKET_S1G1
2         bool
3
4 if CPU_AMD_SOCKET_S1G1
5
6 config SOCKET_SPECIFIC_OPTIONS
7         def_bool y
8         select K8_REV_F_SUPPORT
9         select K8_HT_FREQ_1G_SUPPORT
10         select CPU_AMD_MODEL_FXX
11         select CACHE_AS_RAM
12
13 config CPU_SOCKET_TYPE
14         hex
15         default 0x12
16
17 #DDR2 and REG, S1G1
18 config DIMM_SUPPORT
19         hex
20         default 0x0204
21
22 config CPU_ADDR_BITS
23         int
24         default 40
25
26 config DCACHE_RAM_BASE
27         hex
28         default 0xc8000
29
30 config DCACHE_RAM_SIZE
31         hex
32         default 0x08000
33
34 config DCACHE_RAM_GLOBAL_VAR_SIZE
35         hex
36         default 0x01000
37
38 endif