2 * This file needs a major cleanup. Too much #if 0 code
5 #include <console/console.h>
8 #include <device/device.h>
9 #include <device/pci.h>
10 #include <device/pci_ids.h>
11 #include <device/hypertransport.h>
19 void sc520_udelay(int microseconds) {
21 for(x = 0; x < 1000; x++)
25 /* looks like we define this now */
27 udelay(int microseconds) {
28 sc520_udelay(microseconds);
31 * set up basic things ...
32 * PAR should NOT go here, as it might change with the mainboard.
34 static void cpu_init(device_t dev)
36 unsigned long *l = (unsigned long *) 0xfffef088;
38 for(i = 0; i < 16; i++, l++)
39 printk_err("Par%d: 0x%lx\n", i, *l);
41 printk_spew("SC520 random fixup ...\n");
45 /* Ollie says: make a northbridge/amd/sc520. Ron sez:
46 * there is no real northbridge, keep it here in cpu.
47 * Ron wins, he's writing the code.
49 void sc520_enable_resources(struct device *dev) {
50 unsigned char command;
52 printk_spew("%s\n", __func__);
53 command = pci_read_config8(dev, PCI_COMMAND);
54 printk_spew("========>%s, command 0x%x\n", __func__, command);
55 command |= PCI_COMMAND_MEMORY | PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
56 printk_spew("========>%s, command 0x%x\n", __func__, command);
57 pci_write_config8(dev, PCI_COMMAND, command);
58 command = pci_read_config8(dev, PCI_COMMAND);
59 printk_spew("========>%s, command 0x%x\n", __func__, command);
66 static struct device_operations cpu_operations = {
67 .read_resources = pci_dev_read_resources,
68 .set_resources = pci_dev_set_resources,
69 .enable_resources = sc520_enable_resources,
75 static const struct pci_driver cpu_driver __pci_driver = {
76 .ops = &cpu_operations,
77 .vendor = PCI_VENDOR_ID_AMD,
83 #define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
85 static void pci_domain_read_resources(device_t dev)
87 struct resource *resource;
88 printk_spew("%s\n", __func__);
89 /* Initialize the system wide io space constraints */
90 resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
91 resource->limit = 0xffffUL;
92 resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
94 /* Initialize the system wide memory resources constraints */
95 resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
96 resource->limit = 0xffffffffULL;
97 resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
100 static void ram_resource(device_t dev, unsigned long index,
101 unsigned long basek, unsigned long sizek)
103 struct resource *resource;
104 printk_spew("%s sizek 0x%x\n", __func__, sizek);
108 resource = new_resource(dev, index);
109 resource->base = ((resource_t)basek) << 10;
110 resource->size = ((resource_t)sizek) << 10;
111 resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
112 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
115 static void tolm_test(void *gp, struct device *dev, struct resource *new)
117 struct resource **best_p = gp;
118 struct resource *best;
120 if (!best || (best->base > new->base)) {
126 static uint32_t find_pci_tolm(struct bus *bus)
128 struct resource *min;
130 printk_spew("%s\n", __func__);
132 search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
134 if (min && tolm > min->base) {
137 printk_spew("%s returns 0x%x\n", __func__, tolm);
141 static void pci_domain_set_resources(device_t dev)
145 printk_spew("%s\n", __func__);
146 pci_tolm = find_pci_tolm(&dev->link[0]);
147 mc_dev = dev->link[0].children;
149 unsigned long tomk, tolmk;
150 // unsigned char rambits;
154 for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
156 reg = pci_read_config8(mc_dev, ramregs[i]);
157 /* these are ENDING addresses, not sizes.
158 * if there is memory in this slot, then reg will be > rambits.
159 * So we just take the max, that gives us total.
160 * We take the highest one to cover for once and future coreboot
161 * bugs. We warn about bugs.
166 printk_err("ERROR! register 0x%x is not set!\n",
169 printk_debug("I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
170 tomk = rambits*8*1024;
173 /* Compute the top of Low memory */
174 tolmk = pci_tolm >> 10;
176 /* The PCI hole does does not overlap the memory.
180 /* Report the memory regions */
182 ram_resource(dev, idx++, 0, tolmk);
184 assign_resources(&dev->link[0]);
187 static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
189 printk_spew("%s\n", __func__);
190 max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
196 void sc520_enable_resources(device_t dev) {
198 printk_spew("%s\n", __func__);
199 printk_spew("THIS IS FOR THE SC520 =============================\n");
202 command = pci_read_config8(dev, PCI_COMMAND);
203 printk_spew("%s, command 0x%x\n", __func__, command);
204 command |= PCI_COMMAND_MEMORY;
205 printk_spew("%s, command 0x%x\n", __func__, command);
206 pci_write_config8(dev, PCI_COMMAND, command);
207 command = pci_read_config8(dev, PCI_COMMAND);
208 printk_spew("%s, command 0x%x\n", __func__, command);
210 enable_childrens_resources(dev);
211 printk_spew("%s\n", __func__);
215 static struct device_operations pci_domain_ops = {
216 .read_resources = pci_domain_read_resources,
217 .set_resources = pci_domain_set_resources,
219 * If enable_resources is set to the generic enable_resources
220 * function the whole thing will hang in an endless loop on
221 * the ts5300. If this is really needed on another platform,
222 * something is conceptionally wrong.
224 .enable_resources = 0, //enable_resources,
226 .scan_bus = pci_domain_scan_bus,
230 static void cpu_bus_init(device_t dev)
232 printk_spew("cpu_bus_init\n");
235 static void cpu_bus_noop(device_t dev)
239 static struct device_operations cpu_bus_ops = {
240 .read_resources = cpu_bus_noop,
241 .set_resources = cpu_bus_noop,
242 .enable_resources = cpu_bus_noop,
243 .init = cpu_bus_init,
248 static void enable_dev(struct device *dev)
250 printk_spew("%s\n", __func__);
251 /* Set the operations if it is a special bus type */
252 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
253 dev->ops = &pci_domain_ops;
257 /* This is never hit as none of the sc520 boards have
258 * an APIC cluster defined
260 else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
261 dev->ops = &cpu_bus_ops;
267 struct chip_operations cpu_amd_sc520_ops = {
268 CHIP_NAME("AMD Elan SC520 CPU")
269 .enable_dev = enable_dev,