2 * This file needs a major cleanup. Too much #if 0 code
5 #include <console/console.h>
8 #include <device/device.h>
9 #include <device/pci.h>
10 #include <device/pci_ids.h>
11 #include <device/hypertransport.h>
19 void sc520_udelay(int microseconds) {
21 for(x = 0; x < 1000; x++)
25 /* looks like we define this now */
27 udelay(int microseconds) {
28 sc520_udelay(microseconds);
31 * set up basic things ...
32 * PAR should NOT go here, as it might change with the mainboard.
34 static void cpu_init(device_t dev)
36 unsigned long *l = (unsigned long *) 0xfffef088;
38 for(i = 0; i < 16; i++, l++)
39 printk_err("Par%d: 0x%lx\n", i, *l);
41 printk_spew("SC520 random fixup ...\n");
45 /* Ollie says: make a northbridge/amd/sc520. Ron sez:
46 * there is no real northbridge, keep it here in cpu.
47 * Ron wins, he's writing the code.
49 void sc520_enable_resources(struct device *dev) {
50 unsigned char command;
52 printk_spew("%s\n", __func__);
53 command = pci_read_config8(dev, PCI_COMMAND);
54 printk_spew("========>%s, command 0x%x\n", __func__, command);
55 command |= PCI_COMMAND_MEMORY | PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
56 printk_spew("========>%s, command 0x%x\n", __func__, command);
57 pci_write_config8(dev, PCI_COMMAND, command);
58 command = pci_read_config8(dev, PCI_COMMAND);
59 printk_spew("========>%s, command 0x%x\n", __func__, command);
65 static void sc520_read_resources(device_t dev)
69 pci_dev_read_resources(dev);
71 res = new_resource(dev, 1);
74 res->limit = 0xffffUL;
75 res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
77 res = new_resource(dev, 3); /* IOAPIC */
78 res->base = 0xfec00000;
79 res->size = 0x00001000;
80 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
84 static struct device_operations cpu_operations = {
85 .read_resources = sc520_read_resources,
86 .set_resources = pci_dev_set_resources,
87 .enable_resources = sc520_enable_resources,
93 static const struct pci_driver cpu_driver __pci_driver = {
94 .ops = &cpu_operations,
95 .vendor = PCI_VENDOR_ID_AMD,
99 static void ram_resource(device_t dev, unsigned long index,
100 unsigned long basek, unsigned long sizek)
102 struct resource *resource;
103 printk_spew("%s sizek 0x%x\n", __func__, sizek);
107 resource = new_resource(dev, index);
108 resource->base = ((resource_t)basek) << 10;
109 resource->size = ((resource_t)sizek) << 10;
110 resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
111 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
114 static void tolm_test(void *gp, struct device *dev, struct resource *new)
116 struct resource **best_p = gp;
117 struct resource *best;
119 if (!best || (best->base > new->base)) {
125 static uint32_t find_pci_tolm(struct bus *bus)
127 struct resource *min;
129 printk_spew("%s\n", __func__);
131 search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
133 if (min && tolm > min->base) {
136 printk_spew("%s returns 0x%x\n", __func__, tolm);
140 static void pci_domain_set_resources(device_t dev)
144 printk_spew("%s\n", __func__);
145 pci_tolm = find_pci_tolm(&dev->link[0]);
146 mc_dev = dev->link[0].children;
148 unsigned long tomk, tolmk;
149 // unsigned char rambits;
153 for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
155 reg = pci_read_config8(mc_dev, ramregs[i]);
156 /* these are ENDING addresses, not sizes.
157 * if there is memory in this slot, then reg will be > rambits.
158 * So we just take the max, that gives us total.
159 * We take the highest one to cover for once and future coreboot
160 * bugs. We warn about bugs.
165 printk_err("ERROR! register 0x%x is not set!\n",
168 printk_debug("I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
169 tomk = rambits*8*1024;
172 /* Compute the top of Low memory */
173 tolmk = pci_tolm >> 10;
175 /* The PCI hole does does not overlap the memory.
179 /* Report the memory regions */
181 ram_resource(dev, idx++, 0, tolmk);
183 assign_resources(&dev->link[0]);
187 void sc520_enable_resources(device_t dev) {
189 printk_spew("%s\n", __func__);
190 printk_spew("THIS IS FOR THE SC520 =============================\n");
193 command = pci_read_config8(dev, PCI_COMMAND);
194 printk_spew("%s, command 0x%x\n", __func__, command);
195 command |= PCI_COMMAND_MEMORY;
196 printk_spew("%s, command 0x%x\n", __func__, command);
197 pci_write_config8(dev, PCI_COMMAND, command);
198 command = pci_read_config8(dev, PCI_COMMAND);
199 printk_spew("%s, command 0x%x\n", __func__, command);
201 enable_childrens_resources(dev);
202 printk_spew("%s\n", __func__);
206 static struct device_operations pci_domain_ops = {
207 .read_resources = pci_domain_read_resources,
208 .set_resources = pci_domain_set_resources,
210 * If enable_resources is set to the generic enable_resources
211 * function the whole thing will hang in an endless loop on
212 * the ts5300. If this is really needed on another platform,
213 * something is conceptually wrong.
215 .enable_resources = 0, //enable_resources,
217 .scan_bus = pci_domain_scan_bus,
221 static void cpu_bus_init(device_t dev)
223 printk_spew("cpu_bus_init\n");
226 static void cpu_bus_noop(device_t dev)
230 static struct device_operations cpu_bus_ops = {
231 .read_resources = cpu_bus_noop,
232 .set_resources = cpu_bus_noop,
233 .enable_resources = cpu_bus_noop,
234 .init = cpu_bus_init,
239 static void enable_dev(struct device *dev)
241 printk_spew("%s\n", __func__);
242 /* Set the operations if it is a special bus type */
243 if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
244 dev->ops = &pci_domain_ops;
248 /* This is never hit as none of the sc520 boards have
249 * an APIC cluster defined
251 else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
252 dev->ops = &cpu_bus_ops;
258 struct chip_operations cpu_amd_sc520_ops = {
259 CHIP_NAME("AMD Elan SC520 CPU")
260 .enable_dev = enable_dev,