src/cpu/amd/sc520/sc520.c

   1 /*
   2  * This file needs a major cleanup. Too much #if 0 code
   3  */
   4
   5 #include <console/console.h>
   6 #include <arch/io.h>
   7 #include <stdint.h>
   8 #include <device/device.h>
   9 #include <device/pci.h>
  10 #include <device/pci_ids.h>
  11 #include <device/hypertransport.h>
  12 #include <stdlib.h>
  13 #include <string.h>
  14 #include <bitops.h>
  15 #include <delay.h>
  16 #include "chip.h"
  17
  18 /*
  19  * set up basic things ...
  20  * PAR should NOT go here, as it might change with the mainboard.
  21  */
  22 static void cpu_init(device_t dev)
  23 {
  24   unsigned long *l = (unsigned long *) 0xfffef088;
  25   int i;
  26   for(i = 0; i < 16; i++, l++)
  27     printk(BIOS_ERR, "Par%d: 0x%lx\n", i, *l);
  28
  29   printk(BIOS_SPEW, "SC520 random fixup ...\n");
  30 }
  31
  32
  33 /* Ollie says: make a northbridge/amd/sc520. Ron sez:
  34  * there is no real northbridge, keep it here in cpu.
  35  * Ron wins, he's writing the code.
  36  */
  37 static void sc520_enable_resources(struct device *dev) {
  38         unsigned char command;
  39
  40         printk(BIOS_SPEW, "%s\n", __func__);
  41         command = pci_read_config8(dev, PCI_COMMAND);
  42         printk(BIOS_SPEW, "========>%s, command 0x%x\n", __func__, command);
  43         command |= PCI_COMMAND_MEMORY | PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
  44         printk(BIOS_SPEW, "========>%s, command 0x%x\n", __func__, command);
  45         pci_write_config8(dev, PCI_COMMAND, command);
  46         command = pci_read_config8(dev, PCI_COMMAND);
  47         printk(BIOS_SPEW, "========>%s, command 0x%x\n", __func__, command);
  48 /*
  49  */
  50
  51 }
  52
  53 static void sc520_read_resources(device_t dev)
  54 {
  55         struct resource* res;
  56
  57         pci_dev_read_resources(dev);
  58
  59         res = new_resource(dev, 1);
  60         res->base = 0x0UL;
  61         res->size = 0x400UL;
  62         res->limit = 0xffffUL;
  63         res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
  64
  65         res = new_resource(dev, 3); /* IOAPIC */
  66         res->base = 0xfec00000;
  67         res->size = 0x00001000;
  68         res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
  69 }
  70
  71
  72 static struct device_operations cpu_operations = {
  73         .read_resources   = sc520_read_resources,
  74         .set_resources    = pci_dev_set_resources,
  75         .enable_resources = sc520_enable_resources,
  76         .init             = cpu_init,
  77         .enable           = 0,
  78         .ops_pci          = 0,
  79 };
  80
  81 static const struct pci_driver cpu_driver __pci_driver = {
  82         .ops = &cpu_operations,
  83         .vendor = PCI_VENDOR_ID_AMD,
  84         .device = 0x3000
  85 };
  86
  87 static void ram_resource(device_t dev, unsigned long index,
  88         unsigned long basek, unsigned long sizek)
  89 {
  90         struct resource *resource;
  91         printk(BIOS_SPEW, "%s sizek 0x%lx\n", __func__, sizek);
  92         if (!sizek) {
  93                 return;
  94         }
  95         resource = new_resource(dev, index);
  96         resource->base  = ((resource_t)basek) << 10;
  97         resource->size  = ((resource_t)sizek) << 10;
  98         resource->flags =  IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
  99                 IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 100 }
 101
 102 static void tolm_test(void *gp, struct device *dev, struct resource *new)
 103 {
 104         struct resource **best_p = gp;
 105         struct resource *best;
 106         best = *best_p;
 107         if (!best || (best->base > new->base)) {
 108                 best = new;
 109         }
 110         *best_p = best;
 111 }
 112
 113 static uint32_t find_pci_tolm(struct bus *bus)
 114 {
 115         struct resource *min;
 116         uint32_t tolm;
 117   printk(BIOS_SPEW, "%s\n", __func__);
 118         min = 0;
 119         search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
 120         tolm = 0xffffffffUL;
 121         if (min && tolm > min->base) {
 122                 tolm = min->base;
 123         }
 124   printk(BIOS_SPEW, "%s returns 0x%x\n", __func__, tolm);
 125         return tolm;
 126 }
 127
 128 static void pci_domain_set_resources(device_t dev)
 129 {
 130         device_t mc_dev;
 131         uint32_t pci_tolm;
 132   printk(BIOS_SPEW, "%s\n", __func__);
 133         pci_tolm = find_pci_tolm(dev->link_list);
 134         mc_dev = dev->link_list->children;
 135         if (mc_dev) {
 136                 unsigned long tomk, tolmk;
 137                 //              unsigned char rambits;
 138                 // int i;
 139                 int idx;
 140 #if 0
 141                 for(rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) {
 142                         unsigned char reg;
 143                         reg = pci_read_config8(mc_dev, ramregs[i]);
 144                         /* these are ENDING addresses, not sizes.
 145                          * if there is memory in this slot, then reg will be > rambits.
 146                          * So we just take the max, that gives us total.
 147                          * We take the highest one to cover for once and future coreboot
 148                          * bugs. We warn about bugs.
 149                          */
 150                         if (reg > rambits)
 151                                 rambits = reg;
 152                         if (reg < rambits)
 153                                 printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n",
 154                                         ramregs[i]);
 155                 }
 156                 printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
 157                 tomk = rambits*8*1024;
 158 #endif
 159                 tomk = 32 * 1024;
 160                 /* Compute the top of Low memory */
 161                 tolmk = pci_tolm >> 10;
 162                 if (tolmk >= tomk) {
 163                         /* The PCI hole does does not overlap the memory.
 164                          */
 165                         tolmk = tomk;
 166                 }
 167                 /* Report the memory regions */
 168                 idx = 10;
 169                 ram_resource(dev, idx++, 0, tolmk);
 170         }
 171         assign_resources(dev->link_list);
 172 }
 173
 174 #if 0
 175 void sc520_enable_resources(device_t dev) {
 176
 177         printk(BIOS_SPEW, "%s\n", __func__);
 178         printk(BIOS_SPEW, "THIS IS FOR THE SC520 =============================\n");
 179
 180 /*
 181         command = pci_read_config8(dev, PCI_COMMAND);
 182         printk(BIOS_SPEW, "%s, command 0x%x\n", __func__, command);
 183         command |= PCI_COMMAND_MEMORY;
 184         printk(BIOS_SPEW, "%s, command 0x%x\n", __func__, command);
 185         pci_write_config8(dev, PCI_COMMAND, command);
 186         command = pci_read_config8(dev, PCI_COMMAND);
 187         printk(BIOS_SPEW, "%s, command 0x%x\n", __func__, command);
 188  */
 189         enable_childrens_resources(dev);
 190         printk(BIOS_SPEW, "%s\n", __func__);
 191 }
 192 #endif
 193
 194 static struct device_operations pci_domain_ops = {
 195         .read_resources   = pci_domain_read_resources,
 196         .set_resources    = pci_domain_set_resources,
 197         /*
 198          * If enable_resources is set to the generic enable_resources
 199          * function the whole thing will hang in an endless loop on
 200          * the ts5300. If this is really needed on another platform,
 201          * something is conceptually wrong.
 202          */
 203         .enable_resources = 0, //enable_resources,
 204         .init             = 0,
 205         .scan_bus         = pci_domain_scan_bus,
 206 };
 207
 208 #if 0
 209 static void cpu_bus_init(device_t dev)
 210 {
 211   printk(BIOS_SPEW, "cpu_bus_init\n");
 212 }
 213
 214 static void cpu_bus_noop(device_t dev)
 215 {
 216 }
 217
 218 static struct device_operations cpu_bus_ops = {
 219         .read_resources   = cpu_bus_noop,
 220         .set_resources    = cpu_bus_noop,
 221         .enable_resources = cpu_bus_noop,
 222         .init             = cpu_bus_init,
 223         .scan_bus         = 0,
 224 };
 225 #endif
 226
 227 static void enable_dev(struct device *dev)
 228 {
 229   printk(BIOS_SPEW, "%s\n", __func__);
 230         /* Set the operations if it is a special bus type */
 231         if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
 232                 dev->ops = &pci_domain_ops;
 233                 pci_set_method(dev);
 234         }
 235 #if 0
 236         /* This is never hit as none of the sc520 boards have
 237          * an APIC cluster defined
 238          */
 239         else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
 240                 dev->ops = &cpu_bus_ops;
 241         }
 242 #endif
 243 }
 244
 245
 246 struct chip_operations cpu_amd_sc520_ops = {
 247         CHIP_NAME("AMD Elan SC520 CPU")
 248         .enable_dev = enable_dev,
 249 };