2 * This file is part of the coreboot project.
4 * Copyright (C) 2007 Advanced Micro Devices, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 #define SET_NB_CFG_54 1
25 #include "cpu/amd/quadcore/quadcore_id.c"
27 static u32 get_core_num_in_bsp(u32 nodeid)
30 dword = pci_read_config32(NODE_PCI(nodeid, 3), 0xe8);
32 /* Bit 15 is CmpCap[2] since Revision D. */
33 if ((cpuid_ecx(0x80000008) & 0xff) > 3)
34 dword = ((dword & 8) >> 1) | (dword & 3);
40 #if SET_NB_CFG_54 == 1
41 static u8 set_apicid_cpuid_lo(void)
43 // set the NB_CFG[54]=1; why the OS will be happy with that ???
45 msr = rdmsr(NB_CFG_MSR);
46 msr.hi |= (1<<(54-32)); // InitApicIdCpuIdLo
47 wrmsr(NB_CFG_MSR, msr);
53 static void set_apicid_cpuid_lo(void) { }
58 static void real_start_other_core(u32 nodeid, u32 cores)
62 printk_debug("Start other core - nodeid: %02x cores: %02x\n", nodeid, cores);
64 /* set PCI_DEV(0, 0x18+nodeid, 3), 0x44 bit 27 to redirect all MC4
65 accesses and error logging to core0 */
66 dword = pci_read_config32(NODE_PCI(nodeid, 3), 0x44);
67 dword |= 1 << 27; // NbMcaToMstCpuEn bit
68 pci_write_config32(NODE_PCI(nodeid, 3), 0x44, dword);
69 // set PCI_DEV(0, 0x18+nodeid, 0), 0x68 bit 5 to start core1
70 dword = pci_read_config32(NODE_PCI(nodeid, 0), 0x68);
72 pci_write_config32(NODE_PCI(nodeid, 0), 0x68, dword);
75 dword = pci_read_config32(NODE_PCI(nodeid, 0), 0x168);
76 for (i = 0; i < cores - 1; i++) {
79 pci_write_config32(NODE_PCI(nodeid, 0), 0x168, dword);
83 //it is running on core0 of node0
84 static void start_other_cores(void)
90 if (read_option(CMOS_VSTART_quad_core, CMOS_VLEN_quad_core, 0) != 0) {
91 printk_debug("Skip additional core init\n");
97 for (nodeid = 0; nodeid < nodes; nodeid++) {
98 u32 cores = get_core_num_in_bsp(nodeid);
99 printk_debug("init node: %02x cores: %02x \n", nodeid, cores);
101 real_start_other_core(nodeid, cores);