1 #include <console/console.h>
2 #include <device/device.h>
4 #include <cpu/x86/mtrr.h>
5 #include <cpu/amd/mtrr.h>
6 #include <cpu/x86/cache.h>
7 #include <cpu/x86/msr.h>
10 extern uint64_t uma_memory_size;
13 static unsigned long resk(uint64_t value)
15 unsigned long resultk;
16 if (value < (1ULL << 42)) {
17 resultk = value >> 10;
25 static unsigned fixed_mtrr_index(unsigned long addrk)
28 index = (addrk - 0) >> 6;
30 index = ((addrk - 8*64) >> 4) + 8;
33 index = ((addrk - (8*64 + 16*16)) >> 2) + 24;
35 if (index > NUM_FIXED_RANGES) {
36 index = NUM_FIXED_RANGES;
41 static unsigned int mtrr_msr[] = {
42 MTRRfix64K_00000_MSR, MTRRfix16K_80000_MSR, MTRRfix16K_A0000_MSR,
43 MTRRfix4K_C0000_MSR, MTRRfix4K_C8000_MSR, MTRRfix4K_D0000_MSR, MTRRfix4K_D8000_MSR,
44 MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR,
47 static void set_fixed_mtrrs(unsigned int first, unsigned int last, unsigned char type)
50 unsigned int fixed_msr = NUM_FIXED_RANGES >> 3;
52 msr.lo = msr.hi = 0; /* Shut up gcc */
53 for (i = first; i < last; i++) {
54 /* When I switch to a new msr read it in */
55 if (fixed_msr != i >> 3) {
56 /* But first write out the old msr */
57 if (fixed_msr < (NUM_FIXED_RANGES >> 3)) {
59 wrmsr(mtrr_msr[fixed_msr], msr);
63 msr = rdmsr(mtrr_msr[fixed_msr]);
66 msr.lo &= ~(0xff << ((i&3)*8));
67 msr.lo |= type << ((i&3)*8);
69 msr.hi &= ~(0xff << ((i&3)*8));
70 msr.hi |= type << ((i&3)*8);
73 /* Write out the final msr */
74 if (fixed_msr < (NUM_FIXED_RANGES >> 3)) {
76 wrmsr(mtrr_msr[fixed_msr], msr);
82 unsigned long mmio_basek, tomk;
84 static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resource *res)
86 struct mem_state *state = gp;
88 unsigned int start_mtrr;
89 unsigned int last_mtrr;
91 topk = resk(res->base + res->size);
92 if (state->tomk < topk) {
95 if ((topk < 4*1024*1024) && (state->mmio_basek < topk)) {
96 state->mmio_basek = topk;
98 start_mtrr = fixed_mtrr_index(resk(res->base));
99 last_mtrr = fixed_mtrr_index(resk((res->base + res->size)));
100 if (start_mtrr >= NUM_FIXED_RANGES) {
103 printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) Type: WB, RdMEM, WrMEM\n",
104 start_mtrr, last_mtrr);
105 set_fixed_mtrrs(start_mtrr, last_mtrr, MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM);
109 void amd_setup_mtrrs(void)
111 unsigned long address_bits;
112 struct mem_state state;
115 // Test if this CPU is a Fam 0Fh rev. F or later
116 const int cpu_id = cpuid_eax(0x80000001);
117 printk(BIOS_SPEW, "CPU ID 0x80000001: %x\n", cpu_id);
118 const int has_tom2wb =
119 (((cpu_id>>20 )&0xf) > 0) || // ExtendedFamily > 0
120 ((((cpu_id>>8 )&0xf) == 0xf) && // Family == 0F
121 (((cpu_id>>16)&0xf) >= 0x4)); // Rev>=F deduced from rev tables
123 printk(BIOS_DEBUG, "CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB\n");
125 /* Enable the access to AMD RdDram and WrDram extension bits */
127 sys_cfg = rdmsr(SYSCFG_MSR);
128 sys_cfg.lo |= SYSCFG_MSR_MtrrFixDramModEn;
129 wrmsr(SYSCFG_MSR, sys_cfg);
132 printk(BIOS_DEBUG, "\n");
133 /* Initialized the fixed_mtrrs to uncached */
134 printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) type: UC\n",
135 0, NUM_FIXED_RANGES);
136 set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHEABLE);
138 /* Except for the PCI MMIO hole just before 4GB there are no
139 * significant holes in the address space, so just account
140 * for those two and move on.
142 state.mmio_basek = state.tomk = 0;
143 search_global_resources(
144 IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
145 set_fixed_mtrr_resource, &state);
146 printk(BIOS_DEBUG, "DONE fixed MTRRs\n");
148 if (state.mmio_basek > state.tomk) {
149 state.mmio_basek = state.tomk;
151 /* Round state.mmio_basek down to the nearst size that will fit in TOP_MEM */
152 state.mmio_basek = state.mmio_basek & ~TOP_MEM_MASK_KB;
153 /* Round state.tomk up to the next greater size that will fit in TOP_MEM */
154 state.tomk = (state.tomk + TOP_MEM_MASK_KB) & ~TOP_MEM_MASK_KB;
159 msr.hi = state.mmio_basek >> 22;
160 msr.lo = state.mmio_basek << 10;
162 /* If UMA graphics is enabled, the frame buffer memory
163 * has been deducted from the size of memory below 4GB.
164 * When setting TOM, include UMA DRAM
166 #if CONFIG_GFXUMA == 1
167 msr.lo += uma_memory_size;
171 sys_cfg.lo &= ~(SYSCFG_MSR_TOM2En | SYSCFG_MSR_TOM2WB);
172 if(state.tomk > (4*1024*1024)) {
173 /* DRAM above 4GB: set TOM2, SYSCFG_MSR_TOM2En
174 * and SYSCFG_MSR_TOM2WB
176 msr.hi = state.tomk >> 22;
177 msr.lo = state.tomk << 10;
178 wrmsr(TOP_MEM2, msr);
179 sys_cfg.lo |= SYSCFG_MSR_TOM2En;
181 sys_cfg.lo |= SYSCFG_MSR_TOM2WB;
184 /* zero the IORR's before we enable to prevent
185 * undefined side effects.
188 for(i = IORR_FIRST; i <= IORR_LAST; i++) {
192 /* Enable Variable Mtrrs
193 * Enable the RdMem and WrMem bits in the fixed mtrrs.
194 * Disable access to the RdMem and WrMem in the fixed mtrr.
196 sys_cfg.lo |= SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn;
197 sys_cfg.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
198 wrmsr(SYSCFG_MSR, sys_cfg);
204 address_bits = CONFIG_CPU_ADDR_BITS; //K8 could be 40, and GH could be 48
206 /* AMD specific cpuid function to query number of address bits */
207 if (cpuid_eax(0x80000000) >= 0x80000008) {
208 address_bits = cpuid_eax(0x80000008) & 0xff;
211 /* Now that I have mapped what is memory and what is not
212 * Setup the mtrrs so we can cache the memory.
215 // Rev. F K8 supports has SYSCFG_MSR_TOM2WB and dont need
216 // variable MTRR to span memory above 4GB
217 // Lower revisions K8 need variable MTRR over 4GB
218 x86_setup_var_mtrrs(address_bits, has_tom2wb ? 0 : 1);