src/cpu/amd/model_lx/cpureginit.c

   1 /*
   2  * This file is part of the LinuxBIOS project.
   3  *
   4  * Copyright (C) 2006 Indrek Kruusa <indrek.kruusa@artecdesign.ee>
   5  * Copyright (C) 2006 Ronald G. Minnich <rminnich@gmail.com>
   6  * Copyright (C) 2007 Advanced Micro Devices, Inc.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  21  */
  22
  23 /**************************************************************************
  24 ;*
  25 ;*      SetDelayControl
  26 ;*
  27 ;*************************************************************************/
  28 void SetDelayControl(void){
  29         unsigned int msrnum, glspeed;
  30         unsigned char spdbyte0, spdbyte1;
  31         msr_t msr;
  32
  33         glspeed = GeodeLinkSpeed();
  34
  35         /* fix delay controls for DM and IM arrays */
  36         msrnum = CPU_BC_MSS_ARRAY_CTL0;
  37         msr.hi = 0;
  38         msr.lo = 0x2814D352;
  39         wrmsr(msrnum, msr);
  40
  41         msrnum = CPU_BC_MSS_ARRAY_CTL1;
  42         msr.hi = 0;
  43         msr.lo = 0x1068334D;
  44         wrmsr(msrnum, msr);
  45
  46         msrnum = CPU_BC_MSS_ARRAY_CTL2;
  47         msr.hi = 0x00000106;
  48         msr.lo = 0x83104104;
  49         wrmsr(msrnum,msr);
  50
  51         msrnum = GLCP_FIFOCTL;
  52         msr = rdmsr(msrnum);
  53         msr.hi = 0x00000005;
  54         wrmsr(msrnum, msr);
  55
  56         /* Enable setting */
  57         msrnum = CPU_BC_MSS_ARRAY_CTL_ENA;
  58         msr.hi = 0;
  59         msr.lo = 0x00000001;
  60         wrmsr(msrnum, msr);
  61
  62
  63         /* Debug Delay Control Setup Check
  64         Leave it alone if it has been setup. FS2 or something is here.*/
  65         msrnum = GLCP_DELAY_CONTROLS;
  66         msr = rdmsr(msrnum);
  67         if (msr.lo & ~(0x7C0)){
  68                 return;
  69         }
  70
  71
  72         /*
  73         ; Delay Controls based on DIMM loading. UGH!
  74         ; # of Devices = Module Width (SPD6) / Device Width(SPD13) * Physical Banks(SPD5)
  75         ; Note - We only support module width of 64.
  76         */
  77         spdbyte0 = spd_read_byte(DIMM0, SPD_PRIMARY_SDRAM_WIDTH);
  78         if (spdbyte0 !=0xFF){
  79                 spdbyte0 = (unsigned char) 64/spdbyte0 * (unsigned char) (spd_read_byte(DIMM0, SPD_NUM_DIMM_BANKS));
  80         }
  81         else{
  82                 spdbyte0=0;
  83         }
  84
  85         spdbyte1 = spd_read_byte(DIMM1, SPD_PRIMARY_SDRAM_WIDTH);
  86         if (spdbyte1 !=0xFF){
  87                 spdbyte1 = (unsigned char) 64/spdbyte1 * (unsigned char) (spd_read_byte(DIMM1, SPD_NUM_DIMM_BANKS));
  88         }
  89         else{
  90                 spdbyte1=0;
  91         }
  92
  93
  94
  95 /* The current thinking. Subject to change...
  96
  97 ;                                                                  "FUTURE ROBUSTNESS" PROPOSAL
  98 ;                                                                  ----------------------------
  99 ;               DIMM     Max MBUS                                          MC 0x2000001A bits 26:24
 100 ;DIMMs  devices  Frequency       MCP 0x4C00000F Setting          vvv
 101 ;-----  -------  ---------       ----------------------  ----------
 102 ;1               4               400MHz          0x82*100FF 0x56960004            4
 103 ;1               8               400MHz          0x82*100AA 0x56960004            4
 104 ;1               16              400MHz          0x82*10055 0x56960004            4
 105 ;
 106 ;2               4,4     400MHz          0x82710000 0x56960004            4
 107 ;2               8,8     400MHz          0xC27100A5 0x56960004            4     *** OUT OF PUBLISHED ENVELOPE ***
 108 ;
 109 ;2              16,4     >333            0xB27100A5 0x56960004            4     *** OUT OF PUBLISHED ENVELOPE ***
 110 ;2              16,8     >333            0xB27100A5 0x56960004            4     *** OUT OF PUBLISHED ENVELOPE ***
 111 ;2              16,16    >333            0xB2710000 0x56960004            4     *** OUT OF PUBLISHED ENVELOPE ***
 112 ;
 113 ;1               4               <=333MHz        0x83*100FF 0x56960004            3
 114 ;1               8               <=333MHz        0x83*100AA 0x56960004            3
 115 ;1               16              <=333MHz        0x83*100AA 0x56960004            3
 116 ;
 117 ;2               4,4     <=333MHz        0x837100A5 0x56960004            3
 118 ;2               8,8     <=333MHz        0x937100A5 0x56960004            3
 119 ;
 120 ;2              16,4     <=333MHz        0xB37100A5 0x56960004            3     *** OUT OF PUBLISHED ENVELOPE ***
 121 ;2              16,8     <=333MHz        0xB37100A5 0x56960004            3     *** OUT OF PUBLISHED ENVELOPE ***
 122 ;2              16,16    <=333MHz        0xB37100A5 0x56960004            3     *** OUT OF PUBLISHED ENVELOPE ***
 123 ;=========================================================================
 124 ;* - Bit 55 (disable SDCLK 1,3,5) should be set if there is a single DIMM in slot 0,
 125 ;        but it should be clear for all 2 DIMM settings and if a single DIMM is in slot 1.
 126 ;        Bits 54:52 should always be set to '111'.
 127
 128 ;No VTT termination
 129 ;-------------------------------------
 130 ;ADDR/CTL have 22 ohm series R
 131 ;DQ/DQM/DQS have 33 ohm series R
 132 ;
 133 ;               DIMM     Max MBUS
 134 ;DIMMs  devices  Frequency       MCP 0x4C00000F Setting
 135 ;-----  -------  ---------       ----------------------
 136 ;1               4               400MHz          0xF2F100FF 0x56960004            4                     The MC changes improve Salsa.
 137 ;1               8               400MHz          0xF2F100FF 0x56960004            4                     Delay controls no real change,
 138 ;1               4               <=333MHz        0xF2F100FF 0x56960004            3                     just fixing typo in left side.
 139 ;1               8               <=333MHz        0xF2F100FF 0x56960004            3
 140 ;1               16              <=333MHz        0xF2F100FF 0x56960004            3
 141 */
 142         msr.hi = msr.lo = 0;
 143
 144         if (spdbyte0 == 0 || spdbyte1 == 0){
 145                 /* one dimm solution */
 146                 if (spdbyte1 == 0){
 147                         msr.hi |= 0x000800000;
 148                 }
 149                 spdbyte0 += spdbyte1;
 150                 if (spdbyte0 > 8){
 151                         /* large dimm */
 152                         if (glspeed < 334){
 153                                 msr.hi |= 0x0837100AA;
 154                                 msr.lo |= 0x056960004;
 155                         }
 156                         else{
 157                                 msr.hi |= 0x082710055;
 158                                 msr.lo |= 0x056960004;
 159                         }
 160                 }
 161                 else if (spdbyte0 > 4){
 162                         /* medium dimm */
 163                         if (glspeed < 334){
 164                                 msr.hi |= 0x0837100AA;
 165                                 msr.lo |= 0x056960004;
 166                         }
 167                         else{
 168                                 msr.hi |= 0x0827100AA;
 169                                 msr.lo |= 0x056960004;
 170                         }
 171                 }
 172                 else{
 173                         /* small dimm */
 174                         if (glspeed < 334){
 175                                 msr.hi |= 0x0837100FF;
 176                                 msr.lo |= 0x056960004;
 177                         }
 178                         else{
 179                                 msr.hi |= 0x0827100FF;
 180                                 msr.lo |= 0x056960004;
 181                         }
 182                 }
 183         }
 184         else{
 185                 /* two dimm solution */
 186                 spdbyte0 += spdbyte1;
 187                 if (spdbyte0 > 24){
 188                         /* huge dimms */
 189                         if (glspeed < 334){
 190                                 msr.hi |= 0x0B37100A5;
 191                                 msr.lo |= 0x056960004;
 192                         }
 193                         else{
 194                                 msr.hi |= 0x0B2710000;
 195                                 msr.lo |= 0x056960004;
 196                         }
 197                 }
 198                 else if (spdbyte0 > 16){
 199                         /* large dimms */
 200                         if (glspeed < 334){
 201                                 msr.hi |= 0x0B37100A5;
 202                                 msr.lo |= 0x056960004;
 203                         }
 204                         else{
 205                                 msr.hi |= 0x0B27100A5;
 206                                 msr.lo |= 0x056960004;
 207                         }
 208                 }
 209                 else if (spdbyte0 >= 8){
 210                         /* medium dimms */
 211                         if (glspeed < 334){
 212                                 msr.hi |= 0x0937100A5;
 213                                 msr.lo |= 0x056960004;
 214                         }
 215                         else{
 216                                 msr.hi |= 0x0C27100A5;
 217                                 msr.lo |= 0x056960004;
 218                         }
 219                 }
 220                 else{
 221                         /* small dimms */
 222                         if (glspeed < 334){
 223                                 msr.hi |= 0x0837100A5;
 224                                 msr.lo |= 0x056960004;
 225                         }
 226                         else{
 227                                 msr.hi |= 0x082710000;
 228                                 msr.lo |= 0x056960004;
 229                         }
 230                 }
 231         }
 232         wrmsr(GLCP_DELAY_CONTROLS,msr);
 233         return;
 234 }
 235
 236 /* ***************************************************************************/
 237 /* *    cpuRegInit*/
 238 /* ***************************************************************************/
 239 void
 240 cpuRegInit (void){
 241         int msrnum;
 242         msr_t msr;
 243
 244         /* Castle 2.0 BTM periodic sync period. */
 245         /*      [40:37] 1 sync record per 256 bytes */
 246         msrnum = CPU_PF_CONF;
 247         msr = rdmsr(msrnum);
 248         msr.hi |= (0x8 << 5);
 249         wrmsr(msrnum, msr);
 250
 251         /*
 252         ; Castle performance setting.
 253         ; Enable Quack for fewer re-RAS on the MC
 254         */
 255         msrnum = GLIU0_ARB;
 256         msr = rdmsr(msrnum);
 257         msr.hi &= ~ARB_UPPER_DACK_EN_SET;
 258         msr.hi |= ARB_UPPER_QUACK_EN_SET;
 259         wrmsr(msrnum, msr);
 260
 261         msrnum = GLIU1_ARB;
 262         msr = rdmsr(msrnum);
 263         msr.hi &= ~ARB_UPPER_DACK_EN_SET;
 264         msr.hi |= ARB_UPPER_QUACK_EN_SET;
 265         wrmsr(msrnum, msr);
 266
 267         /*      GLIU port active enable, limit south pole masters (AES and PCI) to one outstanding transaction. */
 268         msrnum = GLIU1_PORT_ACTIVE;
 269         msr = rdmsr(msrnum);
 270         msr.lo &= ~0x880;
 271         wrmsr(msrnum, msr);
 272
 273         /* Set the Delay Control in GLCP */
 274         SetDelayControl();
 275
 276 /*  Enable RSDC*/
 277         msrnum = CPU_AC_SMM_CTL;
 278         msr = rdmsr(msrnum);
 279         msr.lo |= SMM_INST_EN_SET;
 280                 wrmsr(msrnum, msr);
 281
 282
 283         /* FPU imprecise exceptions bit */
 284                 msrnum = CPU_FPU_MSR_MODE;
 285                 msr = rdmsr(msrnum);
 286                 msr.lo |= FPU_IE_SET;
 287                 wrmsr(msrnum, msr);
 288
 289
 290         /* Power Savers (Do after BIST) */
 291         /* Enable Suspend on HLT & PAUSE instructions*/
 292         msrnum = CPU_XC_CONFIG;
 293                 msr = rdmsr(msrnum);
 294         msr.lo |= XC_CONFIG_SUSP_ON_HLT |  XC_CONFIG_SUSP_ON_PAUSE;
 295                 wrmsr(msrnum, msr);
 296
 297         /* Enable SUSP and allow TSC to run in Suspend (keep speed detection happy) */
 298         msrnum = CPU_BC_CONF_0;
 299                 msr = rdmsr(msrnum);
 300         msr.lo |= TSC_SUSP_SET | SUSP_EN_SET;
 301         msr.lo &= 0x0F0FFFFFF;
 302         msr.lo |= 0x002000000;   /* PBZ213: Set PAUSEDLY = 2 */
 303                 wrmsr(msrnum, msr);
 304
 305         /* Disable the debug clock to save power.*/
 306         /* NOTE: leave it enabled for fs2 debug */
 307 /*      msrnum = GLCP_DBGCLKCTL;
 308         msr.hi = 0;
 309         msr.lo = 0;
 310         wrmsr(msrnum, msr);
 311 */
 312
 313         /* Setup throttling delays to proper mode if it is ever enabled. */
 314         msrnum = GLCP_TH_OD;
 315         msr.hi = 0;
 316         msr.lo = 0x00000603C;
 317                 wrmsr(msrnum, msr);
 318         }