2 * This file is part of the coreboot project.
4 * Copyright (C) 2006 Indrek Kruusa <indrek.kruusa@artecdesign.ee>
5 * Copyright (C) 2006 Ronald G. Minnich <rminnich@gmail.com>
6 * Copyright (C) 2007 Advanced Micro Devices, Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
23 /**************************************************************************
27 ;*************************************************************************/
28 static void SetDelayControl(void)
30 unsigned int msrnum, glspeed;
31 unsigned char spdbyte0, spdbyte1;
34 glspeed = GeodeLinkSpeed();
36 /* fix delay controls for DM and IM arrays */
37 msrnum = CPU_BC_MSS_ARRAY_CTL0;
42 msrnum = CPU_BC_MSS_ARRAY_CTL1;
47 msrnum = CPU_BC_MSS_ARRAY_CTL2;
52 msrnum = GLCP_FIFOCTL;
58 msrnum = CPU_BC_MSS_ARRAY_CTL_ENA;
63 /* Debug Delay Control Setup Check
64 Leave it alone if it has been setup. FS2 or something is here. */
65 msrnum = GLCP_DELAY_CONTROLS;
67 if (msr.lo & ~(0x7C0)) {
72 * Delay Controls based on DIMM loading. UGH!
73 * # of Devices = Module Width (SPD6) / Device Width(SPD13) * Physical Banks(SPD5)
74 * Note - We only support module width of 64.
76 spdbyte0 = spd_read_byte(DIMM0, SPD_PRIMARY_SDRAM_WIDTH);
77 if (spdbyte0 != 0xFF) {
78 spdbyte0 = (unsigned char)64 / spdbyte0 *
79 (unsigned char)(spd_read_byte(DIMM0, SPD_NUM_DIMM_BANKS));
84 spdbyte1 = spd_read_byte(DIMM1, SPD_PRIMARY_SDRAM_WIDTH);
85 if (spdbyte1 != 0xFF) {
86 spdbyte1 = (unsigned char)64 / spdbyte1 *
87 (unsigned char)(spd_read_byte(DIMM1, SPD_NUM_DIMM_BANKS));
92 /* The current thinking. Subject to change...
94 ; "FUTURE ROBUSTNESS" PROPOSAL
95 ; ----------------------------
96 ; DIMM Max MBUS MC 0x2000001A bits 26:24
97 ;DIMMs devices Frequency MCP 0x4C00000F Setting vvv
98 ;----- ------- --------- ---------------------- ----------
99 ;1 4 400MHz 0x82*100FF 0x56960004 4
100 ;1 8 400MHz 0x82*100AA 0x56960004 4
101 ;1 16 400MHz 0x82*10055 0x56960004 4
103 ;2 4,4 400MHz 0x82710000 0x56960004 4
105 ;1 4 <=333MHz 0x83*100FF 0x56960004 3
106 ;1 8 <=333MHz 0x83*100AA 0x56960004 3
107 ;1 16 <=333MHz 0x83*100AA 0x56960004 3
109 ;2 4,4 <=333MHz 0x837100A5 0x56960004 3
110 ;2 8,8 <=333MHz 0x937100A5 0x56960004 3
112 ;=========================================================================
113 ;* - Bit 55 (disable SDCLK 1,3,5) should be set if there is a single DIMM in slot 0,
114 ; but it should be clear for all 2 DIMM settings and if a single DIMM is in slot 1.
115 ; Bits 54:52 should always be set to '111'.
118 ;-------------------------------------
119 ;ADDR/CTL have 22 ohm series R
120 ;DQ/DQM/DQS have 33 ohm series R
123 ;DIMMs devices Frequency MCP 0x4C00000F Setting
124 ;----- ------- --------- ----------------------
125 ;1 4 400MHz 0xF2F100FF 0x56960004 4 The No VTT changes improve timing.
126 ;1 8 400MHz 0xF2F100FF 0x56960004 4
127 ;1 4 <=333MHz 0xF2F100FF 0x56960004 3
128 ;1 8 <=333MHz 0xF2F100FF 0x56960004 3
129 ;1 16 <=333MHz 0xF2F100FF 0x56960004 3
133 if (spdbyte0 == 0 || spdbyte1 == 0) {
134 /* one dimm solution */
136 msr.hi |= 0x000800000;
138 spdbyte0 += spdbyte1;
142 msr.hi |= 0x0837100AA;
143 msr.lo |= 0x056960004;
145 msr.hi |= 0x082710055;
146 msr.lo |= 0x056960004;
148 } else if (spdbyte0 > 4) {
151 msr.hi |= 0x0837100AA;
152 msr.lo |= 0x056960004;
154 msr.hi |= 0x0827100AA;
155 msr.lo |= 0x056960004;
160 msr.hi |= 0x0837100FF;
161 msr.lo |= 0x056960004;
163 msr.hi |= 0x0827100FF;
164 msr.lo |= 0x056960004;
168 /* two dimm solution */
169 spdbyte0 += spdbyte1;
173 msr.hi |= 0x0B37100A5;
174 msr.lo |= 0x056960004;
176 msr.hi |= 0x0B2710000;
177 msr.lo |= 0x056960004;
179 } else if (spdbyte0 > 16) {
182 msr.hi |= 0x0B37100A5;
183 msr.lo |= 0x056960004;
185 msr.hi |= 0x0B27100A5;
186 msr.lo |= 0x056960004;
188 } else if (spdbyte0 >= 8) {
191 msr.hi |= 0x0937100A5;
192 msr.lo |= 0x056960004;
194 msr.hi |= 0x0C27100A5;
195 msr.lo |= 0x056960004;
200 msr.hi |= 0x0837100A5;
201 msr.lo |= 0x056960004;
203 msr.hi |= 0x082710000;
204 msr.lo |= 0x056960004;
208 print_debug("Try to write GLCP_DELAY_CONTROLS: hi ");
209 print_debug_hex32(msr.hi);
210 print_debug(" and lo ");
211 print_debug_hex32(msr.lo);
213 wrmsr(GLCP_DELAY_CONTROLS, msr);
214 print_debug("SetDelayControl done\n");
218 /* ***************************************************************************/
220 /* ***************************************************************************/
221 void cpuRegInit(void)
226 /* Castle 2.0 BTM periodic sync period. */
227 /* [40:37] 1 sync record per 256 bytes */
228 print_debug("Castle 2.0 BTM periodic sync period.\n");
229 msrnum = CPU_PF_CONF;
231 msr.hi |= (0x8 << 5);
235 * LX performance setting.
236 * Enable Quack for fewer re-RAS on the MC
238 print_debug("Enable Quack for fewer re-RAS on the MC\n");
241 msr.hi &= ~ARB_UPPER_DACK_EN_SET;
242 msr.hi |= ARB_UPPER_QUACK_EN_SET;
247 msr.hi &= ~ARB_UPPER_DACK_EN_SET;
248 msr.hi |= ARB_UPPER_QUACK_EN_SET;
251 /* GLIU port active enable, limit south pole masters
252 * (AES and PCI) to one outstanding transaction.
254 print_debug(" GLIU port active enable\n");
255 msrnum = GLIU1_PORT_ACTIVE;
260 /* Set the Delay Control in GLCP */
261 print_debug("Set the Delay Control in GLCP\n");
265 print_debug("Enable RSDC\n");
266 msrnum = CPU_AC_SMM_CTL;
268 msr.lo |= SMM_INST_EN_SET;
271 /* FPU imprecise exceptions bit */
272 print_debug("FPU imprecise exceptions bit\n");
273 msrnum = CPU_FPU_MSR_MODE;
275 msr.lo |= FPU_IE_SET;
278 /* Power Savers (Do after BIST) */
279 /* Enable Suspend on HLT & PAUSE instructions */
280 print_debug("Enable Suspend on HLT & PAUSE instructions\n");
281 msrnum = CPU_XC_CONFIG;
283 msr.lo |= XC_CONFIG_SUSP_ON_HLT | XC_CONFIG_SUSP_ON_PAUSE;
286 /* Enable SUSP and allow TSC to run in Suspend (keep speed detection happy) */
287 print_debug("Enable SUSP and allow TSC to run in Suspend\n");
288 msrnum = CPU_BC_CONF_0;
290 msr.lo |= TSC_SUSP_SET | SUSP_EN_SET;
291 msr.lo &= 0x0F0FFFFFF;
292 msr.lo |= 0x002000000; /* PBZ213: Set PAUSEDLY = 2 */
295 /* Disable the debug clock to save power. */
296 /* NOTE: leave it enabled for fs2 debug */
298 msrnum = GLCP_DBGCLKCTL;
304 /* Setup throttling delays to proper mode if it is ever enabled. */
305 print_debug("Setup throttling delays to proper mode\n");
308 msr.lo = 0x00000603C;
310 print_debug("Done cpuRegInit\n");